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| iop 480 data book
iop 480 data book revision 2.0 july 2000 website : http://www.plxtech.com email : apps@plxtech.com phone : 408 774-9060 800 759-3735 fax : 408 774-2169 ? 2000 plx technology, inc. all rights reserved. plx technology, inc. retains the right to make changes to this product at any time, without notice. products may have minor variations to this publication, known as errata. plx assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of plx products. plx technology and the plx logo are registered trademarks and data pipe architecture is a trademark of plx technology, inc. other brands and names are the property of their respective owners. order number: iop 480-sil-db-p1-2.0 printed in the usa, july 2000 iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. v contents figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxiii preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxvii supplemental documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxvii terms and definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxviii revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxviii 1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1. highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2.1. powerpc risc processor core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2.2. on-chip peripheral logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2.2.1. advanced data pipe architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2.2.2. memory controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.2.3. arbiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.3. jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.4. programmable interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.5. local bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.6. programmable chip selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.7. serial port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.8. data transfer mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.3. company and product background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.3.1. iop 480 i/o processor general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.3.2. development tool support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4. applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4.1. pci adapter cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4.2. pci host embedded systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.4.3. high-performance pci i 2 o design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.4.4. high-performance compactpci adapter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.4.4.1. hot swap capable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4.4.2. hot swap friendly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4.5. real time application design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4.6. data communications design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 2. local bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1. transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.2. basic bus states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2. local signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3. local bus signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3.1. clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 contents iop 480 data book r2.0 vi ? 2000 plx technology, inc. all rights reserved. 2.4. bus regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.4.1. address/data/parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.4.1.1. lad[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.4.1.2. dp[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4.2. control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4.2.1. ads# and ale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4.2.2. lbe[3:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4.2.3. lwr# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4.2.4. blast# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4.2.5. ready# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4.2.6. bterm# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.4.2.7. wait# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4.2.8. llock# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4.3. arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4.3.1. boff# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4.3.2. lholdreq0/lholdack and lholdreq1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4.3.3. lholdack0/ldreq and lholdack1/breq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4.4. local chip selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.5. local bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.5.1. basic bus accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.5.2. wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.5.3. bus and control signals during recovery and idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.5.4. burst transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.6. bus region descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.6.1. direct slave or dma burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2.6.2. wait state control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.7. endian swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.7.1. direct master or configuration register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.7.2. direct slave or dma access endian swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.7.3. endian swapping example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.7.4. internal iop 480 cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.7.4.1. big endian (internal cpu setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.7.4.1.1. big endian cycle timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.7.4.2. little endian (internal cpu setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.8. bus width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.9. data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.9.1. iop 480 as a local bus slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.9.2. iop 480 as a local bus master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.10. bus accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.10.1. data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 3. pci bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2. direct slave command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.3. pci master command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.3.1. dma master command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.3.2. direct local-to-pci command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.4. pci signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.4.1. pci signal timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.5. pci bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.6. bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 contents iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. vii 4. direct slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1. direct slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.2. direct slave operation (pci master-to-local bus access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2. registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2.1. pci bus access to internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2.2. direct slave pci-to-local address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.2.1. direct slave local bus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.2.2. direct slave pci initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3. internal fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.4. exclusive accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.5. pci r2.2 delayed read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.6. pci read ahead mode (pcictl[22]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.7. direct slave transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.8. local bus byte enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.9. direct slave priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.10. alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.11. direct slave example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.12. timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.12.1. direct slave configuration cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.12.2. direct slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.12.3. direct slave burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 5. direct master operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1. direct master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.2. direct master operation (local master-to-direct slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.2.1. direct master memory and i/o decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.3. pci command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2. internal fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3. pci memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.4. pci i/o access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.5. pci configuration access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.5.1. configuration cycle example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.6. pci dual address cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.7. target abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.8. memory write and invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.9. deadlock conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.9.1. backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.9.2. software/hardware solution for systems without backoff capability . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 7 5.9.3. software solution to deadlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.10. timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.10.1. direct master configuration cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.10.2. direct master operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 6. iop 480 cpu bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2. initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.3. accessing the spu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.4. accessing the local bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.4.1. internal iop 480 cpu burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.4.1.1. loads and stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.4.1.2. cache line fills/flushes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.5. accessing the pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 contents iop 480 data book r2.0 viii ? 2000 plx technology, inc. all rights reserved. 6.6. alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.7. timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.7.1. iop 480 cpu bootup cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 7. dma operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1. dma channels 0 and 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.2. pci dual address cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.3. block dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.1.4. scatter/gather dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.1.5. local-to-pci transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.1.6. pci-to-local transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.1.7. demand mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.1.8. demand mode/fast terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.1.9. local bus eot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.1.10. dma abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.1.11. local bus latency and pause timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.1.12. dma unaligned transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.1.13. pci memory write and invalidate (mwi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.1.14. dma descriptor ring management (valid mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.1.15. dma priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.1.16. local bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.1.17. pci bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.1.18. dma local bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.1.18.1. local latency and pause timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.1.18.2. dram refresh timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.1.18.3. local arbiter priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.1.19. dma master command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.2. dma channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.2.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.2.2. dma register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.2.2.1. access from the local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.2.2.2. access from the primary pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.2.3. local-to-local mode dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.2.4. demand mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 7.2.5. fast terminate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 7.2.6. dma abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 7.2.7. flyby dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 7.2.8. local bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.2.9. dma unaligned transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.2.10. dma local bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.2.10.1. local bus latency and pause timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.2.10.2. dram refresh timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.2.10.3. local arbiter priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.3. timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 8. local bus internal arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2. initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.3. round-robin mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.4. high-priority mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.5. performance tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.6. timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 contents iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. ix 9. pci bus internal arbiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2. initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.3. priority mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.3.1. priority and round-robin modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.4. grant on idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.5. park on iop 480 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.6. performance tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 10. reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2. power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.3. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.3.1. adapter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.3.1.1. pci reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.3.1.2. software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.3.1.3. power management reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.3.1.4. local reset# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.3.1.5. iop 480 cpu chip reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.3.2. host mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.3.2.1. pci reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.3.2.2. local reset# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.3.2.3. software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.3.2.4. power management reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.3.3. iop 480 cpu chip reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.4. serial eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.4.1. iop 480 initialization from the local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.4.2. serial eeprom load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.4.3. selectively accessing the serial eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.4.4. iop 480 initialization without a serial eeprom or with a blank eeprom . . . . . . . . . . . . . . . . . . . . 10-3 10.5. iop 480 cpu boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.5.1. processor state after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.5.2. iop 480 cpu initial processor sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.5.3. initialization requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10.6. initialization code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10.7. dram initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10.7.1. iop 480 initialization from pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 11. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2. pci interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2.1. local-to-pci doorbell interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2.2. local interrupt input (inti) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2.3. master/target abort interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2.4. dma pci interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2.5. messaging unit outbound post queue interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2.6. 256 consecutive pci retries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2.7. pci interrupt output (inta#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.3. pci system error output (serr#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.4. local interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.4.1. mailbox interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.4.2. pci enumerate input (enum#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.4.3. pci power management event input (pme#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.4.4. pci interrupt input (inta#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 contents iop 480 data book r2.0 x ? 2000 plx technology, inc. all rights reserved. 11.4.5. pci system error input (serr#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.4.6. power management interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.4.7. built-in self test interrupt (bist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.4.8. pci-to-local doorbell interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.4.9. dma local interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.4.10. local interrupt input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.4.11. local bus parity error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.4.12. serial port interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.4.13. local bus timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.4.14. pci bus parity errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.4.15. messaging unit outbound free queue overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1-5 11.4.16. messaging unit inbound post queue interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.4.17. master/target abort interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.4.18. cint critical interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.4.19. refresh interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.4.20. local interrupt output (into) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.5. doorbell registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.6. mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.7. iop 480 exceptions, interrupts, and timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.7.1. interrupts and exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.7.1.1. architectural definitions and behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.7.1.2. iop 480 cpu implementation behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.7.1.3. exception-handling priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.7.2. critical and non-critical exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.7.3. general exception handling registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.7.3.1. machine state register (msr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.7.3.2. save/restore registers 0 and 1 (srr0?srr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 5 11.7.3.3. save/restore registers 2 and 3 (srr2?srr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 5 11.7.3.4. exception vector prefix register (evpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 11.7.3.5. exception syndrome register (esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 11.7.3.6. data exception address register (dear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 11.7.4. critical interrupt exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 11.7.5. machine check exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20 11.7.5.1. instruction machine check handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20 11.7.5.2. data machine check handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 11.7.6. data storage exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 11.7.7. instruction storage exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22 11.7.8. external interrupt exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 11.7.8.1. external interrupt exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 11.7.9. alignment exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 11.7.10. program exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 11.7.11. system call exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 11.7.12. programmable interval timer (pit) exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 11.7.13. fixed interval timer (fit) exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 11.7.14. watchdog timer exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 11.7.15. data tlb miss exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 11.7.16. instruction tlb miss exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 11.7.17. debug exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 11.7.18. timer facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 11.7.18.1. time base. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 11.7.18.2. programmable interval timer (pit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 11.7.18.3. fixed interval timer (fit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 11.7.18.4. watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 11.7.18.5. timer status register (tsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35 11.7.18.6. timer control register (tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-36 contents iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. xi 12. memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2. sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2.1. control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2.2. address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2.3. parity checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2.4. boot prom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.2.5. sram examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.2.6. sram write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.2.7. sram read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 12.3. dram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 12.3.1. synchronous dram (sdram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 12.3.1.1. sdram signal connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 12.3.1.2. sdram example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 12.3.1.3. sdram addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 12.3.1.4. sdram initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 12.3.1.4.1. burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 12.3.1.4.2. burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 12.3.1.4.3. cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 12.3.1.4.4. operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 12.3.1.4.5. write burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 12.3.1.5. sdram commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17 12.3.1.5.1. command inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17 12.3.1.5.2. no operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.3.1.5.3. active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.3.1.5.4. read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.3.1.5.5. write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.3.1.5.6. burst terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.3.1.5.7. precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.3.1.5.8. auto-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.3.1.5.9. auto-refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.3.1.5.10. self-refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.3.1.6. operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.3.1.6.1. page mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18 12.3.1.6.2. parity checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 12.3.1.6.3. burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 12.3.1.6.4. auto-refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 12.3.1.6.5. self-refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 12.3.1.6.6. sdram initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22 12.3.1.6.7. sdram write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22 12.3.1.6.8. sdram read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32 12.3.2. edo dram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39 12.3.2.1. edo signal connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39 12.3.2.2. edo dram examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39 12.3.2.3. edo addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-40 12.3.2.4. initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-42 12.3.2.5. refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-42 12.3.2.6. page mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-42 12.3.2.7. edo write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-42 12.3.2.8. edo read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-48 12.4. signal loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-53 12.4.1. sdrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-53 12.4.2. edo drams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-53 12.5. overlapping address spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-53 contents iop 480 data book r2.0 xii ? 2000 plx technology, inc. all rights reserved. 13. intelligent i/o (i 2 o) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.2. registers used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.3. inbound messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.4. outbound messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.5. i 2 o pointer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.6. inbound free queue fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.7. inbound post queue fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.8. outbound post queue fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.9. outbound free queue fifo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.10. i 2 o enable sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.11. performance tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.11.1. pull option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.11.2. outbound option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.12. timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 14. compactpci hot swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.2. controlling connection processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.2.1. hardware connection control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.2.1.1. board slot control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.2.1.2. board healthy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.2.1.3. platform reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.2.2. software connection control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.2.2.1. ejector switch and blue led . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.2.2.2. enum# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.2.2.3. hot swap control/status register (hscsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.2.2.3.1. hot swap capabilities register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 15. vital product data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.2. vpd registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.2.1. vpd registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.3. serial eeprom vpd partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.4. sequential read area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.5. random read and write area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.6. timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 16. power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.3. system changes power mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.4. wake-up request example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.5. power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 contents iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. xiii 17. register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1. internal register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.2. register address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2.1. configuration register base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2.2. pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.2.3. messaging queue registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.4. local configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.2.5. memory controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17.2.6. runtime registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 17.2.7. dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 17.2.8. serial eeprom loading sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 17.3. pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.4. messaging queue registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21 17.5. local configuration registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-26 17.6. memory controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-38 17.7. runtime registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-56 17.8. dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-63 18. iop 480 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 19. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.1. i/o timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 20. package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.1. 208-pin pqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.1.1. 208-pin pqfp package mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.1.2. 208-pin pqfp pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.1.3. 208-pin pqfp package materials and properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.1.4. 208-pin pqfp printed circuit board (pcb) assembly compatibility . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.2. 225-pin pbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.2.1. 225-pin pbga package mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.2.2. 225-pin pbga suggested land pattern for pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 20.2.3. 225-pin pbga package layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.2.4. 225-pin pbga pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 20.2.5. 225-pin pbga package materials and properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 20.2.6. 225-pin pbga printed circuit board (pcb) assembly compatibility . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 20.2.7. 225-pin pbga die attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 20.2.8. 225-pin pbga encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 21. timing diagrams reference list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 22. serial port operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.2. spu operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.2.1. normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.2.2. internal loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.2.3. automatic echo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 contents iop 480 data book r2.0 xiv ? 2000 plx technology, inc. all rights reserved. 22.3. spu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.4. spu operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.4.1. spu baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.4.2. spu transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.4.2.1. pattern generation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.4.2.2. transmitter line break generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.4.2.3. transmitter interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.4.3. spu receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.4.3.1. receiver interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.5. spu register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.5.1. baud rate divisor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.5.2. serial port control register (spctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.5.3. serial port handshake status register (sphs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.5.4. serial port line status register (spls) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.5.5. serial port receive buffer (sprb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22.5.6. serial port receiver command register (sprc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22.5.7. serial port transmit buffer (sptb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22.6. serial port transmit command register (sptc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22.7. initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 22.7.1. initializing spu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 22.7.2. enabling normal spu operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 23. iop 480 cpu overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1.1. powerpc risc fixed-point cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1.2. storage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1.3. memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.2. powerpc architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.3. iop 480 cpu as powerpc implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.4. iop 480 cpu organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.4.1. risc processor core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.4.2. instruction and data cache controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 23.4.2.1. instruction cache unit (icu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 23.4.2.2. data cache unit (dcu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 23.4.3. timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.4.4. memory management unit (mmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.4.5. debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.4.5.1. development tool support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.4.5.2. debug modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.4.5.3. plb (processor local bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7 23.4.5.4. jtag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7 23.4.5.5. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7 23.4.6. data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7 23.4.7. register set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7 23.4.7.1. general purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7 23.4.7.2. special purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7 23.4.7.3. machine state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8 23.4.7.4. condition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8 23.4.7.5. device control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8 23.4.8. addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8 contents iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. xv 24. iop 480 cpu programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.1. memory organization and addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.1.1. storage attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.2. registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.2.1. general purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.2.2. special purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.2.2.1. count register (ctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.2.2.2. link register (lr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.2.2.3. fixed point exception register (xer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.2.2.3.1. xer[so] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 24.2.2.3.2. xer[ov] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 24.2.2.3.3. xer[ca] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 24.2.2.3.4. xer[tbc] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 24.2.2.4. special purpose register general (sprg0-sprg3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24- 6 24.2.2.5. processor version register (pvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 24.2.3. condition register (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7 24.2.3.1. cr fields after compare instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8 24.2.3.2. cr0 field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8 24.2.4. time base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 24.2.5. machine state register (msr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 24.2.6. device control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24.3. data types and alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24.3.1. alignment for storage reference and cache control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24.3.2. alignment and endian operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 24.3.3. instructions causing alignment exceptions summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 24.4. byte ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13 24.4.1. structure mapping examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13 24.4.1.1. big-endian mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.4.2. powerpc byte ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.4.3. powerpc endian mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.4.3.1. byte ordering in powerpc little endian mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.4.3.2. control of powerpc endian mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16 24.4.3.3. addressing in powerpc little endian mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16 24.4.3.4. little endian mode alignment requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-17 24.4.3.5. switching endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-17 24.4.3.6. direct memory access in powerpc little endian mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-17 24.4.4. endian storage attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-18 24.4.4.1. fetching instructions from little endian storage regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 -18 24.4.4.2. accessing data in little endian storage regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-18 24.4.4.3. endian storage attribute control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19 24.4.4.4. powerpc byte-reverse instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19 24.5. instruction processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-21 24.6. branching control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-21 24.6.1. aa field on unconditional branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-21 24.6.2. aa field on conditional branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-22 24.6.3. bi field on conditional branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-22 24.6.4. bo field on conditional branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-22 24.6.5. branch prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-23 24.7. speculative accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24 24.7.1. speculative accesses in iop 480 cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-24 24.7.1.1. prefetch distance down an unresolved branch path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 4 24.7.1.2. prefetch of branches to count register and branches to link register . . . . . . . . . . . . . . . . . . 24-25 24.7.2. preventing inappropriate speculative accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-25 24.7.2.1. fetching past an interrupt-causing or interrupt-returning instruction . . . . . . . . . . . . . . . . . . . . 24-26 24.7.2.2. fetching past tw or twi instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26 24.7.2.3. fetching past an unconditional branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26 24.7.2.4. suggested locations of memory-mapped hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26 24.7.3. summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27 contents iop 480 data book r2.0 xvi ? 2000 plx technology, inc. all rights reserved. 24.8. privileged mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27 24.8.1. msr bits and exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27 24.8.2. privileged instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28 24.8.3. privileged sprs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28 24.8.4. privileged dcrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28 24.9. synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28 24.9.1. context synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-29 24.9.2. execution synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-30 24.9.3. storage synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-31 24.10. instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-31 24.10.1. instructions specific to ibm powerpc embedded controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24- 31 24.10.2. storage reference instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-31 24.10.3. arithmetic and logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-33 24.10.4. compare instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-33 24.10.5. branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-33 24.10.6. condition register logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-33 24.10.7. rotate and shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-33 24.10.8. cache control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-34 24.10.9. interrupt control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-34 24.10.10. tlb management instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-34 24.10.11. processor management instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-34 24.10.12. extended mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-34 25. iop 480 cpu cache operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25.1. icu and dcu organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25.2. icu overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.2.1. instruction cacheability control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 25.2.2. icu coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.2.3. dcu overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.2.4. dcu write strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.2.5. data cacheability control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.2.6. dcu coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.3. cache instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.3.1. icu instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6 25.3.2. idcu instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6 25.4. cache control and debugging features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 25.4.1. icu debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 25.4.2. dcu debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10 25.5. cache line locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11 25.5.1. locking lines in the icu and dcu cache arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11 25.5.2. unlocking lines in the icu and dcu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11 25.6. dcu performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.6.1. pipeline stalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.6.2. cache operation priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13 25.6.3. simultaneous cache operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13 25.6.4. sequential cache operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13 25.6.5. core clock frequency and write data acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14 25.7. icu and dcu performance modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14 contents iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. xvii 26. iop 480 cpu debugging and jtag facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.1. development tool support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.2. debug modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.2.1. internal debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.2.2. external debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.3. processor control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.4. processor status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.5. debug events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.6. debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.6.1. debug control register (dbcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3 26.6.1.1. dac compare size field (dbcr[d1s]) note. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5 26.6.2. debug status register (dbsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5 26.6.3. data address compare register (dac1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.6.3.1. data address compare (dac) applied to cache instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.6.3.2. dac applied to string instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8 26.6.4. instruction address compare register (iac1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8 26.7. debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8 26.7.1. ieee 1149.1 test access port (jtag debug port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8 26.7.1.1. jtag connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8 26.7.1.2. jtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9 26.7.1.3. jtag boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-10 27. iop 480 cpu memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.2. address translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.3. translation lookaside buffer (tlb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.3.1. unified tlb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.3.2. unified tlb fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 27.3.3. page identification fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 27.3.3.1. translation field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 27.3.3.2. access control fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 27.3.3.3. storage attribute fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 27.3.4. shadow instruction tlb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5 27.3.4.1. itlb accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5 27.3.4.2. itlb consistency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 27.4. tlb-related exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7 27.4.1. data storage exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7 27.4.2. instruction storage exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7 27.4.3. data tlb miss exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7 27.4.4. instruction tlb miss exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.4.5. program exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.5. tlb management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.5.1. tlb search instructions (tlbsx/tlbsx.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.5.2. tlb read/write instructions (tlbre/tlbwe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.5.3. tlb invalidate instruction (tlbia) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.5.4. tlb sync instruction (tlbsync) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.6. recording page references and changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.7. access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.7.1. access protection mechanisms in the tlb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.7.1.1. general access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.7.1.2. execute permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10 27.7.1.3. write permissions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10 27.7.1.4. zone protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10 27.7.2. access protection for cache instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-11 27.7.3. access protection for string instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-12 27.8. real-mode storage attribute control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-13 contents iop 480 data book r2.0 xviii ? 2000 plx technology, inc. all rights reserved. 28. iop 480 cpu instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.1. instruction set portability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.2. instruction formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.3. pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.4. register usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 28.5. alphabetical instruction listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 29. iop 480 cpu register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.1. reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.2. reserved fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.3. general purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.4. machine state register and condition register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.5. special purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.6. device control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 29.7. alphabetical register listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 a. iop 480 cpu instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 a.1. instruction set and extended mnemonics ? alphabetical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 a.2. instructions sorted by opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-30 a.3. instruction formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-36 b. iop 480 cpu instructions by category . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 b.1. instruction set summary categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 b.2. instructions specific to powerpc embedded controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-2 b.3. privileged instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-4 b.4. assembler extended mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-6 b.5. storage reference instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-23 b.6. arithmetic and logical instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-27 b.7. condition register logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-31 b.8. branch instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-32 b.9. comparison instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-33 b.10. rotate and shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-34 b.11. cache control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-35 b.12. interrupt control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-36 b.13. processor management instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-37 c. real code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-1 d. general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-1 d.1. ordering instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-1 d.2. united states and international representatives, and distributors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-1 d.3. technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-1 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . index-1 iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. xix figures 1-1 iop 480 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 sample pci i/o processor adapter design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1-3 sample pci host embedded system design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1-4 typical i 2 o server/adapter card design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 6 1-5 typical i 2 o embedded system design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1-6 high-performance compactpci adapter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1-7 sample real-time application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1-8 data communication design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 2-1 local bus block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-2 endian swapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 3-1 wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 4-1 direct slave access of local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4-2 direct slave pci specification r2.2 delayed reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4-3 direct slave iop 480 read ahead mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4-4 direct slave write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4-5 direct slave read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 5-1 direct master write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5-2 direct master read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5-3 direct master access of pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 7-1 dma, pci-to-local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7-2 dma, local-to-pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7-3 block dma mode initialization (single address or pci dual address cycle) . . . . . . . . . . . . . . . . . . . . . 7-3 7-4 scatter/gather dma mode initialization (single address cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4 7-5 scatter/gather dma mode initialization (pci dual address cycle). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 -4 7-6 scatter/gather dma mode from pci-to-local bus (arbitration from local bus) . . . . . . . . . . . . . . . . . . . 7-5 7-7 scatter/gather dma mode from local-to-pci bus (arbitration from pci bus) . . . . . . . . . . . . . . . . . . . . 7-5 7-8 local-to-pci bus dma data transfer operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7-9 pci-to-local bus dma data transfer operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7-10 local-to-local dma initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 9-1 priority mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9-2 round-robin mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 11-1 dma, local-to-pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11-2 mailbox and doorbell message passing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11-3 relationship of timer facilities to the base clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 11-4 watchdog timer state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34 12-1 memory block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12-2 sram (two 64k x 16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12-3 sram (four 256k x 8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12-4 flash (one 8-bit device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12-5 sdram (two 4m x 16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 12-6 sdram mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 12-7 edo dram (two 4m x 16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39 12-8 edo dram (four 8m x 8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-40 13-1 typical i 2 o server/adapter card design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13-2 driver architecture compared . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 figures iop 480 data book r2.0 xx ? 2000 plx technology, inc. all rights reserved. 13-3 circular fifo operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 14-1 redirection of bd_sel# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14-2 board healthy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14-3 pci reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 17-1 iop 480 internal register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 19-1 iop 480 ale output delay from the local clock (min/max, in nanoseconds) . . . . . . . . . . . . . . . . . . 19-1 20-1 208-pin pqfp package mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-1 20-2 208-pin pqfp pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20-3 225-pin pbga package mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20-4 20-4 225-pin pbga suggested land pattern for pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 -5 20-5 225-pin pbga underside . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 22-1 serial port functional block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22-2 spu registers and buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 23-1 iop 480 cpu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 24-1 iop 480 cpu data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24-2 normal lword load or store (big endian storage region). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24- 20 24-3 byte-reverse lword load or store (little endian storage region) . . . . . . . . . . . . . . . . . . . . . . . . . 24-20 24-4 byte-reverse lword load or store (big endian storage region). . . . . . . . . . . . . . . . . . . . . . . . . . . 24-20 24-5 normal lword load or store (little endian storage region) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24- 21 24-6 iop 480 cpu instruction queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-22 25-1 instruction flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 26-1 jtag connector physical layout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9 27-1 effective to real address translation flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27-2 tlb entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 27-3 itlb/utlb address resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. xxi tables data assignment conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xxxviii 2-1 dp[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-2 ready data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2-3 burst and bterm on local bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2-4 local arbitration signal directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2-5 registers defining local characteristics of all lcs range accesses . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2-6 burst boundaries with bterm enable=0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 2-7 burst boundaries with bterm enable=1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2-8 endian swapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2-9 endian swapping, lower byte lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2-10 endian swapping, upper byte lanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2-11 iop 480 cpu big endian byte ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2-12 iop 480 cpu little endian byte ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2-13 direct slave local byte enable methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2-14 byte enable and coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2-15 byte lane contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2-16 data transfer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 3-1 direct slave command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-2 dma master command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-3 local-to-pci memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-4 local-to-pci i/o access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-5 local-to-pci configuration access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 4-1 response to fifo full or empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4-2 direct slave local byte enable methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 5-1 local-to-pci memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-2 local-to-pci i/o access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-3 local-to-pci configuration access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-4 response to fifo full or empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 6-1 iop 480 cpu byte load/store transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6-2 three-byte load/store transactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6-3 single-lword load/store transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6-4 four-lword cache line fills/flushes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6-5 iop 480 cpu loads/stores. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6-6 iop 480 cpu cache line fills/flushes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 7-1 dma local burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7-2 dma master command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7-3 stop transfer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 10-1 adapter and host mode resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10-2 serial eeprom guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10-3 serial eeprom load registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10-4 contents of registers after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 11-1 pci interrupts (inta#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11-2 local interrupts (into) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11-3 exception-handling priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11-4 exception vector offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 tables iop 480 data book r2.0 xxii ? 2000 plx technology, inc. all rights reserved. 11-5 esr alteration by various exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 11-6 register settings during critical interrupt exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 11-7 register settings during machine check ? instruction exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20 11-8 register settings during machine check ? data exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 11-9 register settings during data storage exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22 11-10 register settings during instruction storage exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 11-11 register settings during external interrupt exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 11-12 alignment exception summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 11-13 register settings during alignment error exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 11-14 esr usage for program exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 11-15 register settings during program exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 11-16 register settings during system call exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 11-17 register settings during programmable interval timer exceptions . . . . . . . . . . . . . . . . . . . . . . . . 11-26 11-18 register settings during fixed interval timer exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1-26 11-19 register settings during watchdog timer exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1-27 11-20 register settings during data tlb miss exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1-27 11-21 register settings during instruction tlb miss exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1-28 11-22 srr2 during debug exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 11-23 register settings during debug exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 11-24 time base comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 11-25 fit controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 11-26 watchdog timer controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 11-27 watchdog timer state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34 12-1 sram signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12-2 local burst address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12-3 sram write access programmable timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12-4 sram read access programmable timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 12-5 dram control signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 12-6 sdram signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 12-7 16-megabit sdram addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 12-8 64-megabit sdram addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 12-9 sdram page lengths/boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 12-10 sdram commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17 12-11 refresh arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 12-12 auto refresh commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 12-13 sdram write access programmable timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23 12-14 sdram read access programmable timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32 12-15 edo signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39 12-16 edo page lengths/boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-40 12-17 16-megabit edo addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-41 12-18 64-megabit edo addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-41 12-19 refresh arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-42 12-20 edo dram write access programmable timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-43 12-21 edo dram read access programmable timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-48 12-22 sdram signal loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-53 12-23 edo signal loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-53 tables iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. xxiii 12-24 edo timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-54 12-25 overlapping address spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-54 13-1 queue starting address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13-2 circular fifo summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 14-1 hot swap control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 17-1 read/write symbols used in register listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17-2 configuration register base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17-3 pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17-4 messaging queue registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17-5 local configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17-6 memory controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17-7 runtime registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 17-8 dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 17-9 serial eeprom loading sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 18-1 i/o pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18-2 pin type abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18-3 i/o buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18-4 pin configuration control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18-5 pci bus controller with i 2 o interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 18-6 pci arbiter pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18-7 serial eeprom interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18-8 hot swap pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18-9 16450 compatible serial port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18-10 memory controller pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 18-11 iop 480 cpu clock and test/debug pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10 18-12 power, ground and unused pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11 18-13 local bus interface (iop 480 cpu type) pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12 18-14 local bus arbiter pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-17 18-15 local bus interrupt pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-18 19-1 ac electrical characteristics (worst case process, t a =85 c, vcc=3.0v) . . . . . . . . . . . . . . . . . . . . 19-1 19-2 iop 480 local bus driver loading derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19-3 iop 480 pci buffer loading derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19-4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19-5 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19-6 capacitance (sample tested only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19-7 package thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19-8 electrical characteristics over operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 20-1 208-pin pqfp mechanical specifications (legend for figure 20-1) . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20-2 package materials and properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20-3 208-pin pqfp pcb assembly compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20-4 225-pin pbga package mechanical specifications (legend for figure 20-3) . . . . . . . . . . . . . . . . . . 20-4 20-5 225-pin pbga pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 20-6 pbga package materials/properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 20-7 pbga typical process conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 21-1 iop 480 timing diagram sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 22-1 spu operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 tables iop 480 data book r2.0 xxiv ? 2000 plx technology, inc. all rights reserved. 22-2 serial port register addresses, names, and access modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22- 3 22-3 baud rate divisor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22-4 tbr/tsre status representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22-5 initialized control register parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 24-1 iop 480 cpu sprs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24-2 xer-updating arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24-3 alignment exception summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 24-4 bits of the bo field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-23 24-5 conditional branch bo field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-23 24-6 example memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-26 24-7 instruction execution privileges and operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-27 24-8 privileged instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-28 24-9 instructions specific to ibm powerpc-embedded controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-31 24-10 iop 480 cpu instruction set functional summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-32 24-11 storage reference instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-32 24-12 arithmetic and logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-32 24-13 compare instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-33 24-14 branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-33 24-15 condition register logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-33 24-16 rotate and shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-33 24-17 cache control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-34 24-18 interrupt control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-34 24-19 tlb management instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-34 24-20 processor management instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-34 25-1 cache array size by core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25-2 icu and dcu cache array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25-3 cache sizes, tag fields, and lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25-4 priority changes with different data cache operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14 25-5 cdbcr[dsd], cdbcr[isd], and effective cache size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15 26-1 debug events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3 26-2 dac applied to cache instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26-3 jtag connector signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9 26-4 jtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9 27-1 tlb fields related to page size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 27-2 process id (pid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27-3 protection applied to cache control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-12 27-4 storage attribute control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-14 28-1 alphabetical instruction listing with page number cross-reference . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28-2 instructions in the ibm powerpc embedded environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28- 4 28-3 operator precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 28-4 extended mnemonics for addi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10 28-5 extended mnemonics for addic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-11 28-6 extended mnemonics for addic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-12 28-7 extended mnemonics for addis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-13 28-8 extended mnemonics for bc, bca, bcl, bcla . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-22 28-9 extended mnemonics for bcctr, bcctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-27 tables iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. xxv 28-10 extended mnemonics for bclr, bclrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-30 28-11 extended mnemonics for cmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-33 28-12 extended mnemonics for cmpi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-34 28-13 extended mnemonics for cmpl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-35 28-14 extended mnemonics for cmpli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-36 28-15 extended mnemonics for creqv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-40 28-16 extended mnemonics for crnor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-42 28-17 extended mnemonics for cror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-43 28-18 extended mnemonics for crxor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-45 28-19 data cache array tag information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-56 28-20 instruction cache array tag information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-69 28-21 extended mnemonics for mfspr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-102 28-22 extended mnemonics for mtcrf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-103 28-23 extended mnemonics for mtspr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-107 28-24 extended mnemonics for nor, nor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-114 28-25 extended mnemonics for or, or. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-115 28-26 extended mnemonics for ori . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-117 28-27 extended mnemonics for rlwimi, rlwimi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-121 28-28 extended mnemonics for rlwinm, rlwinm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-122 28-29 extended mnemonics for rlwnm, rlwnm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-124 28-30 extended mnemonics for subf, subf., subfo, subfo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-149 28-31 extended mnemonics for subfc, subfc., subfco, subfco. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 -150 28-32 extended mnemonics for tlbre . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-158 28-33 extended mnemonics for tlbwe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-162 28-34 extended mnemonics for tw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-165 28-35 extended mnemonics for twi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-168 a-1 iop 480 cpu instruction syntax summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-1 a-2 iop 480 cpu instructions by opcode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-30 b-1 iop 480 cpu instruction set functional summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .b-1 b-2 instructions specific to powerpc-embedded controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-2 b-3 privileged instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-4 b-4 iop 480 cpu extended mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-6 b-5 storage reference instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-23 b-6 arithmetic and logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-27 b-7 condition register logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-31 b-8 branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-32 b-9 comparison instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-33 b-10 rotate and shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-34 b-11 cache control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-35 b-12 interrupt control instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-36 b-13 processor management instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-37 d-1 available packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .d-1 iop 480 data book r2.0 xxvi ? 2000 plx technology, inc. all rights reserved. iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. xxvii registers 11-1 machine state register (msr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11-2 save/restore register 0 (srr0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11-3 save/restore register 1 (srr1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11-4 save/restore register 2 (srr2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11-5 save/restore register 3 (srr3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11-6 exception vector prefix register (evpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 11-7 exception syndrome register (esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 11-8 data exception address register (dear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19 11-9 time base register (tbhi, tbhu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 11-10 time base register (tblo, tblu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 11-11 programmable interval timer (pit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 11-12 timer status register (tsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35 11-13 timer control register (tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-36 14-1 hot swap capabilities register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 15-1 vpd registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 17-1 (pcivid; pci:00h, loc:300h) pci vendor id. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17-2 (pcidid; pci:02h, loc:302h) pci device id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17-3 (pcicr; pci:04h, loc:304h) pci command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17-4 (pcisr; pci:06h, loc:306h) pci status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 17-5 (pcirev; pci:08h, loc:308h) pci revision id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 17-6 (pciccr; pci:09h-0bh, loc:309h-30bh) pci class code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 17-7 (pciclsr; pci:0ch, loc:30ch) pci cache line size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 1 17-8 (pciltr; pci:0dh, loc:30dh) pci latency timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7-11 17-9 (pcihtr; pci:0eh, loc:30eh) pci header type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7-11 17-10 (pcibistr; pci:0fh, loc:30fh) pci built-in self test (bist) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 17-11 (pcibar0; pci:10h, loc:310h) pci base address register for memory accesses to configuration registers and local address space 0. . . . . . . . . . . . . . . . . . 17-12 17-12 (pcibar1; pci:14h, loc:314h) pci base address register for memory accesses to local address space 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 17-13 (pcibar2; pci:18h, loc:318h) pci base address register for memory accesses to local address space 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 17-14 (pcibar3; pci:1ch, loc:31ch) pci base address register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 17-15 (pcibar4; pci:20h, loc:320h) pci base address register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 17-16 (pcibar5; pci:24h, loc:324h) pci base address register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 17-17 (pcicis; pci:28h, loc:328h) pci cardbus cis pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 4 17-18 (pcisvid; pci:2ch, loc:32ch) pci subsystem vendor id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 17-19 (pcisid; pci:2eh, loc:32eh) pci subsystem id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7-14 17-20 (pcierbar; pci:30h, loc:330h) pci expansion rom base . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 17-21 (cap_ptr; pci:34h, loc:334h) capability list pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 -14 17-22 (pciilr; pci:3ch, loc:33ch) pci interrupt line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 17-23 (pciipr; pci:3dh, loc:33dh) pci interrupt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 17-24 (pcimgr; pci:3eh, loc:33eh) pci min_gnt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 17-25 (pcimlr; pci:3fh, loc:33fh) pci max_lat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 17-26 (pmcapid; pci:40h, loc:340h) power management capability id . . . . . . . . . . . . . . . . . . . . . . . 17-15 17-27 (pmnext; pci:41h, loc:341h) power management next capability pointer . . . . . . . . . . . . . . . . 17-15 17-28 (pmc; pci:42h, loc:342h) power management capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 17-29 (pmcsr; pci:44h, loc:344h) power management control/status . . . . . . . . . . . . . . . . . . . . . . . . 17-17 17-30 (pmcsr_bse; pci:46h, loc:346h) pmcsr bridge support extensions . . . . . . . . . . . . . . . . . . . 17-18 17-31 (pmdata; pci:47h, loc:347h) power management data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 registers iop 480 data book r2.0 xxviii ? 2000 plx technology, inc. all rights reserved. 17-32 (pmscale; pci:48h, loc:348h) power management data_scale values . . . . . . . . . . . . . . . . . . 17-18 17-33 (pwrcon; pci:4ch, loc:34ch) power consumed values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 17-34 (pwrdis; pci:50h, loc:350h) power dissipated values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 17-35 (hscapid; pci:54h, loc:354h) hot swap capability id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 17-36 (hsnext; pci:55h, loc:355h) hot swap next capability pointer . . . . . . . . . . . . . . . . . . . . . . . . 17-19 17-37 (hscsr; pci:56h, loc:356h) hot swap control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20 17-38 (vpd_cap; pci:58h, loc:358h) vpd capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 -20 17-39 (vpd_data; pci:5ch, loc:35ch) vpd data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7-20 17-40 (mqcr; pci:00h, loc:00h) messaging queue configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21 17-41 (qbar; pci:04h, loc:04h) queue base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 -21 17-42 (ifhpr; pci:08h, loc:08h) inbound free head pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 1 17-43 (iftpr; pci:0ch, loc:0ch) inbound free tail pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 -22 17-44 (iphpr; pci:10h, loc:10h) inbound post head pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 2 17-45 (iptpr; pci:14h, loc:14h) inbound post tail pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7-22 17-46 (ofhpr; pci:18h, loc:18h) outbound free head pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22 17-47 (oftpr; pci:1ch, loc:1ch) outbound free tail pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23 17-48 (ophpr; pci:20h, loc:20h) outbound post head pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23 17-49 (optpr; pci:24h, loc:24h) outbound post tail pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23 17-50 (qsr; pci:28h, loc:28h) queue status/control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24 17-51 (opqis; pci:30h, loc:30h) outbound post queue interrupt status . . . . . . . . . . . . . . . . . . . . . . . 17-24 17-52 (opqim; pci:34h, loc:34h) outbound post queue interrupt mask . . . . . . . . . . . . . . . . . . . . . . . 17-24 17-53 (iqp; pci:40h) inbound queue port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25 17-54 (oqp; pci:44h) outbound queue port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25 17-55 (hostoutidx; pci:50h, loc:50h) host outbound index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25 17-56 (iopoutidx; pci:54h, loc:54h) iop outbound index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25 17-57 (devinit; pci:80h, loc:80h) device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-26 17-58 (locctl; pci:84h, loc:84h) local bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7-27 17-59 (loctmo; pci:88h, loc:88h) local bus timeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 -28 17-60 (loctmr; pci:8ch, loc:8ch) local bus timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 -28 17-61 (larbr; pci:90h, loc:90h) local/dma arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7-29 17-62 (bigend; pci:94h, loc:94h) big/little endian . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30 17-63 (pcictl; pci:98h, loc:98h) pci bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30 17-64 (las0rr; pci:a0h, loc:a0h) memory-mapped configuration register and local address space 0 range register for pci-to-local bus . . . . . . . . . . . . . . . . . . . . . . . . 17-31 17-65 (las0ba; pci:a4h, loc:a4h) local address space 0 base address (remap) for pci-to-local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-31 17-66 (las1rr; pci:a8h, loc:a8h) local address space 1 range register for pci-to-local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-32 17-67 (las1ba; pci:ach, loc:ach) local address space 1 base address (remap) for pci-to-local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-32 17-68 (las2rr; pci:b0h, loc:b0h) local address space 2 range register for pci-to-local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-33 17-69 (las2ba; pci:b4h, loc:b4h) local address space 2 base address (remap) for pci-to-local bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-33 17-70 (eromrr; pci:c0h, loc:c0h) expansion rom range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-34 17-71 (eromba; pci:c4h, loc:c4h) expansion rom local base address (remap) . . . . . . . . . . . . . . 17-34 17-72 (dmrr; pci:c8h, loc:c8h) local range register for direct master-to-pci . . . . . . . . . . . . . . . . 17-34 17-73 (dmlbam; pci:cch, loc:cch) local bus base address register for direct master-to-pci memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-34 17-74 (dmpbam; pci:d0h, loc:d0h) pci base address (remap) register for direct master-to-pci memory (lower 32 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 5 registers iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. xxix 17-75 (dmdac; pci:d4h, loc:d4h) direct master dual address cycle upper address. . . . . . . . . . . . . 17-36 17-76 (dmlbai; pci:d8h, loc:d8h) local base address register for direct master-to-pci io/cfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-36 17-77 (dmcfga; pci:dch, loc:dch) pci configuration address register for direct master-to-pci io/cfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-36 17-78 (cfgba; pci:e0h, loc:e0h) configuration base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-37 17-79 (uartba; pci:e4h, loc:e4h) uart base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-37 17-80 (plxid; pci:e8h, loc:e8h) plx hardcoded configuration id . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-37 17-81 (plxrev; pci:ech, loc:ech) plx hardcoded revision id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-37 17-82 (lcs0brd; pci:100h, loc:100h) lcs0 bus region descriptor . . . . . . . . . . . . . . . . . . . . . . . . . 17-38 17-83 (lcs0wt; pci:104h, loc:104h) lcs0 write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 9 17-84 (lcs0rt; pci:108h, loc:108h) lcs0 read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 0 17-85 (lcs0base; pci:10ch, loc:10ch) lcs0 base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-40 17-86 (lcs0range; pci:110h, loc:110h) lcs0 range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-40 17-87 (lcs1brd; pci:114h, loc:114h) lcs1 bus region descriptor . . . . . . . . . . . . . . . . . . . . . . . . . 17-41 17-88 (lcs1wt; pci:118h, loc:118h) lcs1 write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 2 17-89 (lcs1rt; pci:11ch, loc:11ch) lcs1 read timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-42 17-90 (lcs1base; pci:120ch, loc:120ch) lcs1 base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-43 17-91 (lcs1range; pci:124h, loc:124h) lcs1 range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-43 17-92 (lcs2brd; pci:128h, loc:128h) lcs2 bus region descriptor . . . . . . . . . . . . . . . . . . . . . . . . . 17-43 17-93 (lcs2wt; pci:12ch, loc:12ch) lcs2 write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-45 17-94 (lcs2rt; pci:130h, loc:130h) lcs2 read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 5 17-95 (lcs2base; pci:134h, loc:134h) lcs2 base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-45 17-96 (lcs2range; pci:138h, loc:138h) lcs2 range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-45 17-97 (lcs3brd; pci:13ch, loc:13ch) lcs3 bus region descriptor . . . . . . . . . . . . . . . . . . . . . . . . 17-46 17-98 (lcs3wt; pci:140h, loc:140h) lcs3 write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 7 17-99 (lcs3rt; pci:144h, loc:144h) lcs3 read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 7 17-100 (lcs3base; pci:148h, loc:148h) lcs3 base address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-48 17-101 (lcs3range; pci:14ch, loc:14ch) lcs3 range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-48 17-102 (drambrd; pci:150h, loc:150h) dram bus region descriptor . . . . . . . . . . . . . . . . . . . . . . . 17-48 17-103 (dramctl; pci:154h, loc:154h) dram control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-50 17-104 (draminit; pci:158h, loc:158h) dram initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 1 17-105 (dramtim; pci:15ch, loc:15ch) dram timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-52 17-106 (drambase; pci:160h, loc:160h) dram base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-53 17-107 (dramrange; pci:164h, loc:164h) dram range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-53 17-108 (dfltbrd; pci:168h, loc:168h) default bus region descriptor . . . . . . . . . . . . . . . . . . . . . . . 17-54 17-109 (mbox0; pci:180h, loc:180h) mailbox 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-56 17-110 (mbox1; pci:184h, loc:184h) mailbox 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-56 17-111 (mbox2; pci:188h, loc:188h) mailbox 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-56 17-112 (mbox3; pci:18ch, loc:18ch) mailbox 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-56 17-113 (mbox4; pci:190h, loc:190h) mailbox 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-56 17-114 (mbox5; pci:194h, loc:194h) mailbox 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-56 17-115 (mbox6; pci:198h, loc:198h) mailbox 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-56 17-116 (mbox7; pci:19ch, loc:19ch) mailbox 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-57 17-117 (p2ldbell; pci:1a0h, loc:1a0h) pci-to-local doorbell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-57 17-118 (l2pdbell; pci:1a4h, loc:1a4h) local-to-pci doorbell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-57 17-119 (pintstat; pci:1b0h, loc:1b0h) pci interrupt status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-58 17-120 (pintenb; pci:1b4h, loc:1b4h) pci interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-59 17-121 (lintstat; pci:1b8h, loc:1b8h) local interrupt status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-60 17-122 (lintenb; pci:1bch, loc:1bch) local interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-61 registers iop 480 data book r2.0 xxx ? 2000 plx technology, inc. all rights reserved. 17-123 (pabtadr; pci:1c0h, loc:1c0h) pci abort address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-62 17-124 (c0mode; pci:200h, loc:200h) channel 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-63 17-125 (c0csr; pci:204h, loc:204h) channel 0 control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-64 17-126 (c0count; pci:208h, loc:208h) channel 0 transfer count . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-64 17-127 (c0pciladr; pci:20ch, loc:20ch) channel 0 pci lower address . . . . . . . . . . . . . . . . . . . . . 17-65 17-128 (c0locadr; pci:210h, loc:210h) channel 0 local address . . . . . . . . . . . . . . . . . . . . . . . . . . 17-65 17-129 (c0descptr; pci:214h, loc:214h) channel 0 descriptor pointer . . . . . . . . . . . . . . . . . . . . . . 17-65 17-130 (c0pcihadr; pci:218h, loc:218h) channel 0 dual address cycle upper address . . . . . . . . . 17-66 17-131 (c0thres; pci:21ch, loc:21ch) channel 0 threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-66 17-132 (c1mode; pci:220h, loc:220h) channel 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-67 17-133 (c1csr; pci:224h, loc:224h) channel 1 control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-68 17-134 (c1count; pci:228h, loc:228h) channel 1 transfer count . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-68 17-135 (c1pciladr; pci:22ch, loc:22ch) channel 1 pci lower address . . . . . . . . . . . . . . . . . . . . . 17-69 17-136 (c1locadr; pci:230h, loc:230h) channel 1 local address . . . . . . . . . . . . . . . . . . . . . . . . . . 17-69 17-137 (c1descptr; pci:234h, loc:234h) channel 1 descriptor pointer . . . . . . . . . . . . . . . . . . . . . . 17-69 17-138 (c1pcihadr; pci:238h, loc:238h) channel 1 dual address cycle upper address . . . . . . . . . 17-69 17-139 (c1thres; pci:23ch, loc:23ch) channel 1 threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-70 17-140 (c2mode; pci:240h, loc:240h) channel 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-71 17-141 (c2csr; pci:244h, loc:244h) channel 2 control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-72 17-142 (c2count; pci:248h, loc:248h) channel 2 transfer count . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-72 17-143 (c2srcadr; pci:24ch, loc:24ch) channel 2 source address . . . . . . . . . . . . . . . . . . . . . . . . 17-72 17-144 (c2destadr; pci:250h, loc:250h) channel 2 destination address. . . . . . . . . . . . . . . . . . . . . 17-72 22-1 baud rate divisor high register (brdh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22-2 baud rate divisor low register (brdl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22-3 serial port control register (spctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22-4 serial port handshake register (sphs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22-5 serial port line status register (spls) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22-6 serial port receive buffer (sprb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22-7 serial port receiver command register (sprc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22-8 serial port transmit buffer (sptb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22-9 serial port transmitter command register (sptc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 24-1 general purpose register (r0-r31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24-2 count register (ctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24-3 link register (lr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24-4 fixed point exception register (xer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24-5 special purpose register general (sprg0-sprg3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4-7 24-6 processor version register (pvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7 24-7 condition register (cr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8 24-8 machine state register (msr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10 25-1 cache debug control register (cdbcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8 25-2 instruction cache debug data register (icdbdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 26-1 debug control register (dbcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26-2 debug status register (dbsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6 26-3 data address compare register (dac1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26-4 instruction address compare register (iac1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8 27-1 zone protection register (zpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-11 29-1 iop 480 cpu general purpose registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29-2 special purpose registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29-3 cache debug control register (cdbcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29-4 condition register (cr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 registers iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. xxxi 29-5 count register (ctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 29-6 data address compare register (dac1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-8 29-7 debug control register (dbcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9 29-8 debug status register (dbsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-11 29-9 data cache cacheability register (dccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-12 29-10 data cache write-thru register (dcwr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14 29-11 data exception address register (dear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-16 29-12 exception syndrome register (esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-17 29-13 exception vector prefix register (evpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-18 29-14 general purpose register (r0-r31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-19 29-15 instruction address compare register (iac1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-20 29-16 instruction cache cacheability register (iccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-21 29-17 instruction cache debug data register (icdbdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-23 29-18 icu tag information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-23 29-19 link register (lr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-24 29-20 machine state register (msr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-25 29-21 process id (pid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-27 29-22 programmable interval timer (pit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-28 29-23 processor version register (pvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-29 29-24 storage guarded register (sgr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-30 29-25 storage compression register (skr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-32 29-26 storage little-endian register (sler) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-34 29-27 special purpose register general (sprg0-sprg3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 6 29-28 save/restore register 0 (srr0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-37 29-29 save/restore register 1 (srr1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-38 29-30 save/restore register 2 (srr2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-39 29-31 save/restore register 3 (srr3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-40 29-32 time base high register (tbhi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-41 29-33 time base high user-mode (tbhu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-42 29-34 time base low register (tblo). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-43 29-35 time base low user-mode (tblu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-44 29-36 timer control register (tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-45 29-37 timer status register (tsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-46 29-38 fixed point exception register (xer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-47 29-39 zone protection register (zpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-48 iop 480 data book r2.0 xxxii ? 2000 plx technology, inc. all rights reserved. iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. xxxiii timing diagrams 2-1 single read/write, 32-bit bus, master=iop 480. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2-2 local bus burst read, delayed with wait#, master=external local bus master . . . . . . . . . . . . . . . . . 2-7 2-3 local bus burst write, delayed with wait#, master=external local bus master . . . . . . . . . . . . . . . . . 2-8 2-4 single read/write with internal wait states, 32-bit bus, master = iop 480 . . . . . . . . . . . . . . . . . . . . . . 2-8 2-5 local bus burst read, 32-bit bus, no wait states, master=iop 480, slave=default space . . . . . . . . 2-9 2-6 local bus burst write, 32-bit bus, no wait states, master=iop 480, slave=default space . . . . . . . . . 2-9 2-7 big endian cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 3-1 direct slave write to 8-bit local bus ? pci signal protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-2 direct slave write of 15 lwords to 32-bit local bus ? pci signal protocol . . . . . . . . . . . . . . . . . . . . . . 3-2 4-1 pci configuration write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4-2 pci configuration read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4-3 pci memory write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4-4 pci memory read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4-5 direct slave write to 32-bit local bus with zero wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4-6 direct slave read from 32-bit local bus with zero wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -13 4-7 direct slave write to 32-bit local bus with one external (ready#) wait state . . . . . . . . . . . . . . . . . 4-14 4-8 direct slave write to 16-bit local bus with one external (ready#) wait state . . . . . . . . . . . . . . . . . 4-15 4-9 direct slave write to 8-bit local bus with one external (ready#) wait state . . . . . . . . . . . . . . . . . . 4-16 4-10 direct slave read from 32-bit local bus with three external (ready#) wait states . . . . . . . . . . . . 4-17 4-11 direct slave read from 32-bit local bus with three internal (wait#) wait states . . . . . . . . . . . . . . 4-18 4-12 direct slave pci write of six lwords to 32-bit local bus, burst disabled . . . . . . . . . . . . . . . . . . . . . 4-19 4-13 direct slave pci write of three lwords to 16-bit local bus, burst disabled . . . . . . . . . . . . . . . . . . . 4-20 4-14 direct slave pci read of six lwords to 32-bit local bus, burst disabled . . . . . . . . . . . . . . . . . . . . . 4-21 4-15 direct slave pci write of six lwords to 32-bit local bus, burst disabled, one external (ready#) wait state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-22 4-16 direct slave pci write of six lwords to 32-bit local bus, local burst enabled, one external (ready#) wait state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-23 4-17 direct slave pci write of six lwords to 16-bit local bus, local burst enabled, one external (ready#) wait state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-24 4-18 direct slave pci write of three lwords to 8-bit local bus, local burst enabled, one external (ready#) wait state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-25 4-19 direct slave pci write of 15 lwords to 32-bit local bus, local burst enabled, one external (ready#) wait state, bterm enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 4-20 direct slave pci write of 15 lwords to 32-bit local bus, local burst enabled, one external (ready#) wait state, bterm disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 4-21 direct slave burst read of five lwords to 32-bit local bus, burst enabled, prefetch counter of 16, zero wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-28 5-1 local master configuration write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5-2 local master configuration read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5-3 direct master single memory write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5-4 direct master single memory read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5-5 direct master i/o write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5-6 direct master i/o read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5-7 direct master burst write of 12 lwords. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5-8 direct master burst read of 12 lwords with wait# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5-9 direct master configuration write type 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 timing diagrams iop 480 data book r2.0 xxxiv ? 2000 plx technology, inc. all rights reserved. 5-10 direct master configuration read type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5-11 direct master pci dual address cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 6-1 iop 480 cpu after reset start address fffffffc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3 7-1 dma from pci-to-local, bterm disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7-2 dma from pci-to-local, bterm enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 7-3 dma demand mode, write from pci-to-local. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 7-4 dma demand mode, write four lwords from pci-to-local . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7 7-5 dma scatter/gather with descriptor on local memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18 7-6 dma scatter/gather with descriptor on pci memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 7-7 dma2 demand mode cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 7-8 dma2 non-flyby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 7-9 dma2 unaligned transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22 7-10 dma2 local-to-local, 8 lwords, 32-bit ram transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-23 7-11 flyby dma2 load data to 32-bit local fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 7-12 flyby dma2 continue ? write data to 32-bit local ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25 7-13 dma write from local-to-pci, local interrupt done bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 7-14 dma write from pci-to-local, pci interrupt done bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 8-1 round-robin priority arbitration (three active requesters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8-2 high-priority arbitration (lholdreq0/lholdack has priority) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 12-1 sram burst write, 32-bit bus; wad=0, wdd=0, wdly=0, whld=0, wrcv=0; master=iop 480 . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12-2 sram burst write, 32-bit bus, 2-1-1-1 wait states, 2 recovery states; wad=2, wdd=1, wdly=0, whld=1, wrcv=2; lcs x brd [19]=1; master=iop 480 . . . . . . . . 12-6 12-3 sram burst write, 32-bit bus, 2-1-1-1 wait states, 1 write enable delay; wad=2, wdd=1, wdly=1, whld=1, wrcv=0; master=iop 480 . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12-4 sram burst write, 32-bit bus, 1 write hold delay; wad=1, wdd=0, wdly=0, whld=1, wrcv=0; master=iop 480 . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12-5 sram burst write, 32-bit bus; wad=0, wdd=0, wdly=0, whld=1, wrcv=0; master=external . . . . . . . . . . . . . . . . . . . . . . . . 12-8 12-6 sram burst read, 32-bit bus, 0 wait states; rad=0, rdd=0, rdlya=0, rdlyd=0, rrcv=0; master=iop 480 . . . . . . . . . . . . . . . . . . . . . . . 12-10 12-7 sram burst read, 32-bit bus, 2-1-1-1 wait states, 2 recovery states; rad=2, rdd=1, rdlya=0, rdlyd=0, rrcv=2; master=iop 480 . . . . . . . . . . . . . . . . . . . . . . . 12-10 12-8 sram burst read, 32-bit bus, 3-2-2-2 wait states, 2 recovery states; rad=3, rdd=2, rdlya=1, rdlyd=1, rrcv=2; master=iop 480 . . . . . . . . . . . . . . . . . . . . . . . 12-11 12-9 sram burst read, 32-bit bus, 0 wait states; rad=0, rdd=0, rdlya=0, rdlyd=0, rrcv=0; master=external local bus master . . . . . . . . . . . . . . . . . . . . . . 12-11 12-10 sdram initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 12-11 sdram auto-refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 12-12 sdram self-refresh start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 12-13 sdram self-refresh end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 12-14 sdram four word non-page mode burst write, 2-0-0-0 wait states; a2c=1, w2w=0, prcg=3; master=iop 480 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23 12-15 sdram page hit burst write, 1-0-0-0 wait states; w2w=0; master=iop 480 . . . . . . . . . . . . . . . 12-24 12-16 sdram page hit burst write, 2-1-1-1 wait states; w2w=1; master=iop 480 . . . . . . . . . . . . . . . 12-25 12-17 sdram page miss burst write, 6-0-0-0 wait states; a2c=1, w2w=0, prcg=2; master=iop 480 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26 12-18 sdram four word non-page mode burst write, 2-0-0-0 wait states; a2c=1, w2w=0, prcg=3; master=external local bus master . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27 timing diagrams iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. xxxv 12-19 sdram page hit burst write, 1-0-0-0 wait states; w2w=0; master=external local bus master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28 12-20 sdram page hit burst write, 2-1-1-1 wait states; w2w=1; master=external local bus master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29 12-21 sdram page miss burst write, 6-0-0-0 wait states; a2c=1, w2w=0, prcg=2; master=external local bus master . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30 12-22 long sdram burst write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31 12-23 sdram non-page mode burst read, 4-0-0-0 wait states; a2c=1, pchg=2; master=iop 480 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 -33 12-24 sdram page hit burst read, 3-0-0-0 wait states; master=iop 480. . . . . . . . . . . . . . . . . . . . . . . 12-34 12-25 sdram page miss burst read, 8-0-0-0 wait states; a2c=1, prcg=2; master=iop 480 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 -35 12-26 sdram non-page mode burst read, 4-0-0-0 wait states; a2c=1, pchg=2; master=external local bus master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36 12-27 sdram page hit burst read, 3-0-0-0 wait states; master=external local bus master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37 12-28 sdram page miss burst read, 8-0-0-0 wait states; a2c=1, pchg=2; master=external local bus master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38 12-29 edo dram refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-43 12-30 edo dram non-page mode burst write, 3-1-1-1 wait states; r2r=1, r2c=2, c2c=1, wcw=1, prcg=3; master=iop 480 . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-44 12-31 edo dram page hit burst write, 1-1-1-1 wait states; c2c=1, wcw=1; master=iop 480. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 -44 12-32 edo dram page hit burst write, 2-2-2-2 wait states; c2c=2, wcw=1; master=iop 480. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 -45 12-33 edo dram page miss burst write, 6-1-1-1 wait states; r2r=1, r2c=2, c2c=1, wcw=1, prcg=3; master=iop 480 . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-45 12-34 edo dram non-page mode burst write, 4-1-1-1 wait states; r2r=1, r2c=2, c2c=1, wcw=1, prcg=3; master=external local bus master. . . . . . . . . . . . . 12-46 12-35 edo dram page hit burst write, 2-1-1-1 wait states; c2c=1, wcw=1; master=external local bus master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-46 12-36 edo dram page hit burst write, 3-2-2-2 wait states; c2c=1, wcw=2; master=external local bus master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-47 12-37 edo dram page miss burst write, 6-1-1-1 wait states; r2r=1, r2c=2, c2c=1, wcw=1, prcg=3; master=external local bus master. . . . . . . . . . . . . 12-47 12-38 edo dram non-page mode burst read, 4-1-1-1 wait states; r2r=1, r2c=2, c2c=1, rcw=1, rrcv=2, prcg=3; master=iop 480 . . . . . . . . . . . . . . . . . . . 12-49 12-39 edo dram page hit burst read, 2-1-1-1 wait states; c2c=1, rcw=1; master=iop 480 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 -49 12-40 edo dram page hit burst read, 3-2-2-2 wait states; c2c=1, rcw=1; master=iop 480 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 -50 12-41 edo dram page miss burst read, 6-1-1-1 wait states; r2r=1, r2c=2, c2c=1, rcw=1, prcg=3; master=iop 480 . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-50 12-42 edo dram non-page mode burst read, 5-1-1-1 wait states; r2r=1, r2c=2, c2c=1, rcw=1, rrcv=2, prcg=3; master=external local bus master . . . . . . . . . . . . . . . . . . 12-51 12-43 edo dram page hit burst read, 3-1-1-1 wait states; c2c=1, rcw=1; master=external local bus master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-51 12-44 edo dram page hit burst read, 3-2-2-2 wait states; c2c=1, rcw=2; master=external local bus master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-52 12-45 edo dram page miss burst read, 7-1-1-1 wait states; r2r=1, r2c=2, c2c=1, rcw=1, rrcv=2, prcg=3; master=external local bus master . . . . . . . . . . . . . . . . . . 12-52 timing diagrams iop 480 data book r2.0 xxxvi ? 2000 plx technology, inc. all rights reserved. 13-1 i 2 o inbound write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13-2 i 2 o outbound write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 15-1 register write to start vpd write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15-2 register read to show completion of vpd read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. xxxvii preface the information contained in this document is subject to change without notice. although an effort has been made to keep the information accurate, there may be misleading or even incorrect statements made herein. supplemental documentation the following is a list of additional documentation to provide the reader with further information: pci local bus specification, revision 2.2 , december 18, 1998 pci special interest group (pci sig) 5440 sw westgate drive #217, portland, or 97221 usa tel: 800 433-5177 (domestic only) or 503 693-6232, fax: 503 693-8344, http://www.pcisig.com pci hot-plug specification, revision 1.0 pci special interest group (pci sig) 5440 sw westgate drive #217, portland, or 97221 usa tel: 800 433-5177 (domestic only) or 503 693-6232, fax: 503 693-8344, http://www.pcisig.com pci bus power management interface specification , revision 1.1 , december 18, 1998 pci special interest group (pci sig) 5440 sw westgate drive #217, portland, or 97221 usa tel: 800 433-5177 (domestic only) or 503 693-6232, fax: 503 693-8344, http://www.pcisig.com picmg 2.1, compactpci hot swap specification, revision 1.0 , august 3, 1998 pci industrial computer manufacturers group (picmg) c/o virtual inc., 401 edgewater place, suite 500, wakefield, ma 01880, usa tel: 781 224-1100, fax: 781 224-1239, http://www.picmg.org intelligent i/o (i 2 o) architecture specification, revision 2.0 , may 1999 i 2 o special interest group (i 2 o sig) 404 balboa street, san francisco, ca 94118, usa tel: 415 750-8352, fax: 415 751-4829, http://www.i2osig.org preface iop 480 data book r2.0 xxxviii ? 2000 plx technology, inc. all rights reserved. terms and definitions direct master external local bus master initiates data write/read to/from the pci bus direct slave external pci bus master initiates data write/read to/from the local bus revision history data assignment conventions data width iop 480 convention 1 byte (8 bits) byte 2 bytes (16 bits) word 4 bytes (32 bits) lword 8 bytes (64 bits) qword date revision comment 7/30/1997 0.1 red book initial release. 3/6/1998 0.2 revised red book to include detailed core and peripheral specifications. 4/15/1998 0.3 revised red book to separate ibm and plx material. 7/8/1998 0.31 revised red book to combine ibm and plx materials and incorporate engineering changes. 12/7/1998 0.90 blue book initial release. incorporate red book engineering changes. 1/27/1999 ? 2/12/1999 0.92 blue book update. 7/1999 0.96 blue book update. 10/1999 1.0 initial release. 7/12/2000 2.0 initial release revision 2.0. integrated powerpc i/o processor july 2000 incorporates advanced pci functionality, memory controller revision 2.0 and powerpc processor for adapters and embedded systems iop 48 0 iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 1-1 section 1?introduction 1 introduction 1.1 highlights plx industry-leading advanced data pipe architecture ? technology pci controller with dual dma channels, programmable direct master and direct slave data transfer modes, and pci messaging functions local bus dma channel with flyby dma support 66 mhz 32-bit powerpc risc cpu core 32-bit pci interface operating up to 33 mhz flexible memory controller offering support of up to 256 mb of sdram or edo dram of up to 66 mhz pci bus arbiter supports up to three external pci masters and high priority mode local bus arbiter supports two external local bus masters and high priority mode programmable interrupt controller with multiple timers and counters i 2 o- ready messaging unit with r2.0 performance extensions pci specification r2.2 power management features pci hot plug compatible compactpci ? hot swap friendly pci dual address cycle (dac) support 32-bit multiplexed local bus up to 66 mhz supports 8-, 16-, or 32-bit peripheral and memory devices with unlimited bursting up to 264 mb/s debug serial port (tx/rx) ieee 1149.1 jtag port for test and debug 3.3v, 5v tolerant pci and local signaling supports universal pci adapter designs 3.3v core cmos in 208-pin pqfp and 225-pin pbga industrial temp range operation figure 1-1. iop 480 block diagram local bus control logic local bus arbiter sram controller sdram controller dma2 control logic pci bus control logic cpu dma channels 0/1 control logic local bus controller pci bus controller pci bus arbiter i 2 o controller hot swap controller 32-bit 66 mhz local bus 32-bit 33 mhz pci bus pci configuration registers local configuration registers fifos serial eeprom controller uart section 1 introduction features iop 480 data book r2.0 1-2 ? 2000 plx technology, inc. all rights reserved. 1.2 features 1.2.1 powerpc risc processor core 66 mhz powerpc risc 32-bit cpu core thirty-two, 32-bit general purpose registers code compatible with powerpc user instruction set architecture and development tools separate 4 kb instruction cache and write-back/ write-through 2 kb data cache hardware multiply and divide on-chip clock generation and power management up to 66 mhz cpu core and 66 mhz local bus four timers (64-bit time base, programmable interval timer, fixed interval timer, and watchdog timer) memory management unit 1.2.2 on-chip peripheral logic 1.2.2.1 advanced data pipe architecture pci specification r2.2 -compliant 32-bit, 33 mhz bus master interface controller with pci power management features for adapters and embedded systems data pipe architecture technology includes two dma engines, programmable target and initiator data transfer modes and pci messaging functions dual independent dma channels with flexible prioritization scheme direct hardware control of dma demand mode dma operation burst length control ? bterm end of transfer (eot) programmable burst length using thresholds including unlimited burst shuttle mode dma channel support with automatic invalidation of used dma descriptors unaligned transfer support supports pci bus mastering from local slave-only devices (and vice-versa) scatter/gather list/ring management descriptors can be found in pci bus memory or in local bus memory automatic polling for valid descriptors (pci or local bus) automatically returns transfer count upon hardware (eot) dma termination local-to-local dma flyby i/o-to-memory transfers between local devices dma initiated burst reads and writes on the local bus (memory-to-memory) direct master mode 1 type 0 and type 1 configuration cycles supports all pci cycle types, including full support for memory write and invalidate (mwi) cycles initiator read prefetching burst length control unaligned transfer control endian swapping direct slave mode multiple independent address spaces dynamic local bus width control target read prefetching endian swapping local bus priority control pci latency timer eight local bus chip selects supports both memory-mapped and i/o- mapped burst accesses from pci-to-local pci messaging incorporates an i 2 o- ready messaging unit, which is fully compatible with the pci extensions of i 2 o architecture specification r2.0 (pull and outbound option) complete messaging unit with two doorbell registers, and eight mailbox registers with interrupt capability automatically updating queue management pointers, which can be used for message passing under the i 2 o protocol or a custom protocol 1. although pci local bus specification , revision 2.2 utilizes ? pci initiator ? for ? direct master ? and ? pci target ? for ? direct slave, ? plx technology, inc., continues to utilize ? direct master ? and ? direct slave. ? section 1 features introduction iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 1-3 section 2 ? m bus op vital product data support ? fully supports the vital product data (vpd) pci extension, which provides an alternate access method other than expansion rom for vpd. it is updated for distinguishing identical system boards. pci dual address cycle (dac) support (64-bit address space) ? supports pci dac beyond the 4-gb address space, which can be used during iop 480 bus master operations (dma, direct master). pci ? locally-sustained data transfers up to 132 mb/s. six fifos for zero wait-state burst in master, target, and dma modes (32 words deep for writes, and 16 words deep for reads). pci configuration cycles ? in direct master mode, the pci controller can generate type 0 and type 1 pci configuration cycles to enable configuration of other pci devices or cards in the system. interrupt generator ? the pci controller can generate pci and local interrupts to the internal interrupt controller from several sources, including pci interrupt (inta#), system error (serr#), and parity error (perr#). asynchronous bus clocks ? the local bus interface runs from a local system clock and generates the necessary internal clocks. this clock is capable of running asynchronously to the pci clock. the iop 480 requires 3.3v vcc and provides 3.3v signaling with 5v i/o tolerance on both the pci and local buses. it can support universal pci adapter designs. serial eeprom interface ? the iop 480 contains a serial eeprom interface, which can optionally be used to load configuration information. this is useful for loading information unique to a particular adapter (such as, device id or vendor id). 1.2.2.2 memory controller interface 66 mhz memory-bus capability programmable timing, supporting either sdram, edo dram, sram, parallel eeprom, fifo, flash memory, and/or i/o peripheral chips high-bandwidth bus (32-bit data bus) 1.2.2.3 arbiters pci bus arbiter supports up to three external masters local bus arbiter supports up to two external masters high priority modes supported by both arbiters enables deterministic transfer 1.2.3 jtag interface ieee 1149.1 jtag boundary scan interface used for testing and powerpc debug 1.2.4 programmable interrupt controller critical interrupt input (from external devices) external interrupt input (from external devices) timer and debug event interrupts interrupts programmable as either active-high or active-low, and maskable 1.2.5 local bus interface multiplexed 32-bit external bus operates up to 66 mhz compatible with industry-leading dsps, risc processors, and a wide variety of i/o and memory devices supports 8-, 16-, or 32-bit peripherals big-endian or little-endian device attachment programmable wait states up to four external programmable peripherals/ memory regions 1.2.6 programmable chip selects provides chip select pins for up to four external i/o or memory-mapped devices (non-sdram) connected to the local bus each chip select is programmable for bus width and wait states 1.2.7 serial port debug serial uart port for communications with serial devices ttl-level rx and tx signals used for controller debug or attaching external serial devices section 1 introduction company and product background iop 480 data book r2.0 1-4 ? 2000 plx technology, inc. all rights reserved. 1.2.8 data transfer mechanisms the iop 480 supports nine data transfer mechanisms: direct master ? local external master initiates cycle to direct slave direct slave ? pci master initiates cycle to local slave, perhaps memory local bus master ? access to internal registers pci bus ? access to: local configuration/runtime registers pci configuration registers i 2 o message queues dma ? local-to-pci , pci-to-local cpu ? access to: spu direct slave local slave all internal registers dma2 ? local slave-to-local slave (flyby or non-flyby) vpd ? access to serial eeprom external local master ? access to external local slave (as we now own the local bus) 1.3 company and product background plx technology, inc., the world leader in pci-to-local bus i/o accelerator chips, supports more than 500 oem customers in a wide variety of pci applications. customer applications include pc workstations and servers, pci add-in boards, embedded pci communication systems (such as routers and switches), and industrial pci implementations (such as compactpci, pmc, and passive backplane pci). plx technology, inc., is an active participant in industry standard committees, including the pcisig ? , i 2 o sig ? , and picmg ? , and maintains active developer technology and cross-marketing partnerships with industry leaders, such as intel, ibm, hewlett-packard, motorola, integrated systems, windriver, and others. focused on providing complete solutions for pci implementations, plx provides design assistance to customers in the form of reference design kits and software development kits. depending upon the application, these kits may include reference boards, api libraries, software debug tools, and sample device drivers with source, enabling customers to quickly bring new designs to production. new tools, application notes, faqs, and information updates are constantly added to our website (www.plxtech.com) for the convenience of plx customers. our expertise and total solutions for the pci interface allow customers to focus on adding value in their designs without worrying about the complexities of implementing pci, i 2 o, and compactpci. 1.3.1 iop 480 i/o processor general description the iop 480 is designed to support a new class of products that are used in the embedded space ? the i/o processor (iop). design requirements driving the development of the iop include the following: distributed processing architecture (off-load host processor) high-speed pci system bus high-performance, low-cost processor high-performance burst mode data transfers intelligent message passing support efficient i/o transaction management performance scalability the iop 480 integrated powerpc i/o processor is also designed for applications where cost, space, power consumption and performance are all equally critical. the iop 480 provides a high level of integration, reducing chip count from five chips to one, thereby significantly reducing system component cost. the high integration of the iop 480 results in a simplified board design, less power consumption and faster time-to-market solution. this cost-effective, general-purpose integrated processor targets system pci interfaces in networking, telecommunications and other embedded markets. the iop 480 can be used for control purposes in applications such as routers, switches, network storage applications, and image display systems. the iop 480 is a high-performance, low-cost, low-power, integrated i/o processor (iop). it combines a powerpc risc cpu, sdram/sram/edo memory controller, and a pci r2.2 -compliant bus master controller to enable the development of low-cost section 1 applications introduction iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 1-5 section 2 ? m bus op intelligent pci adapters and embedded host pci systems. the iop 480 cpu is a powerpc core with integrated 4 kb instruction cache and 2 kb data cache. it is code-compatible with other members or the powerpc 401xx, 403xx, and 60x processor families. the iop 480 pci bus master design is based on the industry-standard plx pci 9054 i/o accelerator device. additional enhancements to the pci 9054 design include the following: dma ring management local-to-local dma mode a memory controller pci and local bus arbiters additional enhancements to the i 2 o- ready messaging unit at the heart of the iop 480 bus master is the plx proprietary data pipe architecture technology. many high-performance designs are adopting the pci standard for use in their i/o subsystems. however, implementations vary, which can lead to inefficiencies. the plx data pipe architecture technology is tuned for pci efficiency. its capabilities include significantly reduced management and housekeeping overhead and intelligent dma logic for scatter/gather protocols. 1.3.2 development tool support the iop 480 is supported by a wide variety of development tools, including the ibm high c/c++ compiler, ibm riscwatch emulator, third party compilers, debuggers, real time operating systems, and other tools available through the plx partners program. the iop 480 is fully compatible with plx pci sdk and i 2 o sdk software development kits, which allow quick and easy development of high performance local and host pci software through standard apis, i 2 o messaging protocols, pci debug tools, and example device drivers. iop 480 design support is provided through reference design kits (rdk) which provide a flexible pci development board, complete with orcad schematics, documentation, and software. simulation models for the iop 480 are also available. 1.4 applications 1.4.1 pci adapter cards major pci adapter card applications for the iop 480 include high performance communications, networking, disk control, multimedia and video adapters. the iop 480 moves data between the host pci bus and the adapter local bus in several ways. first, the host processor may program the iop 480 dma controller to move data between the adapter memory and the host pci bus. second, the iop 480 can perform ? direct master transfers, ? whereby a local mastering device accesses the pci bus directly through a pci master transfer. the iop 480 supports slave (target) transfers in which another pci device is the master. the iop 480 also has a complete messaging unit with mailbox registers, doorbell registers, and queue management pointers, which can be used for message passing under the i 2 o protocol or a custom protocol. adapter cards are the primary vehicle for i/o processing and host processor off-loading. (refer to figure 1-2.) figure 1-2. sample pci i/o processor adapter design 1.4.2 pci host embedded systems another application for the iop 480 lies in pci host embedded systems, such as network hubs and routers, printer engines, set top boxes, and industrial equipment. in this configuration, all four of the above- mentioned data transfer modes are used. in addition, the iop 480 supports type 0 and type 1 pci configuration cycles. this allows the iop 480 to configure the other pci devices or cards in the system. the iop 480 provides a pci bus arbiter with support for up to three pci bus master devices or pci slots. (refer to figure 1-3.) iop 480 i/o i/o sdram firmware (flash) pci bus local bus section 1 introduction applications iop 480 data book r2.0 1-6 ? 2000 plx technology, inc. all rights reserved. figure 1-3. sample pci host embedded system design 1.4.3 high-performance pci i 2 odesign as a member of the i 2 o sig, plx helped define the i 2 o specification, and was the first to offer a processor-independent i 2 o implementation in the pci 9080. the iop 480 is the first second-generation iop, incorporating the latest i 2 o and pci performance enhancements. applications include high-performance storage controllers (raid), and network interface cards (10/100baset, atm). i 2 o also provides an efficient solution for embedded designs. i 2 o takes advantage of the pci performance features, while providing a level of abstraction from both the host operating system and i/o subsystem. the i 2 o design simplifies the upgrade path of the user's product to take advantage of future hardware and software performance enhancements. (refer to figure 1-4 and figure 1-5.) the iop 480 incorporates the pull and outbound option, as specified in i 2 o specification r2.0 . these options aid the development of write-only architecture. advantages: split driver model model coprocessor implementation facilitates peer-to-peer transfers manages batching interrupts aides write-only architectures aides local bus balancing figure 1-4. typical i 2 o server/adapter card design figure 1-5. typical i 2 o embedded system design 1.4.4 high-performance compactpci adapter design another key application for the iop 480 is compactpci adapters for telecom and networking applications. these applications include high performance communications, such as wan/lan controller cards, high-speed modem cards, frame relay cards, and telephony cards for telecom switches and remote-access systems. the iop 480 has integrated key features to enable live-insertion of hot swap compactpci adapters. the iop 480 picmg 2.1 r1.0 -compatible hot swap friendly pci interface includes both hot swap capable and hot swap friendly features. (refer to figure 1-6.) iop 480 i/o i/o sdram firmware (flash) pci bus pci i/o chip pci slots local bus host local bus iop local bus no hardware changes required on the host side inbound queue port outbound queue port host pci interface i/o chip i/o chip iop 480 i 2 o messaging unit host cpu pci bus host system memory message frames iop local memory message frames message queues host local bus iop local bus i 2 o defines efficient use of bus mastering dma interrupts burst modes push/pull memor y ? ? ? ? inbound queue port outbound queue port iop 480 i 2 o messaging unit pci 9080 i 2 o messaging unit host cpu host system memory message frames iop local memory message frames message queues pci bus section 1 applications introduction iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 1-7 section 2 ? m bus op 1.4.4.1 hot swap capable pci specification r2.1 or better tolerant of vcc from early power tolerant of asynchronous reset tolerant of precharge voltage limited i/o pin leakage at precharge voltage 1.4.4.2 hot swap friendly incorporates the hot swap control/status register (hscsr) incorporates an extended capability pointer (ecp) mechanism incorporates added resources for software control of enum#, the ejector switch, and the status led, which indicates insertion and removal to the user figure 1-6. high-performance compactpci adapter 1.4.5 real time application design to face the problems of real-time applications on the pci bus, the iop 480 provides a high-priority mode. the pci bus provides a 132 mb/s of bandwidth. however, there is no built-in mechanism for a particular application to have a consistent slice of that bandwidth. if a plug-in card is gathering real-time data, even at relatively slow rates, large buffers are required on board to guarantee that the none of the data is dropped. dropped data may appear as missed frames in a movie or clicks in an audio stream. (refer to figure 1-7.) to address this problem, the iop 480 ? s arbiters can be put into a high-priority mode. instead of using the standard fairness algorithm, the iop 480 can be set up to be deliberately biased towards a particular transfer. if the internal dma channels (channels 0 and 1) are used to transfer data and the built-in local and pci arbiters are set for high priority (and used), the iop 480 delivers a guaranteed minimum bandwidth. this amount of guaranteed bandwidth depends on several factors. the burst capability of the pci and local targets, the relative speeds of the pci and local buses, and the bus latency timer settings all contribute to this guaranteed bandwidth. the number and traffic patterns of other masters on either bus do not effect this bandwidth. a 33 mhz system capable of bursts up to 16 words can easily achieve a 100 mb/s guaranteed minimum bandwidth with the iop 480. (refer to figure 1-7.) figure 1-7. sample real-time application 1.4.6 data communications design in many datacom and telecom applications, the iop 480 is tasked to work in conjunction with a processor (either in the iop itself or externally) to transfer data to and from i/o chips. this usually means that the processor would set up dma descriptor chains for both transmit and receive operations. to occupy a fixed block of memory, the tails of these chains are made to point back to the head, resulting in descriptor rings. the iop 480 incorporates ring management specifically for this type of application. (refer to figure 1-8.) the rings and the i/o chips may reside either on the pci bus or on the local bus. one of the iop's dma channels would be set for local-to-pci transfers and the other for pci to local transfers (for separate transmit and receive rings). the iop utilizes a valid bit in each dma descriptor link to keep track of its location in the ring sequence. this valid bit is automatically invalidated at the completion of each descriptor link. as the iop circles through the rings, the managing processor can update the links and then again validate local bus i/o chips (datacom, telecom, storage, etc.) rom ram iop 480 pci bus i/o iop 480 target i/o device sdram master i/o device real -time data input local bus memory controller signals pci bus signals pci arbitration local arbitration section 1 introduction applications iop 480 data book r2.0 1-8 ? 2000 plx technology, inc. all rights reserved. them. if the iop 480 reaches an invalidate link, it waits for that link to become valid before processing. in this manner, both the iop and the managing processor can run at their fastest possible speed without interrupts. the end of a packet would be signaled to the iop via the eot# (end of transfer) pins. when the iop encounters an eot, instead of simply invalidating the current descriptor link, it writes the number of words remaining to be transferred (in the current link) to the current descriptor link location, giving an idea of packet size. figure 1-8. data communication design receive i/o transmit i/o iop 480 receive ring transmit ring sram iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 2-1 section 2 ? lb interface 2 local bus interface 2.1 introduction the local bus provides a data path between the pci bus and non-pci devices, such as the iop 480 cpu, memory devices, and peripherals. the local bus is 32-bit multiplexed bus, with bus memory regions that can be programmed for 8-, 16-, or 32-bit widths. the iop 480 local bus is signal-compatible with popular risc and bridge architecture, including the i960jx, ppc401 gf, and j mode of the pci 9080 or pci 9054. the iop 480 acts as a master and slave on the local bus. when the iop 480 is acting as a local bus slave, an external master on the local bus can access all internal configuration registers, as well as perform direct master accesses to the pci bus. the iop 480 accepts burst transfers at a maximum rate of one word per clock cycle. external local bus masters that access the iop 480 must have a 32-bit data bus, and treat the iop 480 as a 32-bit slave device. when the iop 480 is acting as a local bus master, the direct slave controller, internal dma controllers, or internal iop 480 cpu can transfer data between the local bus, internal registers and fifos. burst lengths are limited to four lwords when the iop 480 cpu controls the bus, and to memory page boundaries when dma channels or a direct slave controller are bursting data. the width of the bus depends upon the local address space accessed. there are four sram spaces, one dram space, and one default space. each space contains a set of configuration registers that determine all local bus characteristics when that space is accessed. 2.1.1 transactions four types of transactions can occur on a local bus: read write read burst write burst a bus access is a transaction which is bounded by the assertion of ads# or ale at the beginning and de-assertion of blast# at the end. a bus access consists of an address cycle followed by one or more data transfers. during each clock cycle of an access, the local bus is in one of four basic states defined in section 2.1.2, ? basic bus states. ? a clock cycle consists of one period of the local bus clock. figure 2-1. local bus block diagram arbiter local clock local master controller local slave controller config registers direct master fifos local dma direct slave fifos local addr/ data bus iop 480 cpu control control addr/data lad[31:0] addr/data local control bus section 2 local bus interface local signals iop 480 data book r2.0 2-2 ? 2000 plx technology, inc. all rights reserved. 2.1.2 basic bus states the four basic bus states are idle, address, data/wait, and recovery. once the local bus master owns the bus and needs to start a bus access, the address state is entered, ads# or ale is asserted, and a valid address is presented on the address/data bus. data is then transferred while in a data/wait state. ready# or wait# is used to insert wait states. blast# is asserted during the last data/wait state to signify the last transfer of the access. after all data has been transferred, the bus enters the recovery state to allow the bus devices to recover. after recovery state, the bus enters the idle state and waits for another access. 2.2 local signals the key local bus control signals shown in most timing diagram examples are as follows: ads# or ale indicates the start of an access ready#, wait#, and bterm# indicate data transfer with wait state or terminating burst cycle lwr#, direction of data transfer blast#, bterm# indicate the end of an access the key data signals are: lad address, data bus lbe# local byte enables, indicating valid byte lane 2.3 local bus signals there are four groups of local bus signals: clock, address/data/parity, control/status, and arbitration. signal usage varies upon application. 2.3.1 clock lclk, the local bus clock, operates at frequencies up to 66 mhz, and is asynchronous to the pci bus clock. most local bus signals are driven and sampled on the rising edge of lclk. the ale address latch enable is asserted on the rising edge and de-asserted on the falling edge of lclk. setup and hold times, with respect to lclk, must be observed. 2.4 bus regions there are six bus regions and each region can have its own characteristics, such as bus width (8, 16, or 32 bit), burst enable, bterm enable, parity checking, big/little endian selection, read prefetch count, and timeout enable. if the iop 480 is a local bus slave, the bus width is fixed 32-bit, and the regions are direct master memory, direct master i/o, and local access registers. the bus regions are: chip selects (lcs0#, lcs1#, lcs2#, and lcs3#) dram default the three master bus regions are: direct master memory direct master i/o configuration register the direct master and configuration regions are fixed at 32-bit wide regions. 2.4.1 address/data/parity 2.4.1.1 lad[31:0] the lad[31:0] bus is a 32-bit multiplexed address/ data bus. during address state, lad[31:2] contains the word address of the transfer. memory address bits ma[17:0] provide an incrementing word address during burst access (refer to section 12, ? memory controller ? ). if the bus width is 8 or 16 bits, additional de-multiplexed address signals are available on the unused byte enables: lbe1# acts as a1 and lbe0# acts as a0. (refer to table 2-14 on page 2-16.) note: dedicated address pins are available. during data states, lad[31:0], lad[15:0], or lad[7:0] contain transfer data for a 32-, 16-, or 8-bit bus, respectively. if the bus is 8 or 16 bits wide, the data supplied by the iop is replicated across the entire 32-bit wide bus. section 2 bus regions local bus interface iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 2-3 section 2 ? lb interface 2.4.1.2 dp[3:0] byte parity is generated when data is driven out of the iop 480. when data is passed into the iop 480, parity is checked on each active byte lane. even or odd parity can be selected. an interrupt can be generated if a parity error is detected. each address space on the local bus has configuration register bits for enabling parity checking and selecting even or odd parity. 2.4.2 control/status the control/status signals the control address latches and flow of data across the local bus. 2.4.2.1 ads# and ale a local bus access starts when ads# (address/data status) is asserted during an address state by the local bus master. ale is used to strobe the lad bus into an external address latch. 2.4.2.2 lbe[3:0]# during an address state, the lbe[3:0]# byte enables denote which byte lanes are being used during access of a 32-bit bus. they remain asserted until the end of the data transfer. refer to table 2-14 on page 2-16 for a functionality description of lbe[3:0]# for different bus widths. 2.4.2.3 lwr# during an address state, lwr# is driven to a valid state, signifying the data transfer direction. when the iop 480 is the local bus master, lwr# is driven high when the iop 480 is writing data to the local bus, and low when it is reading the bus. as a slave, the iop 480 monitors lwr# to determine direction of the data transfer. lwr# is driven high by another local bus master that is writing data to the iop 480 local bus, and low when data is being read from the iop 480 local bus. 2.4.2.4 blast# blast# is asserted by the current local bus master to indicate the last transfer of an access, both for single and burst accesses. when the iop 480 is the local bus master, the blast# timing bit (locctl[19]) determines the behavior of blast#. if that bit is set to 0, blast# is asserted by the master during the entire last transfer of an access. if that bit is set to 1, then blast# is not asserted by the master until the internal wait state counters have finished counting. note: dma can be programmed to end an access without blast# being asserted (c0mode[15], c1mode[15], and/or c2mode[15]). 2.4.2.5 ready# ready# indicates that write data is being accepted or read data is being provided by the bus slave. if a bus slave needs to insert wait states, it can de-assert ready# until it is ready to accept or provide data. the ready# input pin has a corresponding enable bit in the configuration registers for each local address space. if ready# is disabled, then the length of the local bus transfer is determined by internal wait state generators. (refer to table 2-2.) table 2-1. dp[3:0] dp bit number lad parity byte lane relationship 3 [31:24] 2 [23:16] 1 [15:8] 0 [7:0] section 2 local bus interface bus regions iop 480 data book r2.0 2-4 ? 2000 plx technology, inc. all rights reserved. 2.4.2.6 bterm# the burst terminate signal, bterm#, is used by a bus slave to stop a burst access. when the iop 480 is the local bus master and detects bterm# asserted, it terminates the burst. if there is more data to transfer, a new burst access is initiated with the assertion of ads#. if the internal wait state generators are active, then bterm# is not sampled until the wait state counters decrement to zero. bterm# also signals to the iop 480 that data has been accepted or provided, so ready# need not be asserted when bterm# is asserted. when the iop 480 is the local bus slave, it asserts bterm# and ready# when a pci abort or retry timeout is encountered during a direct master access. if the ready# input is enabled, then bterm# is asserted when the local address matches the page boundary. if the ready# input is disabled, bterm# is asserted when ready# is driven by the iop 480 if the local address matches the page boundary. the bterm# input pin has a corresponding enable bit in the configuration registers for each local address space. if bterm# is disabled, then the length of a local burst when the iop 480 is the local bus master is a maximum of four lwords. note: in table 2-3, 0 = disable and 1 = enable. table 2-2. ready data transfers master device slave device ready# input enable ready# description iop 480 sram space 0 driven data transfers determined by wait state generator. ready# is asserted when data transfer takes place. iop 480 sram space 1 input data transfers determined by an external device which asserts ready# to indicate data transfer is taking place. iop 480 dram space ? driven data transfers determined by wait state generator. ready# is asserted when data transfer takes place. iop 480 default space ? input data transfers are determined by an external device, which asserts ready# to indicate data transfer is taking place. external sram space 0 driven data transfers determined by wait state generator. ready# is asserted when data transfer takes place. external sram space 1 input data transfers determined by an external device, which asserts ready# to indicate data transfer is taking place. external dram space ? driven data transfers determined by wait state generator. ready# is asserted when data transfer takes place. external default space ? input driven if timeout data transfers are determined by an external device, which asserts ready# to indicate data transfer is taking place if a timeout occurs, and the timeout ready out enable bit is set, ready# is driven. external iop 480 configuration registers ? driven data transfers determined by internal logic. ready# is asserted when data transfer takes place. external iop 480 direct master controller ? driven data transfers determined by internal logic. ready# is asserted when data transfer takes place. table 2-3. burst and bterm on local bus mode burst bterm result single cycle 00 one ads# per data (default). single cycle 01 one ads# per data. burst-4 10 one ads# per four data (recommended for i960 and ppc401 family). burst forever 11 one ads# per bterm#. section 2 bus regions local bus interface iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 2-5 section 2 ? lb interface 2.4.2.7 wait# when an external agent is the local bus master, wait# can be used to signal the iop 480 that the local bus master cannot accept or provide data, and needs wait states to be inserted. the iop 480 signals the local bus master with ready# when it has provided/accepted the direct master data. using both wait# and ready# allows the master or slave to insert wait states during direct master accesses. when the iop 480 is the local bus master, wait# is an output that provides status of the internal wait state generators. it is asserted while internal wait states are being inserted ? ready# as an input is not sampled until wait# is de-asserted. 2.4.2.8 llock# when the iop 480 is the local bus master, llock# is asserted to indicate that an atomic operation for a direct slave pci access may require multiple transactions to complete. llock# is asserted during the address state of the first transaction of the atomic operation, and de-asserted one clock after the last transaction of the atomic operation is complete. if enabled, the local bus arbiter does not grant the bus to another master until the atomic operation has completed. 2.4.3 arbitration arbitration signals control which device is to be local bus master. a round-robin arbiter selects between five internal and two external local bus masters. (refer to section 8, ? local bus internal arbiter. ? ) 2.4.3.1 boff# boff# is an output indicating the iop 480 requires the local bus for a direct slave access while a direct master access is pending. it is associated with the deadlock situation (refer to section 5.9, ? deadlock conditions ? ). larbr[16] is used to enable the local bus boff# signal (refer to section 5.9.1, ? backoff ? ). 2.4.3.2 lholdreq0/lholdack and lholdreq1 the iop 480 local bus arbiter supports two external bus masters and five internal bus masters (a direct slave controller, three dma controllers, and the iop 480 cpu). when an external local bus master wants control of the local bus, it asserts its corresponding local bus hold request signal through the iop 480 (either the multiplexed lholdreq0/ lholdack pin or the non-multiplexed lholdreq1 pin). after the local bus is granted, the external local bus master should keep its corresponding local bus hold request signal (either the multiplexed lholdreq0/lholdack pin or the non-multiplexed lholdreq1 pin) asserted until it is finished with the bus. (refer to table 2-4.) the local arbiter enable bit (larbr[0]), is used to enable the iop 480 local bus arbiter (default is enabled). 2.4.3.3 lholdack0/ldreq and lholdack1/breq the iop 480 local bus arbiter asserts its corresponding local bus hold acknowledge signal (either the multiplexed lholdack0/ldreq or lholdack1/breq pin) to grant the local bus to an external local bus master. (refer to table 2-4.) 2.4.4 local chip selects during a local bus cycle, the accessed range can be one of the following: configuration register direct master memory direct master i/o one of four sram spaces (lcs[3:0]#) dram space default local chip select (lcs[3:0]#) is used to select one of four sram spaces (devices). each range is defined by its base and range, and access should be enabled for it to be selected. table 2-4. local arbitration signal directions external arbitration signal local arbiter enabled local arbiter disabled lholdreq0/lholdack input input lholdreq1 input not used lholdack0/ldreq output output lholdack1/breq output not used section 2 local bus interface local bus protocol iop 480 data book r2.0 2-6 ? 2000 plx technology, inc. all rights reserved. for example , lcs3# is asserted if the local address of an access is within the range defined by the local chip select 3 base address (lcs3base) and local chip select 3 range (lcs3range), and local chip select 3 enabled (lcs3base[0]=1). because lcs3# is the output on a multiplexed pin (lcs3#/ma17), the lcs3# function must be selected in the locctl configuration register (locctl[7]=0) before using this bus region. the default lcs0# base address is 0xfff0_0000, which allows the internal iop 480 cpu to boot from a serial eeprom at location 0xffff_fffc. the local characteristics of all accesses in the lcs range are defined by three registers, as described in the following table. 2.5 local bus protocol 2.5.1 basic bus accesses a basic bus access consists of one data transfer. it can be one byte, word, or lword of data being transferred between a master and a slave. after a master gains control of the local bus, it pulses ale to latch the address or asserts ads#. the iop 480 does both with the following valid address and cycle status information: lad[31:2] word address lbe[3:0]# byte enables lwr# 1=write status, 0=read status for additional details of other signals during a read or write access, refer to section 12, ? memory controller. ? during the next clock cycle, ads# is de-asserted, and blast# asserted. the bus master then waits for a data transfer upon which blast# is de-asserted. (refer to figure 2-2.) 2.5.2 wait states ready# is used by a slave to insert wait states in a data transfer. during data/wait states, data transfer takes place if ready# was sampled asserted by the master on the rising edge of the clock. if ready# input is disabled for a local address space, then the number of wait states is determined by the internal wait state generator. for dram space, ready# input is ignored and the number of wait states is always determined by the internal wait state generator. the wait# pin is sampled by the iop 480 during direct master accesses, and used by the local bus master to insert wait states. the wait# pin is driven by the iop 480 when it is the local bus master, and asserted when the internal wait state generator is inserting wait states. table 2-5. registers defining local characteristics of all lcs range accesses register defined by local chip select bus region descriptor (lcsxbrd) characteristics of: recovery state prefetch timeout parity memory write protect bterm# input ready# input burst iop 480 byte ordering big endian byte lane mode local byte ordering data bus width local chip select write timing (lcsxwt) number of: write recovery states write hold states write delay states write data-to-data wait states write address-to-data wait states local chip select read timing (lcsxrt) number of: read recovery states read delay states read data-to-data wait states read address-to-data wait states section 2 local bus protocol local bus interface iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 2-7 section 2 ? lb interface timing diagram 2-1. single read/write, 32-bit bus, master=iop 480 timing diagram 2-2. local bus burst read, delayed with wait#, master=external local bus master addr data addr wr data 0ns 25ns 50ns 75ns 100ns 125ns lclk lad[31:0] ma[13:0] lbe[3:0]# ale ads# lwr# blast# ready# addr d0 d1 d2 d3 a0 a1 a2 a3 0ns 25ns 50ns 75ns 100ns lclk lad[31:0] lbe[3:0]# ma[13:0] ale ads# lwr# blast# ready# wait# section 2 local bus interface local bus protocol iop 480 data book r2.0 2-8 ? 2000 plx technology, inc. all rights reserved. timing diagram 2-3. local bus burst write, delayed with wait#, master=external local bus master timing diagram 2-4. single read/write with internal wait states, 32-bit bus, master = iop 480 addr d0 d1 d2 d3 a0 a1 a2 a3 0ns 25ns 50ns 75ns 100ns lclk lad[31:0] lbe[3:0]# ma[13:0] ale ads# lwr# blast# ready# wait# addr data addr wr data 0ns 25ns 50ns 75ns 100ns 125ns 150ns lclk lad[31:0] ma[13:0] lbe[3:0]# ale ads# lwr# blast# wait# ready# section 2 local bus protocol local bus interface iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 2-9 section 2 ? lb interface timing diagram 2-5. local bus burst read, 32-bit bus, no wait states, master=iop 480, slave=default space timing diagram 2-6. local bus burst write, 32-bit bus, no wait states, master=iop 480, slave=default space addr d0 d1 d2 d3 a0 a1 a2 a3 0ns 25ns 50ns 75ns 100n s lclk lad[31:0] lbe[3:0]# ma[13:0] ale ads# lwr# blast# ready# addr d0 d1 d2 d3 a0 a1 a2 a3 0ns 25ns 50ns 75ns 100n s lclk lad[31:0] lbe[3:0]# ma[13:0] ale ads# lwr# blast# ready# section 2 local bus interface bus region descriptors iop 480 data book r2.0 2-10 ? 2000 plx technology, inc. all rights reserved. 2.5.3 bus and control signals during recovery and idle states bus signals are driven to the following state during recovery: lad[31:0] floats following a read access lad[31:0] freezes ale, ads#, and blast# are de-asserted lbe[3:0]# are driven to ones ma[17:0] and lwr# freeze if the internal arbiter is enabled (larbr[6]=1) and no external requester controls the bus, lad and lbe[3:0]# are driven by the iop 480 during idle states. 2.5.4 burst transactions a burst access consists of at least two data transfers. maximum length of a burst depends upon the local bus master, local slave, and bus memory region descriptor registers. as with a basic bus access, a master gains control of the local bus and asserts ads# with the valid address and cycle status information. the local bus master then continues with the data transfer. blast# is asserted during the last data transfer, indicating the end of the bus access. however, an exception exists. dma can be programmed to use eot# or dreq# in place of blast# to end the bus access. (refer to section 7, ? dma operation. ? ) if the number of address-to-data wait states is set to zero, care must be taken to prevent bus contention between the address and first data word. in most cases, at least one address-to-data wait state is required. during a write access, the master continues driving the write data until the slave asserts ready#. the next word of data is driven and burst address incremented. blast# is asserted during the last data transfer, indicating the end of access. 2.6 bus region descriptors 2.6.1 direct slave or dma burst when the direct slave interface, or one of the internal dma controllers in the iop 480 is the local bus master, there are several bits in the memory controller configuration registers that determine bursting characteristics. there are six sets of bus region descriptor registers, one of which is selected during a local bus access. the value on lad[31:2] bus during an address state determines which set is used. within each set of registers there are two bits that control bursting, burst enable and bterm enable. if burst is disabled, then the iop 480 only runs single transfers on the bus. if burst is enabled, the iop 480 runs burst access if more than one piece of data needs to be transferred. bterm enable controls the length of bursts. if bterm is disabled, then bursting can start on any address boundary and continue up to an address boundary specified in table 2-6 for a maximum of four data transactions. if bterm enable is high, then bursting continues until one of the following occurs: fifos become full or empty target device asserts bterm# page boundary crossing detection asserts bterm#, according to table 2-7 if there is more data to transfer when the burst terminates, a new bus access is initiated. table 2-6. burst boundaries with bterm enable=0 bus width boundary 32 bits four lwords or up to a quad-lword boundary (la3,la2 = 11) 16 bits four words or up to a quad-word boundary (la2,la1 = 11) 8 bits four bytes or up to a quad-byte boundary (la1,la0 = 11) section 2 endian swapping local bus interface iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 2-11 section 2 ? lb interface 2.6.2 wait state control if ready# mode is disabled, the external ready# input signal has no effect on wait states for a local access. wait states between data cycles are asserted internally by a wait state counter. the wait state counter is initialized with its configuration register value at the start of each data access. if ready# mode is enabled, ready# then controls the number of additional wait states. bterm# overrides ready# when bterm# is enabled and asserted. 2.7 endian swapping the iop 480 supports both big and little endian byte ordering on the local bus. big endian implies that the most significant byte is located at the lowest address, while little endian implies that the least significant byte is located at the lowest address. there are two approaches to mapping between big and little endian, address invariance and data invariance. the iop 480 uses the address invariance approach in which the address of each byte in memory is preserved. this technique employs the use of byte lane swapping. 2.7.1 direct master or configuration register access as a local bus slave, the iop 480 supports big and little endian byte ordering. the big/little endian configuration register (bigend) contains bits to select big or little endian mode for direct master or configuration register accesses. one set of bits (bigend[1:0]) are used when an external master controls the local bus, and another set (bigend[3:2]) when the iop 480 cpu controls the local bus. 2.7.2 direct slave or dma access endian swapping as a local bus master, and during direct slave or dma accesses, the iop 480 byte ordering and big endian byte lane mode bits in each of the memory controller bus region descriptor registers determine byte ordering. 2.7.3 endian swapping example suppose a value of 0xaabbccdd is stored in one of the internal registers or the iop 480 fifos. the value appears on various byte lanes depending upon bus width, address, and endian selection. when big endian mode is selected, upper or lower bytes lanes can be used for 8- or 16-bit bus widths, depending upon the configuration bit. (refer to table 2-9 and table 2-10.) 2.7.4 internal iop 480 cpu the natural byte ordering of the iop 480 cpu is big endian. although the iop 480 cpu configuration bits allow it to switch to little endian byte ordering, it is recommended that endian swapping configuration issues be handled through the iop 480 configuration registers (lcs0brd[4], lcs1brd[4], lcs2brd[4], lcs3brd[4], dfltbrd[4], and drambrd[4]). these iop 480 configuration registers allow selection table 2-7. burst boundaries with bterm enable=1 local address space number of columns boundary sram ? 32 kb (7fffh) edo dram 8 1 kb (3ffh) edo dram 9 2 kb (7ffh) edo dram 10 4 kb (fffh) edo dram 11 8 kb (1fffh) edo dram 12 16 kb (3fffh) sdram (x16) 8 1 kb (3ffh) sdram (x8) 9 2 kb (7ffh) sdram (x4) 10 4 kb (fffh) default ? 2 kb (7ffh) table 2-8. endian swapping big endian word little endian word b0 ??????????? b31 b31 ??????????? b0 b0 b1 b2 b3 b3 b2 b1 b0 plxttxlp msb lsb msb lsb lad31 ???????? lad0 lad31 ???????? lad0 section 2 local bus interface endian swapping iop 480 data book r2.0 2-12 ? 2000 plx technology, inc. all rights reserved. of big or little endian ordering for each of six local address spaces (four sram, one dram, and one default). the iop 480 utilizes address invariant endian swapping. this preserves the relative byte addresses of all data flowing through, thus preserving character strings. accesses to an 8-bit local bus device do not swap byte order, regardless of whether the local bus is set for big or little endian ordering. (refer to figure 2-2.) table 2-9. endian swapping, lower byte lanes word data type byte lanes bus width addr bits a1, a0 transfer little endian big endian, lower byte lanes ad[31:24] ad[23:16] ad[15:8] ad[7:0] ad[31:24] ad[23:16] ad[15:8] ad[7:0] 32 bits 00 1st aa bb cc dd dd cc bb aa 16 bits 00 1st ?? cc dd ?? dd cc 10 2nd ?? aa bb ?? bb aa 8 bits 00 1st ??? dd ??? dd 01 2nd ??? cc ??? cc 10 3rd ??? bb ??? bb 11 4th ??? aa ??? aa table 2-10. endian swapping, upper byte lanes word data type byte lanes bus width addr bits a1, a0 transfer little endian big endian, upper byte lanes ad[31:24] ad[23:16] ad[15:8] ad[7:0] ad[31:24] ad[23:16] ad[15:8] ad[7:0] 32 bits 00 1st aa bb cc dd dd cc bb aa 16 bits 00 1st ?? cc dd dd cc ?? 10 2nd ?? aa bb bb aa ?? 8 bits 00 1st ??? dd dd ??? 01 2nd ??? cc cc ??? 10 3rd ??? bb bb ??? 11 4th ??? aa aa ??? section 2 endian swapping local bus interface iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 2-13 section 2 ? lb interface figure 2-2. endian swapping note: arrows in the figure denote the initiator of a cycle (read or write). 2.7.4.1 big endian (internal cpu setting) bigend register bits bus region descriptors bit bit 1 2 3 4 2 2 0 2 2 dm fifo internal cpu core (software-configurable endianess) dma2 fifo configuration registers dma fifos ds fifo always little endian select byte lane mode and bus width local bus pci bus table 2-11. iop 480 cpu big endian byte ordering word data type byte lanes bus width addr bits a1, a0 transfer little endian internal cpu bus ad[31:24] ad[23:16] ad[15:8] ad[7:0] ad[31:24] ad[23:16] ad[15:8] ad[7:0] 32 bits 00 1st aa bb cc dd dd cc bb aa 16 bits 00 1st ?? cc dd dd cc ?? 10 2nd ?? aa bb ?? bb aa 8 bits 00 1st ??? dd dd ??? 01 2nd ??? cc ? cc ?? 10 3rd ??? bb ?? bb ? 11 4th ??? aa ??? aa section 2 local bus interface endian swapping iop 480 data book r2.0 2-14 ? 2000 plx technology, inc. all rights reserved. 2.7.4.1.1 big endian cycle timing diagram timing diagram 2-7. big endian cycle 5a5a5a5a abcdef09 5 f 6 0 f 09efcdab 30313233 ffffffff 0080 0 f 33323130 0ns 250ns 500ns pclk gnt0#/req# req0#/gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# devsel# stop# lock# lclk ads# ale lad[31:0] ma[12:0] lbe[3:0]# blast# ready# bterm# lwr# rd# lholdack0/ldreq0 lholdack1/breq lholdreq0/lholdack lholdreq1 llock# section 2 bus width local bus interface iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 2-15 section 2 ? lb interface 2.7.4.2 little endian (internal cpu setting) 2.8 bus width memory controller configuration bus region descriptor registers determine the width of the local bus. as a slave, the iop 480 expects all four byte lanes to be used (32-bit bus). the following byte lanes and byte enables are used for various bus widths. (refer to table 2-14). during write accesses, data is replicated on unused byte lanes. (refer to table 2-15). 2.9 data alignment 2.9.1 iop 480 as a local bus slave as a local bus slave, the iop 480 allows unaligned accesses (any combination of byte enables asserted) to the configuration registers or the direct master fifos, and either single or burst transfers are supported. the iop 480 must always be accessed as a 32-bit slave on the local bus. 2.9.2 iop 480 as a local bus master as a local bus master, the iop 480 supports unaligned transfers. for direct slave writes, the iop 480 breaks any partial write into a single access. it only bursts on the local bus if all byte enables are asserted. if no pci byte enables are active, there is no transfer to the local bus, and the iop 480 issues a target abort. for direct slave reads, regardless of the pci byte enable, the iop 480 reads all bytes on the local bus during a burst prefetch transaction. for single reads, the iop 480 passes the byte enables. for a 32-bit bus, if a dma transfer does not start at an address with lad[1:0] = 00, then a partial word transfer is first performed, followed by word bursts. for a 16-bit bus, if the dma transfer does not start at an address with lad[0] = 0, then a byte transfer is first performed, followed by word bursts. for an 8-bit bus, a dma transfer may start bursting at any address. 2.10 bus accesses any bus access can have different characteristics based upon the bus region descriptor. these characteristics include bus width and burst behavior. table 2-12. iop 480 cpu little endian byte ordering word data type byte lanes bus width addr bits a1,a0 transfer little endian internal cpu bus ad[31:24] ad[23:16] ad[15:8] ad[7:0] ad[31:24] ad[23:16] ad[15:8] ad[7:0] 32 bits 00 1st aa bb cc dd aa bb cc dd 16 bits 00 1st ?? cc dd ?? cc dd 10 2nd ?? aa bb aa bb ?? 8 bits 00 1st ?? ? dd ??? dd 01 2nd ?? ? cc ?? cc ? 10 3rd ?? ? bb ? bb ?? 11 4th ?? ? aa aa ??? table 2-13. direct slave local byte enable methods direct slave methods byte enables dsr burst don ? t pass dsr single / i/o pass dsw burst breakup burst for alignment dsw single / i/o pass dsw to 8-bit bus skip if no byte enables allowed section 2 local bus interface bus accesses iop 480 data book r2.0 2-16 ? 2000 plx technology, inc. all rights reserved. note: unused signals are driven to 1 as output, and ignored as input. 2.10.1 data transfer data transfer occurs on the local bus when the master and slave devices are ready to receive data. the master device uses the wait# pin to insert wait states, and the slave device uses the ready# pin. (refer to table 2-16.) table 2-14. byte enable and coding bus width lbe3# lbe2# lbe1# lbe0# comments 32 bits lad[31:24] lad[23:16] lad[15:8] lad[7:0] (all byte lanes used) 16 bits lad[15:8] not used a1 lad[7:0] (lbe3# = bhe#, lbe0# = ble#) 8 bits not used not used a1 a0 (all data transfers use lad[7:0]) table 2-15. byte lane contents bus width lad[31:24] lad[23:16] lad[15:8] lad[7:0] comments 8 bits byte n byte n byte n byte n 8-bit access 16 bits byte n byte n byte n byte n 8-bit access 16 bits byte n+1 byte n byte n+1 byte n 16-bit access 32 bits byte n byte n byte n byte n 8-bit access 32 bits byte n+1 byte n byte n+1 byte n 16-bit access table 2-16. data transfer control ready# enabled wait# ready# transfer 00xno 01xyes 10xno 110yes 111no iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 3-1 section 3 ? pb interface 3 pci bus interface 3.1 overview the iop 480 is compliant with pci specification r2.2 . refer to pci specification r2.2 for specific pci bus functions. 3.2 direct slave command codes as a target, the iop 480 allows access to the iop 480 internal registers and the local bus, using the commands listed in table 3-1. all read or write accesses to the iop 480 can be byte, word, or longword (lword) accesses. all memory commands are aliased to basic memory commands. all i/o accesses to the iop 480 are decoded to an lword boundary. byte enables are used to determine which bytes are read or written. an i/o access with illegal byte enable combinations is terminated with a target abort. 3.3 pci master command codes the iop 480 can access the pci bus to perform dma or direct master local-to-pci bus transfers. during a direct master or dma transfer, the command code assigned to the iop 480 internal register location (pcictl[15:0]) is used as the pci command code. notes: programmable internal registers determine pci command codes when the iop 480 is the master. dma cannot perform i/o or configuration accesses. 3.3.1 dma master command codes the iop 480 dma controllers can assert the following memory cycles. 3.3.2 direct local-to-pci command codes for direct local-to-pci bus accesses, the iop 480 asserts the cycles listed in the following tables. table 3-1. direct slave command codes command type code (c/be[3:0]#) i/o read 0010 (2h) i/o write 0011 (3h) memory read 0110 (6h) memory write 0111 (7h) configuration read 1010 (ah) configuration write 1011 (bh) memory read multiple 1100 (ch) memory read line 1110 (eh) memory write and invalidate 1111 (fh) table 3-2. dma master command codes command type code (c/be[3:0]#) memory read 0110 (6h) memory write 0111 (7h) memory read multiple 1100 (ch) dual address cycle 1101 (dh) memory read line 1110 (eh) memory write and invalidate 1111 (fh) table 3-3. local-to-pci memory access command type code (c/be[3:0]#) memory read 0110 (6h) memory write 0111 (7h) memory read multiple 1100 (ch) dual address cycle 1101 (dh) memory read line 1110 (eh) memory write and invalidate 1111 (fh) table 3-4. local-to-pci i/o access command type code (c/be[3:0]#) i/o read 0010 (2h) i/o write 0011 (3h) table 3-5. local-to-pci configuration access command type code (c/be[3:0]#) configuration memory read 1010 (ah) configuration memory write 1011 (bh) section 3 pci bus interface pci signals iop 480 data book r2.0 3-2 ? 2000 plx technology, inc. all rights reserved. 3.4 pci signals the key pci bus control signals are: frame# ? 1->0 transition indicates the start of an access, 0->1 indicates the last data phase irdy#, trdy# ? indicate data transfer devsel# ? indicates target acceptance stop# ? indicates premature termination ad ? address during address phase c/be[3:0]# ? command during address phase, byte enables during data phase 3.4.1 pci signal timing diagrams timing diagram 3-1. direct slave write to 8-bit local bus ? pci signal protocol timing diagram 3-2. direct slave write of 15 lwords to 32-bit local bus ? pci signal protocol addr d0 7 0 0ns 250ns 500ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# 7 0 a d0 d14 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 0ns 250ns 500ns 750ns 1000ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# section 3 pci bus protocol pci bus interface iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 3-3 section 3 ? pb interface 3.5 pci bus protocol the pci bus master throttles irdy# and the pci bus slave throttles trdy# to insert pci bus wait state(s). a simple pci protocol follows. the pci bus samples at the positive (rising) edge of the pci clock, pclk. the pci bus is idle when frame# and irdy# are both samples. (for more detail, consult additional pci reference material.) an address phase occurs when frame# is first sampled as 0[1 0 transition]. thereafter, all clocks are data phases until the bus is idle. figure 3-1. wait states note: the figure represents a sequence of bus cycles. 3.6 bus arbitration pci bus arbitration is point-to-point, rather than bused, handshaking. a potential initiator requests the bus by asserting its req# pin, and acquires it when its gnt# pin is asserted on an idle bus. the iop 480 can use either an internal or external pci arbiter. the default is to use an external pci arbiter. however, for maximum iop 480 direct master performance, the internal pci arbiter should be used. the selection is made in pcictl[16]. refer to section 9, ? pci bus internal arbiter ? for more information on using the iop 480 ? s internal pci arbiters. iop 480 accessing iop 480 from pci bus iop 480 de-asserts trdy# when waiting on the local bus pci bus de-asserts irdy# or simply ends the cycle when it is not ready iop 480 accessing pci bus iop 480 can be programmed to de-assert irdy# read fifo is full when its pci initiator pci bus de-asserts trdy# when it is not ready accessing iop 480 from local bus iop 480 generates ready# when data is valid on the following clock edge local processor generates wait states with wait# iop 480 accessing local bus iop 480 generates wait states with wait# (programmable) local bus can respond to iop 480 requests with ready# pci bus local bus iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 4-1 section 4 ? direct slave op 4 direct slave operation 4.1 overview direct slave operations originate on the pci bus, transfer through the iop 480, and finally access the local bus. the iop 480 is a pci bus target and a local bus master. 4.1.1 direct slave the pci bus master reads from and writes to the local bus through one of four memory- or i/o-mapped pci spaces. 4.1.2 direct slave operation (pci master-to-local bus access) the iop 480 supports both burst memory-mapped transfer accesses and i/o-mapped, single-transfer accesses to the local bus from the pci bus through a 64-byte direct slave read fifo and a 128-byte direct slave write fifo. the pci base address registers are provided to set up the location of the adapter in pci memory and i/o space. in addition, local mapping registers allow address translation from pci address space to local address space. there are four available spaces: space 0 (memory-mapped only) space 1 space 2 expansion rom expansion rom space is intended to support a bootable rom device for the pci host. local bus burst transfers depend upon local bus region descriptors. for single-cycle direct slave reads, the iop 480 reads a single local bus lword or partial lword. the iop 480 disconnects after one transfer for all direct slave i/o accesses. for the highest data transfer rate, the iop 480 supports posted writes and can be programmed to prefetch data during a pci burst read. when the read prefetch register is enabled (set by bit 16 in the region descriptor), the prefetch count can be set to be programmed as 0, 4, 8, or 16 (set by bits [18:17] in the region descriptor register). the iop 480 prefetches, if enabled, and drops the local bus after reaching the prefetch counter value. in continuous prefetch mode, the iop 480 prefetches as long as fifo space is available and stops prefetching when the pci master completes or terminates the transfer. if read prefetching is disabled, the iop 480 disconnects after one read transfer. in addition to prefetch mode, the iop 480 supports read ahead mode (refer to section 4.6, ? pci read ahead mode (pcictl[22]), ? on page 4-5). each local address space can be programmed to operate with an 8-, 16-, or 32-bit local bus width. the iop 480 has an internal wait state generator and external wait state input, ready#. ready# can be disabled or enabled in the bus region descriptor registers. with or without wait state(s), the local bus, independent of the pci bus can burst as long as data is available (continuous burst mode) burst four lwords at a time (recommended) perform multiple single-cycle accesses 4.2 registers 4.2.1 pci bus access to internal registers the iop 480 pci configuration registers can be accessed from the pci bus with a configuration type 0 cycle. all other iop 480 internal registers can be accessed at offsets from local address space 0. space 0 is memory-mapped at the address in the pci base address 0 (pcibar0[31:10]) for the iop 480 memory- mapped configuration register. the internal registers take up 1k of space 0. all pci read or write accesses to iop 480 registers can be byte, word, or lword accesses. all pci memory accesses to iop 480 registers can be burst or non-burst accesses. accessing reserved registers returns 0 for reads, and writes have no effect. section 4 direct slave operation registers iop 480 data book r2.0 4-2 ? 2000 plx technology, inc. all rights reserved. 4.2.2 direct slave pci-to-local address mapping note: not applicable in i 2 o mode. four local address spaces ? space 0, space 1, space 2, and expansion rom ? are accessible from the pci bus. each is defined by a set of three registers: local address range (las0rr, las1rr, las2rr, and/or eromrr) local base address (las0ba, las1ba, las2ba, and/or eromba) pci base address (pcibar0, pcibar1, pcibar2, and/or pcierbar) the memory controller registers define the local bus characteristics for the direct slave regions (refer to figure 4-1 on page 4-3). each pci-to-local address space is defined as part of reset initialization. these local bus characteristics can be modified at any time before actual data transactions. 4.2.2.1 direct slave local bus initialization range ? specifies which pci address bits to use for decoding a pci access to local bus space. each bit corresponds to a pci address bit. bit 31 corresponds to address bit 31. write 1 to all bits that must be included in the decode and 0 to all others. (the range should be programmed before the other registers.) remap pci-to-local addresses into a local address space ? bits in this register remap (replace) the pci address bits used in decode as the local address bits. memory controller region descriptors ? specify the local bus characteristics. 4.2.2.2 direct slave pci initialization after pci reset, software determines the amount of address space required by writing all ones (1) to a pci base address register and then reading back the value. the iop 480 returns zeroes (0) in the don ? t care address bits, effectively specifying the address space required. the pci software then maps the local address space into the pci address space by programming the pci base address register. (refer to figure 4-1.) section 4 registers direct slave operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 4-3 section 4 ? direct slave op figure 4-1. direct slave access of local bus range for pci-to-local address space 0/1/2 local base address (remap) for pci-to-local address space 0/1/2 bus region descriptors for pci-to-local accesses range for pci-to-local expansion rom local base address (remap) for pci-to-local expansion rom pci base address to local address space 0/1/2 bus region descriptors for pci-to-local accesses pci base address to local expansion rom 1 initialize pci base address registers local bus hardware characteristics 2 fifos 32-lword deep write 16-lword deep read pci address space pci base address local bus access local memory local base address range pci bus access 3 4 internal iop 480 cpu or local processor pci bus master initialize registers from pci or local section 4 direct slave operation internal fifos iop 480 data book r2.0 4-4 ? 2000 plx technology, inc. all rights reserved. 4.3 internal fifos for direct slave memory accesses to the local bus, the iop 480 utilizes a 32-lword (128-byte) write fifo and a 16-lword (64-byte) read fifo. the fifos enable the pci bus to operate independently of the local bus, and allow high-performance bursting on the pci and local buses. for a direct slave write, the pci master writes data to the local bus slave. for a direct slave read, the pci master reads data from the local bus slave. illustrated in figure 4-4 and figure 4-5 are the fifos that function during a direct slave write and read. refer to table 4-1, which also lists the response of the iop 480 to full and empty fifos. table 4-1. response to fifo full or empty mode data direction fifo pci bus local bus direct master write local-to-pci full normal de-assert ready# empty de-assert req# (off pci bus) normal direct master read pci-to-local full de-assert req# or throttle irdy# 1 normal empty normal de-assert ready# direct slave write pci-to-local full disconnect or throttle trdy# 2 normal empty normal de-assert lhold, assert blast# 3 direct slave read local-to-pci full normal de-assert lhold, assert blast# 3 empty throttle trdy# 4 normal dma local-to-pci full normal de-assert lhold, assert blast# empty de-assert req# normal pci-to-local full de-assert req# normal empty normal de-assert lhold, assert blast# 1. throttle irdy# depends on the direct master pci read mode bit (dmpbam[6]). 2. throttle trdy# depends on the direct slave write bit (pcictl[27]). 3. de-assertion of lhold depends upon the local bus direct slave release bus mode bit (larbr[8]). 4. retry throttle trdy# depends upon direct slave read bit (pcictl[25]). de-assert trdy# if bit is equal to zero. if bit is equal to 1, retry. section 4 exclusive accesses direct slave operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 4-5 section 4 ? direct slave op 4.4 exclusive accesses the iop 480 supports direct pci-to-local-bus exclusive accesses (locked atomic operations). a pci-locked operation to the local bus results in the entire address space 0, space 1, space 2, and expansion rom space being locked until they are released by the pci bus master. locked operations are enabled or disabled with the direct slave lock# enable bit (larbr[9]) for pci-to-local accesses. 4.5 pci r2.2 delayed read mode the iop 480 can be programmed through the pci specification r2.2 mode bit (pcictl[25]=1) to perform delayed reads, as specified in pci specification r2.2 . figure 4-2. direct slave pci specification r2.2 delayed reads note: the figure represents a sequence of bus cycles. in addition to delayed reads, the iop 480 supports the following pci specification r2.2 functions: no writes allowed while read is pending ? pci retry for reads (pcictl[24]) write and flush pending read (pcictl[23]) 4.6 pci read ahead mode (pcictl[22]) the iop 480 also supports read ahead mode, where prefetched data can be read from the iop 480 internal fifo instead of the local bus. the address must be subsequent to the previous address and 32-bit aligned (next address=current address + 4). read ahead mode functions can be used with or without pci delayed read mode. figure 4-3. direct slave iop 480 read ahead mode note: the figure represents a sequence of bus cycles. 4.7 direct slave transfer transactions are initiated by a pci bus master addressing the memory space decoded for the local bus. upon a pci read/write, the iop 480 becomes a local bus master and arbitrates for the local bus. the iop 480 then reads data into the direct slave read fifo from the local bus or writes data to the local bus from the direct slave write fifo. the direct slave preempts dma only when the local arbiter is in direct slave high-priority mode (larbr[3:1] =0116). the iop 480 can be programmed to ? keep ? the pci bus by generating a wait state(s) and de-asserting trdy# if the write fifo becomes full. the iop 480 can also be programmed to ? keep ? the local bus. lhold is asserted if the direct slave write fifo becomes empty or the direct slave read fifo becomes full. in either case, the local bus is dropped when the local bus latency timer is enabled and expires (loctmr[7:0]). for direct slave writes, the pci bus writes data to the local bus. the direct slave is the ? command from the pci host, ? which has highest priority. for direct slave reads, the pci bus master reads data from the local bus slave. spec r2.2 mode is set in internal registers data is stored in 16-lword internal fifo iop 480 returns prefetched data immediately pci bus local bus pci read request iop 480 instructs pci host to retry read cycle later pci bus is free to perform other cycles during this time pci host returns to fetch read data again read data is now ready for host iop 480 request s read data from local bus local memory returns requested data to iop 480 iop 480 iop 480 pci bus local bus pci read request read data read data pci bus master read returns with ? sequential address ? iop 480 prefetche s data from local bus device read ahead mode is set in internal registers prefetched data is stored in the internal fifo iop 480 returns prefetched data immediately from internal fifo without reading again from the local bus iop 480 prefetches more data if fifo space is available iop 480 prefetches more data from local memory section 4 direct slave operation local bus byte enables iop 480 data book r2.0 4-6 ? 2000 plx technology, inc. all rights reserved. the iop 480 supports on-the-fly endian conversion for direct slave cycles. the local bus can be big/little endian by programming the memory controller registers. note: the pci bus is always little endian. figure 4-4. direct slave write figure 4-5. direct slave read note: the figures represents a sequence of bus cycles. 4.8 local bus byte enables during a direct slave transfer, each of four spaces (space 0, space 1, space 2, and expansion rom) can be programmed to operate in an 8-, 16-, or 32-bit local bus width by encoding the local byte enables (lbe[3:0]#). lbe[3:0]# is encoded, based on the configured bus width, as follows. 32-bit bus ? the four-byte enables indicate which of the four bytes are active during a data cycle. lbe3# byte enable 3 ? lad[31:24] lbe2# byte enable 2 ? lad[23:16] lbe1# byte enable 1 ? lad[15:8] lbe0# byte enable 0 ? lad[7:0] 16-bit bus ? lbe3#, lbe1# and lbe0# are encoded to provide bhe#, lad1, and ble#, respectively. lbe3# byte high enable (bhe#) ? lad[15:8] lbe2# not used lbe1# address bit 1 (lad1) lbe0# byte low enable (ble#) ? lad[7:0] 8-bit bus ? lbe1# and lbe0# are encoded to provide lad1 and lad0, respectively. lbe3# not used lbe2# not used lbe1# address bit 1 (lad1) lbe0# address bit 0 (lad0) 4.9 direct slave priority if the local arbiter is set in direct slave high-priority mode (larbr[3:1]=011b), direct slave accesses have a higher priority than dma accesses, thereby preempting dma transfers. during a dma transfer, if the iop 480 detects a pending direct slave access, it gives up the local bus within two data transfers. the iop 480 resumes operation after the direct slave access completes. when the iop 480 dma controller owns the local bus, its lhold output and lholda input are asserted. when a direct slave access occurs, the iop 480 gives up the local bus within two lword transfers by de-asserting lhold and floating the local bus outputs. after the iop 480 acknowledges that lholda is de-asserted, it requests the local bus for a direct slave transfer by asserting lhold. when the iop 480 receives lholda, it drives the bus and performs the direct slave transfer. upon completing a direct slave transfer, the iop 480 gives up the local bus by de-asserting lhold and floating the local bus outputs. after the iop 480 samples lholda as de-asserted, and the local bus pause timer is set to iop 480 lad, ads#, lwr#, blast# irdy#, ad (data) pci bus local bus lhold lholda ready# devsel#, trdy# frame#, c/be#, ad (addr) slave master master slave iop 480 lad, ads#, lwr#, blast# trdy#, ad (data) pci bus lhold lholda ready#, lad devsel# frame#, c/be#, ad (addr) irdy# slave master master slave local bus section 4 alignment direct slave operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 4-7 section 4 ? direct slave op zero, it requests a dma transfer from the local bus by re-asserting lhold. when it receives lholda, it drives the bus and continues the dma transfer. 4.10 alignment as a local bus master, the iop 480 supports unaligned transfers. for direct slave writes, the iop 480 breaks any partial write into a single access. it only bursts on the local bus if all byte enables are asserted. if all bytes are disabled (lbe[3:0]# = fh), the transfer is skipped. for direct slave reads, regardless of the pci byte enables, the iop 480 reads all bytes on the local bus during a burst prefetch transaction. for single reads, the iop 480 passes the byte enables. 4.11 direct slave example a 1 mb local address space 12300000h through 123fffffh is accessible from the pci bus at pci addresses 78900000h through 789fffffh. local initialization software sets the range and local base address registers as follows: range ? fff00000h (1 mb, decode the upper 12 pci address bits) local base address (remap) ? 123xxxxxh, (local base address for pci-to-local accesses) [space enable bit(s) must be set to be recognized by the pci host, (las1ba[0]=1) and (las2ba[0]=1)] for space 1 and space 2; however, space 0 and erom space are always set to enable [no space enable bit(s)] pci initialization software writes all ones to pci base address registers, then reads back the registers. the iop 480 returns a value of fff00000h. the pci software then writes to the pci base address register(s) pci base address ? 789xxxxxh (pci base address for access to local address space registers) for a pci direct access to the local bus, the iop 480 has a 32-lword (128 bytes) write fifo and a 16-lword (64 bytes) read fifo. fifos enable the local bus to operate independently of the pci bus. the iop 480 can be programmed to return a retry response or to throttle trdy# for any pci bus transaction attempting to write to the iop 480 local bus when the write fifo is full. for pci read transactions from the local bus, the iop 480 holds off trdy# while gathering data from the local bus. for read accesses mapped to pci memory space, the iop 480 prefetches 0 (no prefetch), 4, 8, or 16 lwords in read prefetch count enable mode, or prefetches continuously from the local bus until terminated by the pci bus or until a page boundary is reached. unused read data is flushed from the fifo. for read accesses mapped to pci i/o space, the iop 480 does not prefetch read data. rather, it breaks each read of a burst cycle into a single address/data cycle on the local bus. the direct slave retry delay clocks bits (pcictl[31:28]) can be used to program the time period in which the iop 480 holds off asserting trdy#. the iop 480 issues a retry to the pci bus transaction master when the programmed time period expires. this occurs when the iop 480 cannot gain control of the local bus and return trdy# within the programmed time period. table 4-2. direct slave local byte enable methods direct slave methods byte enables dsr burst don ? t pass dsr single / i/o pass dsw burst breakup burst for alignment dsw single / i/o pass dsw to 8-bit bus skip if no byte enables allowed section 4 direct slave operation timing diagrams iop 480 data book r2.0 4-8 ? 2000 plx technology, inc. all rights reserved. 4.12 timing diagrams 4.12.1 direct slave configuration cycle timing diagram 4-1. pci configuration write cmd=b be=0 data addr 0ns 100ns 200ns 300ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lholdreq1 lholdack1 ads# lwr# blast# ready# section 4 timing diagrams direct slave operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 4-9 section 4 ? direct slave op timing diagram 4-2. pci configuration read a 0 d0 addr 0ns 100ns 200ns 300ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lholdreq1 lholdack1 ads# lwr# blast# ready# section 4 direct slave operation timing diagrams iop 480 data book r2.0 4-10 ? 2000 plx technology, inc. all rights reserved. timing diagram 4-3. pci memory write 7 0 d0 addr 0ns 100ns 200ns 300ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lholdreq1 lholdack1 ads# lwr# blast# ready# section 4 timing diagrams direct slave operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 4-11 section 4 ? direct slave op timing diagram 4-4. pci memory read 6 0 d0 addr 0ns 100ns 200ns 300ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lholdreq1 lholdack1 ads# lwr# blast# ready# section 4 direct slave operation timing diagrams iop 480 data book r2.0 4-12 ? 2000 plx technology, inc. all rights reserved. 4.12.2 direct slave timing diagram 4-5. direct slave write to 32-bit local bus with zero wait states addr d0 7 0 laddr d0 0 0ns 100ns 200ns 300ns 400ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ale ads# lwr# blast# ready# section 4 timing diagrams direct slave operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 4-13 section 4 ? direct slave op timing diagram 4-6. direct slave read from 32-bit local bus with zero wait states d0 a 6 0 addr d0 0 0ns 250ns 500ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ale ads# lwr# blast# ready# section 4 direct slave operation timing diagrams iop 480 data book r2.0 4-14 ? 2000 plx technology, inc. all rights reserved. timing diagram 4-7. direct slave write to 32-bit local bus with one external (ready#) wait state addr d0 0 addr d0 7 0 0ns 100ns 200ns 300ns 400ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ale ads# lwr# blast# ready# section 4 timing diagrams direct slave operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 4-15 section 4 ? direct slave op timing diagram 4-8. direct slave write to 16-bit local bus with one external (ready#) wait state addr d0 7 0 a ld0 ld1 4 6 0ns 100ns 200ns 300ns 400ns 500ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ale ads# lwr# blast# ready# section 4 direct slave operation timing diagrams iop 480 data book r2.0 4-16 ? 2000 plx technology, inc. all rights reserved. timing diagram 4-9. direct slave write to 8-bit local bus with one external (ready#) wait state addr d0 7 0 addr ld0 ld3 c d e f ld1 ld2 0ns 250ns 500ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ale ads# lwr# blast# ready# section 4 timing diagrams direct slave operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 4-17 section 4 ? direct slave op timing diagram 4-10. direct slave read from 32-bit local bus with three external (ready#) wait states d0 0 addr 6 a 0 d0 0ns 250ns 500ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ale ads# lwr# blast# ready# wait# section 4 direct slave operation timing diagrams iop 480 data book r2.0 4-18 ? 2000 plx technology, inc. all rights reserved. timing diagram 4-11. direct slave read from 32-bit local bus with three internal (wait#) wait states d0 0 addr 6 laddr 0 d0 note: blast# timing shown assumes locctl[19]=0. if locctl[19]=1, blast# assertion is delayed until wait# is de-asserted. 0ns 250ns 500ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ale ads# lwr# blast# ready# wait# section 4 timing diagrams direct slave operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 4-19 section 4 ? direct slave op timing diagram 4-12. direct slave pci write of six lwords to 32-bit local bus, burst disabled 0 a a a a a a d0 d1 d2 d3 d4 d5 addr d0 d5 7 0 d1 d2 d3 d4 0ns 250ns 500ns 750ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ale ads# lwr# blast# ready# section 4 direct slave operation timing diagrams iop 480 data book r2.0 4-20 ? 2000 plx technology, inc. all rights reserved. timing diagram 4-13. direct slave pci write of three lwords to 16-bit local bus, burst disabled 4 6 4 6 6 4 a d a d a d a d a d a d a d0 d2 7 0 d1 0ns 250ns 500ns 750ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ale ads# lwr# blast# ready# section 4 timing diagrams direct slave operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 4-21 section 4 ? direct slave op timing diagram 4-14. direct slave pci read of six lwords to 32-bit local bus, burst disabled 0 a a a a a a a a a a d0 d1 d2 d3 d4 d5 x x x x d0 d5 addr 6 0 d1 d2 d3 d4 0ns 250ns 500ns 750ns 1000ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ale ads# lwr# blast# ready# section 4 direct slave operation timing diagrams iop 480 data book r2.0 4-22 ? 2000 plx technology, inc. all rights reserved. timing diagram 4-15. direct slave pci write of six lwords to 32-bit local bus, burst disabled, one external (ready#) wait state 0 a a a a a a a a a a d d d d d d d d d d d0 d5 addr 6 0 d1 d2 d3 d4 0ns 250ns 500ns 750ns 1000ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ale ads# lwr# blast# ready# section 4 timing diagrams direct slave operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 4-23 section 4 ? direct slave op 4.12.3 direct slave burst timing diagram 4-16. direct slave pci write of six lwords to 32-bit local bus, local burst enabled, one external (ready#) wait state 0 a a a a a a d0 d1 d2 d3 d4 d5 d0 d5 addr 6 0 d1 d2 d3 d4 0ns 250ns 500ns 750ns 1000ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ale ads# lwr# blast# ready# section 4 direct slave operation timing diagrams iop 480 data book r2.0 4-24 ? 2000 plx technology, inc. all rights reserved. timing diagram 4-17. direct slave pci write of six lwords to 16-bit local bus, local burst enabled, one external (ready#) wait state addr d0 d2 7 0 a d d 4 6 4 6 4 6 d1 0ns 250ns 500ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ale ads# lwr# blast# ready# section 4 timing diagrams direct slave operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 4-25 section 4 ? direct slave op timing diagram 4-18. direct slave pci write of three lwords to 8-bit local bus, local burst enabled, one external (ready#) wait state c d e f c d e f c d e f 0 6 addr d0 d2 a d d d1 0ns 250ns 500ns 750ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ale ads# lwr# blast# ready# section 4 direct slave operation timing diagrams iop 480 data book r2.0 4-26 ? 2000 plx technology, inc. all rights reserved. timing diagram 4-19. direct slave pci write of 15 lwords to 32-bit local bus, local burst enabled, one external (ready#) wait state, bterm enabled 0 7 0 a d0 d14 a d0 d3 a d5 d6 d14 a d4 d1 d2 d7 d8 d9 d10 d11 d12 d13 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 0ns 250ns 500ns 750ns 1000ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ale ads# lwr# blast# ready# bterm# section 4 timing diagrams direct slave operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 4-27 section 4 ? direct slave op timing diagram 4-20. direct slave pci write of 15 lwords to 32-bit local bus, local burst enabled, one external (ready#) wait state, bterm disabled 7 0 0 a d0 d14 a d0 d3 a d4 d7 a d8 d11 a d12 d14 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d1 d2 d5 d6 d9 d10 d13 0ns 250ns 500ns 750ns 1000ns 12 5 pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ale ads# lwr# blast# ready# section 4 direct slave operation timing diagrams iop 480 data book r2.0 4-28 ? 2000 plx technology, inc. all rights reserved. timing diagram 4-21. direct slave burst read of five lwords to 32-bit local bus, burst enabled, prefetch counter of 16, zero wait states addr d0 d4 6 0 0 a d0 d1 d2 d3 d1 d2 d3 d4 0ns 250ns 500ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ale ads# lwr# blast# ready# iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 5-1 section 5 ? direct master op 5 direct master operation 5.1 overview direct master operations originate on the local bus, go through the iop 480, and finally access the pci bus. the iop 480 will be a local bus slave and a pci bus master. all direct master operations require a 32-bit wide bus region. 5.1.1 direct master local bus cycles can be continuous single or burst cycles (programmable through the iop 480 internal registers). as a local bus target, the iop 480 allows access to the iop 480 internal registers and the pci bus. 5.1.2 direct master operation (local master-to-direct slave) the iop 480 supports a direct access of the pci bus by the local processor or an intelligent controller. direct master mode must be enabled in the pci command register. the following registers define local-to-pci accesses: direct master memory and i/o range (dmrr) local base address for direct master-to-pci memory (dmlbam) local base address for direct master-to-pci i/o and configuration (dmlbai) pci base address (dmpbam) direct master configuration (dmcfga) direct master dual address cycles (dmdac) 5.1.2.1 direct master memory and i/o decode the range register and local base address specifies the local address bits to use for decoding a local- to-pci access. the range of memory or i/o space must be a power of 2 and the range register value must be the inverse of the range value. in addition, the local base address must be a multiple of the range value. any local master address starting from the direct master local base address (memory or i/o) to the range value is recognized as a direct master access by the iop 480. all direct master cycles are then decoded as pci memory, i/o, or configuration type 0 or type 1. moreover, a direct master memory or i/o cycle is remapped according to the remap register value. the remap register value must be a multiple of the direct master range value. the local range registers determine whether to remap addresses to pci memory or to pci i/o space. 5.1.3 pci command codes for direct local-to-pci bus accesses, the iop 480 asserts the cycles listed in the following tables. table 5-1. local-to-pci memory access command type code (c/be[3:0]#) memory read 0110 (6h) memory write 0111 (7h) memory read multiple 1100 (ch) dual address cycle 1101 (dh) memory read line 1110 (eh) memory write and invalidate 1111 (fh) table 5-2. local-to-pci i/o access command type code (c/be[3:0]#) i/o read 0010 (2h) i/o write 0011 (3h) table 5-3. local-to-pci configuration access command type code (c/be[3:0]#) configuration memory read 1010 (ah) configuration memory write 1011 (bh) section 5 direct master operation internal fifos iop 480 data book r2.0 5-2 ? 2000 plx technology, inc. all rights reserved. 5.2 internal fifos for direct master memory accesses to the pci bus, the iop 480 has a 32-lword (128-byte) write fifo and a 16-lword (64-byte) read fifo. the fifos enable the local bus to operate independently with the pci bus and allow high-performance bursting on the pci and local buses. for a direct master write, the local processor (master) writes data to the pci bus (slave). for a direct master read, the local processor (master) reads data from the pci bus (slave). fifos functioning during a direct master write and read are illustrated in figure 5-1 and figure 5-2. (refer also to table 5-4.) figure 5-1. direct master write figure 5-2. direct master read note: the figures represent a sequence of bus cycles. iop 480 slave master master slave req# gnt# frame#, c/be# ad (addr) irdy# devsel#, trdy# ad (data) lad, ads#, lbe#, lwr#, blast# ready# pci bus local bus local bus pci bus iop 480 slave master master slave req# gnt# frame#, c/be#, ad (addr) irdy# devsel#, trdy#, ad (data) lad, ads#, lwr# lad, ready# blast# table 5-4. response to fifo full or empty mode data direction fifo pci bus local bus direct master write local-to-pci full normal de-assert ready# empty de-assert req# (off pci bus) normal direct master read pci-to-local full de-assert req# or throttle irdy# 1 1. throttle irdy# depends on the direct master pci read mode bit (dmpbam[6]). normal empty normal de-assert ready# direct slave write pci-to-local full disconnect or throttle trdy# 2 2. throttle trdy# depends on the direct slave write bit (pcictl[27]). normal empty normal de-assert lhold, assert blast# 3 3. de-assertion of lhold depends upon the local bus direct slave release bus mode bit (larbr[8]). direct slave read local-to-pci full normal de-assert lhold, assert blast# 3 empty throttle trdy# 4 4. retry throttle trdy# depends upon direct slave read bit (pcictl[25]). de-assert trdy# if the bit is equal to zero. if the bit is equal to 1, retry. normal dma local-to-pci full normal de-assert lhold, assert blast# empty de-assert req# normal pci-to-local full de-assert req# normal empty normal de-assert lhold, assert blast# section 5 internal fifos direct master operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 5-3 section 5 ? direct master op figure 5-3. direct master access of pci bus pci bus master internal iop 480 cpu or local processor local range for direct master-to-pci (dmrr) local base address for direct master-to-pci memory (dmlbam) dual address-upper address (dmdac) pcl base address (remap) for direct master-to-pci (dmpbam) local base address for direct master-to-pci i/o configuration (dmlbai) pci configuration address register for direct master-to-pci i/o configuration (dmcfga) pci command register (pcicr) 1 initialize registers from pci or local i/o or configuration configuration 0 = i/o 1 = fifos 32-lword deep write 16-lword deep read local base address for pci initiator-to- pci memory space pci address space* pci base address local base address for pci initiator-to- pci i/o configuration local bus access local memory memory command i/o command range range pci bus access 3 2 * note: memory commands are in memory space, i/o commands are in i/o space, and configuration commands are in configuration space. section 5 direct master operation pci memory access iop 480 data book r2.0 5-4 ? 2000 plx technology, inc. all rights reserved. 5.3 pci memory access the local processor can read or write to the pci memory. the iop 480 converts the local read/write access. the local address space starts from the direct master local base address up to the range. remap (pci base address) defines the pci starting address. writes ? iop 480 continues to accept writes and returns ready# until the write fifo is full. it then holds off ready# until space becomes available in the write fifo. a programmable direct master fifo ? almost full ? status output is provided (dmpaf). (refer to figure 5-1.) reads ? iop 480 holds off ready# while gathering an lword from the pci bus. programmable prefetch modes are available if prefetch is enabled: prefetch, 4, 8, 16, or continuous until the direct master cycle ends. the read cycle is terminated when local blast# input is asserted. unused read data is flushed from the fifo. (refer to figure 5-2.) the iop 480 does not prefetch read data for single-cycle direct master reads (local blast# input asserted during the first data phase). in this case, the iop 480 reads a single pci lword. for direct master single-cycle reads, the iop 480 sets the same pci bus byte enables as the local bus. for multiple-cycle reads, the iop 480 reads multiple entire lwords (all pci bus byte enables are set). for multiple-cycle writes, the iop 480 sets the same pci bus byte enables as the local bus. if the direct master prefetch limit bit is enabled (dmpbam[5]=1), the iop 480 does not prefetch past a 4-kb boundary. also, the local bus must not cross a 4-kb boundary during a burst read. the iop 480 never prefetches beyond the region specified for direct master accesses. 5.4 pci i/o access when a local direct master i/o access to the pci bus occurs, the pci configuration address register for direct master-to-pci i/o configuration enable bit (dmcfga[31]) determines whether an i/o or configuration access is to be made to the pci bus. local burst accesses are broken into single pci i/o address/data cycles. the iop 480 does not prefetch read data for i/o or configuration reads. for direct master i/o or configuration cycles, the iop 480 asserts the same pci bus byte enables as set on the local bus. if the configuration enable bit is cleared (dmcfga[31]=0), a single i/o access is made to the pci bus. the local address, remapped decode address bits, and local byte enables are encoded to provide the address and are output with an i/o read or write command during a pci address cycle. when the i/o remap select bit is set (dmpbam[15]=1), the pci address bits [31:16] are forced to 0 for the 64k i/o address limit. for writes, data is loaded into the write fifo and ready# is returned to the local bus. for reads, the iop 480 holds off ready# while receiving an lword from the pci bus. 5.5 pci configuration access when a local direct master i/o access to the pci bus occurs, the pci configuration address register for direct master-to-pci i/o configuration enable bit (dmcfga[31]) determines whether an i/o or configuration access is to be made to the pci bus. if the configuration enable bit (dmcfga[31]) is set, a configuration access is made to the pci bus. in addition to enabling configuration of this bit, the user must provide all register information. the register number bits and device number bits (dmcfga[7:2, 15:11], respectively) must be modified and a new configuration read/write cycle must be performed before accessing other registers or devices. section 5 pci dual address cycle direct master operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 5-5 section 5 ? direct master op if the pci configuration address register selects a type 0 command, bits [10:0] of the register are copied to address bits [10:0]. bits [15:11] (device number) are translated into a single bit being set in the pci address bits [31:11]. the pci address bits [31:11] can be used as a device select. for a type 1 command, bits [23:0] are copied from the register to bits [23:0] of the pci address. the pci address bits [31:24] are 0. a configuration read or write command code is output with the address during the pci address cycle (refer to the dmcfga register). for writes, local data is loaded into the write fifo and ready# is returned. for reads, the iop 480 holds off ready# while gathering an lword from the pci bus. 5.5.1 configuration cycle example to perform a type 0 configuration cycle to pci device on ad[21]: 1. the iop 480 must be configured to allow direct master access to the pci bus. the iop 480 must also be set to respond to i/o space accesses. these bits must be set (pcicr[2:0]=111b). in addition, direct master memory and i/o access must be enabled (dmpbam[1:0]=11b). 2. the local memory map selects the direct master range. for this example, use a range of 1 mb: 1 mb=2 20 =000fffffh the value to program into the range register is the inverse of 000fffffh (fff00000h): dmrr=fff00000h 3. the local memory map determines the local base address for the direct master-to-pci i/o configuration register. for this example, use 40000000h: dmlbai=40000000h 4. the pci address (remap) for direct master-to-pci memory register must enable the direct master i/o access. the direct master i/o access enable bit must be set (dmpbam[1]=1). 5. the user must know which pci device and pci configuration register the pci configuration cycle is accessing. this example assumes the idsel signal of the target pci device is connected to ad[21] (logical device #10=0ah). also access pcibar0 (the fourth register, counting from 0). set dmcfga[31, 23:0) as follows: after these registers are configured, a simple local master memory cycle to the i/o base address is necessary to generate a pci configuration read or write cycle. offset to the base address is not necessary because the register offset for the read or write is specified in the configuration register. the iop 480 takes the local bus master memory cycle and checks for the configuration enable bit (dmcfga[31]). if set, the iop 480 converts the current cycle to a pci configuration cycle, using the dmcfga register and the write/read signal (lwr#). 6. the register number bits and device number bits (dmcfga[7:2, 15:11], respectively) must be modified and a new configuration read/write cycle must be performed before accessing other registers or devices. 5.6 pci dual address cycle the iop 480 supports pci dual address cycle (dac) when it is a pci bus master using the dmdac register for direct master transactions. the dac command is used to transfer a 64-bit address to devices that support 64-bit addressing when the address is not in the low 4 gb address space. the iop 480 performs a dac within two pci clock periods, where the first pci address is a lo-addr with the command (c/be[3:0]#) ? d ? and the second pci address is a hi-addr with the command (c/be[3:0]#) ? 6 ? or ? 7 ? , depending upon it being a pci read or a pci write cycle. when the dmdac register contains a value of 0h, the iop 480 performs a single address cycle (sac) on the pci bus. bit description value 1:0 configuration type 0. 00b 7:2 register number. fourth register. must program a ? 4 ? into this value, beginning with bit 2. 000100b 10:8 function number. 000b 15:11 device number n-11, where n is the value in ad[n]=21-11=10. 01010b 23:16 bus number. 00000000b 31 configuration enable. 1 section 5 direct master operation targ et ab or t iop 480 data book r2.0 5-6 ? 2000 plx technology, inc. all rights reserved. 5.7 target abort the iop 480 master/target abort logic enables a local bus master to perform a direct master bus poll of devices to determine whether devices exist (typically when the local bus performs configuration cycles to the pci bus). when a pci master device attempts to access and does not receive devsel# within six pci clocks, it results in a master abort. the local bus master must clear the received master abort bit or target abort bit (pcisr[13 or 12]=0, respectively) and continue by processing the next task. if a pci master, target abort, or retry timeout is encountered during a transfer, the iop 480 asserts into if enabled (lintenb[1:0]=1). if a local bus master is waiting for ready#, it is asserted along with bterm#. the local master ? s interrupt handler can take the appropriate application-specific action. it can then clear the target abort bit (pcisr[12]) to de-assert the into interrupt and re-enable direct master transfers. if a local bus master is attempting a burst read from a nonresponding pci device (master/target abort), it receives ready# and bterm# for the first cycle only. in addition, the iop 480 asserts into if the enable local bus into bits are enabled (lintenb[1:0]). if the local processor cannot terminate its burst cycle, it may cause the local processor to hang. in this case, look at locctl[25]. 5.8 memory write and invalidate the iop 480 can be programmed to perform memory write and invalidate cycles to the pci bus for direct master transfers, as well as for dma transfers. the iop 480 supports memory write and invalidate transfers for cache line sizes of 8 or 16 lwords. size is specified in the system cache line size bits (pciclsr[7:0]). if a size other than 8 or 16 is specified, the iop 480 performs write transfers rather than memory write and invalidate transfers. direct master memory write and invalidate transfers are enabled when invalidate enable (dmpbam[7]) and memory write and invalidate enable (pcicr[4]) are set. in memory write and invalidate mode, if the start address of the direct master transfer is on a cache line boundary, the iop 480 waits until the number of lwords required for the specified cache line size are written from the local bus before starting a pci memory write and invalidate access. this ensures a complete cache line write can complete in one pci bus ownership. if the start address is not on a cache line boundary, the iop 480 starts a normal pci write access (pci command 7h). the iop 480 terminates a cycle at a cache line boundary if it is performing a normal write or a memory write and invalidate cycle and another cache line of data is not available. if an entire cache line is available by the time iop 480 regains use of the pci bus, the iop 480 resumes memory write and invalidate cycles; otherwise, it continues with a normal write. if a target disconnects before a cache line is completed, the iop 480 completes the remainder of that cache line, using normal writes. 5.9 deadlock conditions deadlock can occur when a pci bus master must access the iop 480 local bus at the same time a master on the iop 480 local bus must access the pci bus. there are two types of deadlock: partial deadlock ? a local bus master is performing a direct bus master access to a pci bus device other than the pci bus device concurrently trying to access the local bus full deadlock ? a local bus master is performing a direct bus master access to the same pci bus device concurrently trying to access the local bus this applies only to direct master and direct slave accesses through the iop 480. deadlock does not occur in transfers through the iop 480 dma channels or the iop 480 internal registers (such as mailboxes). section 5 deadlock conditions direct master operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 5-7 section 5 ? direct master op for partial deadlock, the pci access to the local bus times out (the direct slave retry delay clock (lbrd0[31:28]), which is programmable through the local bus region descriptor register) and the iop 480 responds with a pci retry. the pci specification requires that a pci master release its request for the pci bus (de-assert req#) for a minimum of two pci clocks after receiving a retry. this allows the pci bus arbiter to grant the pci bus to the iop 480 so that it can complete its direct master access and free up the local bus. possible solutions are described below for cases in which the pci bus arbiter does not function as described (pci bus architecture dependent), waiting for a time out is undesirable, or a full deadlock condition exists. for full deadlock, the only solution is to backoff the local bus master. 5.9.1 backoff the iop 480 boff# signal indicates whether a possible deadlock condition exists. the iop 480 starts the backoff timer (programmable through registers) when it detects the following conditions: a pci bus master is attempting to access memory or an i/o device on the local bus and is not gaining access ( for example , lholda is not received). a local bus master is performing a direct bus master read access to the pci bus. or, a local bus master is performing a direct bus master write access to the pci bus and the iop 480 direct master write fifo cannot accept another write cycle. if the local bus backoff enable bit is enabled (eromba[4]=1) and expires and the iop 480 has not received lholda, the iop 480 asserts boff#. external bus logic can use this signal to perform backoff. the backoff cycle is device/bus architecture dependent. external logic (an arbiter) can assert the necessary signals necessary to cause a local bus master to release a local bus (backoff). after the local bus master backs off, it can grant the bus to the iop 480 by asserting lholda. once boff# is asserted, ready# for the current data cycle is never asserted (the local bus master must perform backoff). when the iop 480 detects lholda, it proceeds with the pci master-to-local bus access. when this access completes and the iop 480 releases the local bus, external logic can release the backoff and the local bus master can resume the cycle interrupted by the backoff cycle. the iop 480 write fifo retains all data it acknowledged ( that is , the last data for which ready# was asserted). after the backoff condition ends, the local bus master restarts the last cycle with ads#. for writes, data following ads# should be the data the iop 480 did not acknowledge prior to the backoff cycle ( for example , the last data for which ready# is not asserted). if a pci read cycle completes when the local bus is backed off, the local bus master receives that data if the local master restarts the same last cycle (data is not read twice). a new read is performed if the resumed local bus cycle is not the same as the backed off cycle. 5.9.2 software/hardware solution for systems without backoff capability for adapters that do not support backoff, a possible deadlock solution is as follows. pci host software, external local bus hardware, general purpose output user0/user1 and general purpose input user3/user4 can be used by the pci host software to prevent deadlock. user0/ user1 can be asserted to request that the external arbiter not grant the bus to any local bus master except the iop 480. status output from the local arbiter can be connected to the general purpose input user3/user4 to indicate that no local bus master owns the local bus, or the pci host to determine that no local bus master that currently owns the local bus can read input. the pci host can then perform direct slave access. when the host finishes, it de-asserts user0/user2. 5.9.3 software solution to deadlock pci host software and local bus software can use a combination of mailbox registers, doorbell registers, interrupts, direct local-to-pci accesses and direct pci-to-local accesses to avoid deadlock. section 5 direct master operation timing diagrams iop 480 data book r2.0 5-8 ? 2000 plx technology, inc. all rights reserved. 5.10 timing diagrams 5.10.1 direct master configuration cycle timing diagram 5-1. local master configuration write 0 d0 addr 0ns 100ns 200ns 300ns 400ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lholdreq1 lholdack1 lad[31:0] lbe[3:0]# ads# lwr# blast# ready# section 5 timing diagrams direct master operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 5-9 section 5 ? direct master op timing diagram 5-2. local master configuration read 0 addr d0 0ns 100ns 200ns 300ns 400ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lholdreq1 lholdack1 lad[31:0] lbe[3:0]# ads# lwr# blast# ready# section 5 direct master operation timing diagrams iop 480 data book r2.0 5-10 ? 2000 plx technology, inc. all rights reserved. 5.10.2 direct master operation timing diagram 5-3. direct master single memory write a d0 0 addr 7 0 d0 0ns 100ns 200ns 300ns 400ns lclk lad[31:0] lbe[3:0]# ads# lwr# blast# ready# pclk req# gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# section 5 timing diagrams direct master operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 5-11 section 5 ? direct master op timing diagram 5-4. direct master single memory read a d0 0 a d0 6 0 0ns 250ns 500ns lclk lad[31:0] lbe[3:0]# ads# lwr# blast# ready# pclk req# gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# section 5 direct master operation timing diagrams iop 480 data book r2.0 5-12 ? 2000 plx technology, inc. all rights reserved. timing diagram 5-5. direct master i/o write a d 0 a 3 0 d 0ns 100ns 200ns 300ns 400ns lclk lad[31:0] lbe[3:0]# ads# lwr# blast# ready# pclk req# gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# section 5 timing diagrams direct master operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 5-13 section 5 ? direct master op timing diagram 5-6. direct master i/o read a d0 0 a d0 2 0 0ns 250ns 500ns lclk lad[31:0] lbe[3:0]# ads# lwr# blast# ready# pclk req# gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# section 5 direct master operation timing diagrams iop 480 data book r2.0 5-14 ? 2000 plx technology, inc. all rights reserved. timing diagram 5-7. direct master burst write of 12 lwords 7 0 a d0 d11 a d11 d0 0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 0ns 250ns 500ns 750ns lclk lholdreq1 lholdack1/breq lad[31:0] lbe[3:0]# ads# lwr# blast# ready# wait# pclk req# gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# section 5 timing diagrams direct master operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 5-15 section 5 ? direct master op timing diagram 5-8. direct master burst read of 12 lwords with wait# 6 0 a d0 d11 a 0 0 d11 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 xxxxx 0ns 250ns 500ns 750ns 1000ns lclk lholdreq1 lholdack1 lad[31:0]# lbe[3:0]# ads# lwr# blast# ready# wait# pclk req# gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# section 5 direct master operation timing diagrams iop 480 data book r2.0 5-16 ? 2000 plx technology, inc. all rights reserved. timing diagram 5-9. direct master configuration write type 0 f 5 00000000 ffffffff 0000 0 f ffffffff 5a5a5a5a f a 0 f 5 0ns 250ns 500ns pclk gnt0#/req# req0/#gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# devsel# stop# lock# lclk ads# lad[31:0] ma[12:0] lbe[3:0]# blast# ready# bterm# lwr# rd# lholdack0/ldreq lholdack1/breq lholdreq0/lholdack lholdreq1 llock# section 5 timing diagrams direct master operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 5-17 section 5 ? direct master op timing diagram 5-10. direct master configuration read type 1 5 f b 0 f ffffffff 00000002 ffffffff f 0 f 0ns 250ns 500ns pclk gnt0#/req# req0#/gnt# frame ad[31:0] cbe[3:0]# irdy# trdy# devsel# stop# lock# lclk ads# ale lad[31:0] ma[12:0] lbe[3:0]# blast# ready# lwr# rd# lholdack0/ldreq lholdack1/breq lholdreq0/lholdack lholdreq1 llock# section 5 direct master operation timing diagrams iop 480 data book r2.0 5-18 ? 2000 plx technology, inc. all rights reserved. timing diagram 5-11. direct master pci dual address cycle 5 ffffffff ffffffff 05d5 05c2 05c0 05c1 ffffffff 5a5a5a5a f d 7 0 f 5 0ns 250ns 500ns 750ns pclk gnt0#req# req0#gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# devsel# stop# lock# lclk ads# ale lad[31:0] ma[12:0] lbe[3:0]# blast# ready# bterm# lwr# rd lholdack0/ldreq lholdack1/breq lholdreq0/lholdack lholdreq1 llock# iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 6-1 section 6 ? cpu bus interface 6 iop 480 cpu bus interface 6.1 overview the iop 480 cpu can access both the local and pci buses, as well as the serial port unit (spu). when accessing the local bus, it acts very similar to a direct slave operation accessing the local bus. when accessing the pci bus, it acts exactly as a direct master operation. the iop 480 cpu is the only device that can access the spu, and no external bus activity is generated. 6.2 initialization the iop 480 cpu, after reset, reads from local address 0xfffffffc. the default (if not programmed differently by way of the serial eeprom) is for this to be an 8-bit-wide bus region, as described by the local chip select 0 bus region descriptor register (lcs0brd). this address should be programmed with a branch instruction to branch to wherever (in local address space) the rest of the initialization code lies. if the default iop 480 register values are used, the initialization code can be located anywhere from 0xfff00000 to 0xfffffffc, which is located in the register described by [lcs0bra]. 6.3 accessing the spu the iop 480 cpu is the only device that can access the internal serial port unit (spu), and this is only at the fixed address range of 0x4000000 to 0x40000020. the spu is on an internal 8-bit-wide bus, so only byte instructions should be used for spu access. refer to section 22, ? serial port operation, ? for more information. 6.4 accessing the local bus the iop 480 cpu accesses the local bus in much the same way as a direct slave operation accesses the local bus. 6.4.1 internal iop 480 cpu burst when the internal iop 480 cpu is the local bus master, the maximum number of bytes the iop 480 bursts is 16. 6.4.1.1 loads and stores for load and store operations, the iop 480 cpu reads and writes a maximum of four bytes. word address is specified by lad[31:2] during an address cycle, and byte lanes involved in the transfer are specified by lbe[3:0]#. 6.4.1.2 cache line fills/flushes for cache line fills and flushes, the iop 480 cpu always transfers 16 bytes. byte lanes involved in the transfers are specified by lbe[3:0]#. 6.5 accessing the pci bus the iop 480 cpu can access the pci bus in exactly the same method as a direct master transaction. the iop 480 cpu first acquires the local bus, and then hits are to the direct master regions, either memory or i/o. refer to section 5, ? direct master operation, ? for more information. 6.6 alignment the iop 480 cpu supports aligned and unaligned bus transfers. alignment rules for load and stores are based on address offsets from word boundaries. table 6-1 through table 6-6 describe the bus accesses resulting from aligned and unaligned loads and stores for various bus widths. section 6 iop 480 cpu bus interface alignment iop 480 data book r2.0 6-2 ? 2000 plx technology, inc. all rights reserved. table 6-1. iop 480 cpu byte load/store transactions address offset from lword boundary (in bytes) 8-bit bus 16-bit bus 32-bit bus n/a byte access byte access byte access table 6-2. three-byte load/store transactions address offset from lword boundary (in bytes) 8-bit bus 16-bit bus 32-bit bus +0 (aligned) 3-byte burst burst of one word and one byte 3-byte access +1 3-byte burst burst of one byte and one word 3-byte access +2 n/a +3 table 6-3. single-lword load/store transactions address offset from lword boundary (in bytes) 8-bit bus 16-bit bus 32-bit bus +0 4-byte burst two word bursts lword access +1 3-byte burst; byte access burst of one byte and one word; byte access 3-byte access; byte access +2 2-byte burst; 2-byte burst word access; word access word access; word access +3 byte access; 3-byte burst byte access; burst of one byte and one word byte access; 3-byte access table 6-4. four-lword cache line fills/flushes address offset from lword boundary (in bytes) 8-bit bus 16-bit bus 32-bit bus +0 16-byte burst 8-word burst 4-lword burst +1 n/a +2 +3 table 6-5. iop 480 cpu loads/stores local bus width transfers bytes transferred starting addresses address bits incremented during transfer 8 bits 4 max 4 max lbe[1:0]# (a[1:0]) lbe[1:0]# (a[1:0]) 16 bits 2 max 4 max lbe1# (a1) lbe1# (a1) 32 bits 1 max 4 max ? none table 6-6. iop 480 cpu cache line fills/flushes local bus width transfers bytes transferred starting addresses address bits incremented during transfer 8 bits 16 16 ma[3:2] = 00 lbe[1:0]# (a[1:0]) = 00 ma[3:2], lbe[1:0]# (a[1:0]) 16 bits 8 16 ma[3:2] = 00 lbe1# (a1) = 0 ma[3:2], lbe1# (a1) 32 bits 4 16 ma[3:2] = 00 ma[3:2] section 6 timing diagrams iop 480 cpu bus interface iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 6-3 section 6 ? cpu bus interface 6.7 timing diagrams 6.7.1 iop 480 cpu bootup cycle timing diagram 6-1. iop 480 cpu after reset start address fffffffc fffffffff 5a5a5a5a f 5 fffffffff 00000000 0000 f 0 c fffffffc 0ns 500ns 1000ns 1500ns pclk gnt0#/req# req0#/gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# devsel# stop# lock# lclk ads# ale lad[31:0] ma[12:0] lbe[3:0]# blast# ready# bterm# lwr# rd# lholdack0/ldreq lholdack1/breq lholdreq0/lholdack lholdreq1 reset# iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 7-1 section 7 ? dma operation 7 dma operation 7.1 dma channels 0 and 1 7.1.1 overview the iop 480 supports three independent dma channels capable of transferring data from: local-to-pci bus (dma ch 0/ch1) pci-to-local bus (dma ch 0/ch1) local-to-local bus (dma ch 2 only) dma channel 0 has a programmable 32-lword bi-directional fifo, while dma channel 1 has a programmable 16-lword bi-directional fifo. both channels support block transfers, scatter/gather transfers, and an end of transfer pin (eot#). both channels also support demand mode dma transfers. for dma transfers, the pci master enable bit must be enabled in pcicr[2] before the iop 480 can become a pci bus master. in addition, both dma channels 0 and 1 can be programmed to: operate with 8-, 16-, or 32-bit local bus width use 0-15 internal wait states (local bus) data-to-data enable/disable local bus burst capability limit local bus bursts to four (bterm# enable/disable) hold local address constant (local target is fifo) or increment perform pci memory write and invalidate (command code = fh) or normal pci memory write (command code = 7h) end local transfer with/without blast# (dma fast/slow termination) assert pci interrupt (inta#) or local interrupt (into) when dma transfer is complete or terminal count is reached during scatter/gather dma mode transfers operate in dma clear count mode pause/poll/skip invalid descriptors eot# to end a link or whole chain the iop 480 dma controllers also support dual address pci registers (c0pcihadr and c1pcihadr). the local bus latency timer determines the number of local clocks the iop 480 can hold the local bus before relinquishing it. the local pause timer starts after lholda is de-asserted. it sets the number of local bus clocks to wait after relinquishing the bus before the dma channel can request the local bus. 7.1.2 pci dual address cycle the iop 480 supports pci dual address cycle (dac) for dma. for scatter/gather dma, set c0mode[17] and/or c1mode[17] to 1. the dac command is used to transfer a 64-bit address to devices that support 64-bit addressing when the address is not in the low 4-gb address space. the iop 480 performs a dac within two pci clock periods, where the first pci address is a lo-addr with the command (c/be[3:0]#) ? d ? and the second pci address is a hi-addr with the command (c/be[3:0]#) ? e ? or ? 7 ? (pci read or write cycle). when the c0pcihadr or c1pcihadr register contains a value of 0h, the iop 480 performs a single address cycle (sac) on the pci bus. (refer to figure 7-3 on page 7-3.) figure 7-1. dma, pci-to-local bus note: the figure represents a sequence of bus cycles. iop 480 lad, ads#, lwr#, blast# devsel#, trdy#, ad (data) lhold lholda ready# slave master master slave dma start (c1locadr & c1count) dma start (c1locadr & c1count) req# gnt# irdy# frame#, c/be#, ad (addr) pci bus local bus section 7 dma operation dma channels 0 and 1 iop 480 data book r2.0 7-2 ? 2000 plx technology, inc. all rights reserved. figure 7-2. dma, local-to-pci bus note: the figure represents a sequence of bus cycles. note: in table 7-1, x = don?t care, 0 = disable and 1 = enable. 7.1.3 block dma mode to perform block dma mode, set (c0mode[9]=0) for dma channel 0 and/or (c1mode[9])=0 for dma channel 1. the host processor or the local processor sets the local and pci starting addresses, transfer byte count, and transfer direction. the host or local processor then sets the start bit to initiate a transfer. the iop 480 arbitrates for the pci and local buses and transfers data. once the transfer completes, the iop 480 sets the channel done bit(s) (c0csr[4]=1 and/or c1csr[4]=1) and, if enabled, asserts an interrupt(s) (c0mode[10] and/or c1mode[10]) to the local processor or the pci host (programmable). the channel done bit(s) can be polled to indicate the dma transfer status. dma registers are accessible from the pci and local buses (refer to figure 7-3). during a dma transfer(s), the iop 480 is a master on both the pci and local buses. the iop 480 releases the pci bus if one of the following conditions occurs: fifo is full (pci-to-local) fifo is empty (local-to-pci) terminal count is reached pci bus latency timer expires (pciltr[7:0]) ? normally programmed by the host pci bios ? and pci gnt# de-asserts pci host asserts stop# direct master request is pending the iop 480 releases the local bus if one of the following occurs: fifo is empty (pci-to-local) fifo is full (local-to-pci) terminal count is reached local bus latency timer is enabled and expires (loctmr[7:0]) boff# is asserted direct slave request is pending table 7-1. dma local burst mode burst enable bit bterm# enable bit result 0 x single cycle 1 0 burst up to four data cycles 11 burst forever (terminate when bterm# is asserted or transfer complete) iop 480 lad, ads#, lwr# devsel#, trdy# pci bus local bus lhold lholda lad, ready# dma start (c1locadr & c1count) dma start (c1locadr & c1count) req# gnt# irdy# ad (addr & data) slave master master slave section 7 dma channels 0 and 1 dma operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 7-3 section 7 ? dma operation figure 7-3. block dma mode initialization (single address or pci dual address cycle) 7.1.4 scatter/gather dma mode in scatter/gather dma mode, the host processor or local processor sets up descriptor blocks in local or host memory composed of pci and local addresses, transfer count, transfer direction, and address of next descriptor block (refer to figure 7-6 on page 7-5). the host or local processor then: enables the scatter/gather mode bit(s) (c0mode[9]=1 and/or c1mode[9]=1) sets up the address of the initial descriptor block in the iop 480 descriptor pointer register(s) (c0descptr and/or c1descptr) initiates the transfer by setting a start bit(s) (c0csr[1:0] and/or c1csr[1:0]) the iop 480 loads the first descriptor block and initiates the data transfer. the iop 480 continues to load descriptor blocks and transfer data until it detects the end of chain bit(s) (c0descptr[1] and/or c1descptr[1]) are set. (these bits are part of each descriptor.) when the end of chain bit(s) is detected, the iop 480 completes the current descriptor block and sets the dma done bit(s) (c0csr[4] and/or c1csr[4]). if the done interrupt enable bit is set (c0mode[10]/c1mode[10]) to 1, the iop 480 asserts a pci interrupt (inta#) and/or local interrupt (into) at the end of the scatter/gather and interrupt enabled. the iop 480 can also be programmed to assert pci or local interrupts after each descriptor block transfer is complete. the dma controller can be programmed to clear the transfer size at completion of each dma, using the dma clear count mode bit(s) (c0mode[16] and/or c1mode[16]). notes: in scatter/gather dma mode, the descriptor includes the pci and local address space, transfer size, and next descriptor pointer. the descriptor pointer register(s) (c0descptr and/or c1descptr) contains end of chain (bit 1), direction of transfer (bit 3), next descriptor address (bits [31:4]), interrupt after terminal count (bit 2), and descriptor location (bit 0) bits. the local bus width must be the same as local memory bus width. a dma descriptor can be in either local or pci memory (for example, first descriptor in local memory, and second descriptor in pci memory). pci host memory memory block to transfer memory block to transfer local memory mode register descriptor pointer register (set direction only) control/status register set dma mode to block set up transfer parameters set enable and go bits in dma control/status registers to initiate dma transfer transfer size (byte count) register dual address ? pci addresses register single address ? pci address register local address register section 7 dma operation dma channels 0 and 1 iop 480 data book r2.0 7-4 ? 2000 plx technology, inc. all rights reserved. figure 7-4. scatter/gather dma mode initialization (single address cycle) figure 7-5. scatter/gather dma mode initialization (pci dual address cycle) set up first descriptor pointer register (only requires descriptor pointer) first memory block to transfer first memory block to transfer next memory block to transfer next memory block to transfer initialize dma descriptors in either host or local memory pci memory local memory mode register set dma mode to scatter/gather sac control/status register set enable and go bits in dma control/status register to initiate dma transfer first transfer size (byte count) and valid bit descriptor pointer register end of chain specification bit 1 2 3 4 first pci address first local address next descriptor pointer pci address local address transfer size (byte count) and valid bit next descriptor pointer pci address high transfer size (byte count) and valid bit set up first descriptor pointer register (only requires descriptor pointer) first memory block to transfer first memory block to transfer next memory block to transfer next memory block to transfer initialize dma descriptors in either host or local memory pci memory local memory mode register set dma mode to scatter/gather dac control/status register set enable and go bits in dma control/status register to initiate dma transfer first transfer size (byte count) and valid bit descriptor pointer register end of chain specification bit 1 2 3 4 first pci address first local address next descriptor pointer pci address high pci address low local address next descriptor pointer section 7 dma channels 0 and 1 dma operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 7-5 section 7 ? dma operation figure 7-6. scatter/gather dma mode from pci-to-local bus (arbitration from local bus) figure 7-7. scatter/gather dma mode from local-to-pci bus (arbitration from pci bus) note: the figures represent a sequence of bus cycles. read and write cycles continue... set up scatter/gather dma for pci-to-local iop 480 initiates read from pci bus iop 480 initiates read from pci bus iop 480 initiates read from pci bus iop 480 initiates read from pci bus iop 480 retrieves scatter/gather data from local memory iop 480 retrieves scatter/gather data from local memory iop 480 writes data to local bus iop 480 writes data to local bus iop 480 writes data to local bus iop 480 writes data to local bus pci bus local bus iop 480 read and write cycles continue... set up scatter/gather dma for local-to-pci iop 480 initiates read from local bus iop 480 initiates read from local bus iop 480 initiates read from local bus iop 480 initiates read from local bus iop 480 retrieves scatter/gather data from pci memory iop 480 retrieves scatter/gather data from pci memory iop 480 writes data to pci bus iop 480 writes data to pci bus iop 480 writes data to pci bus iop 480 writes data to pci bus pci bus local bus iop 480 section 7 dma operation dma channels 0 and 1 iop 480 data book r2.0 7-6 ? 2000 plx technology, inc. all rights reserved. 7.1.5 local-to-pci transfer figure 7-8. local-to-pci bus dma data transfer operation 7.1.6 pci-to-local transfer figure 7-9. pci-to-local bus dma data transfer operation 7.1.7 demand mode a bit in the dma configuration register specifies that the channel operates in demand mode. in demand mode, the user sets up the configuration registers of the dma controller and initiates a transfer. the dma controller transfers data when the dreq[1:0]# input of the dma channel is asserted. the dma controller then asserts dack[1:0]# to indicate that the current local bus transfer is in response to the dreq[1:0]# input. the dma controller continues to transfer data until it reaches the transfer count or until dreq[1:0]# is de- asserted. the minimum transfer size per dreq[1:0]# input is one lword (32 bits). this may result in multiple transfers for an 8- or 16-bit bus. the dreq [1:0]# input can be thought of as a dma pause button. local bus arbitration: pci bus arbitration: releases control of pci bus whenever fifo becomes empty, pci bus latency timer expires and pci gnt# de-asserts, pci disconnect is received, or direct local-to-pci bus request is pending. rearbitrates for control of pci bus when preprogrammed number of entries in fifo becomes available, or after two pci clocks if disconnect is received. pci bus arbitration local bus arbitration fifo unload fifo with pci bus write cycles load fifo with local bus read cycles gnt# req# lholda lhold local interrupt generation (programmable) done pci interrupt generation (programmable) done releases control of local bus whenever fifo becomes full, terminal count is reached, local bus latency timer is enabled and expires, lholdreq is asserted, or direct pci-to-local bus request is pending. rearbitrates for control of local bus when preprogrammed number of empty entries in fifo becomes available. if local bus waits until local bus pause timer expires. latency timer is enabled and expires, local bus arbitration: pci bus arbitration: releases control of pci bus whenever fifo becomes full, terminal count is reached, pci latency timer expires and pci gnt# de-asserts, pci disconnect is received, or direct local-to-pci bus request is pending. rearbitrates for control of pci bus when preprogrammed number of empty entries in fifo becomes available, or after two pci clocks if disconnect is received. pci bus arbitration local bus arbitration fifo load fifo with pci bus read cycles unload fifo with local bus write cycles local interrupt generation (programmable) done pci interrupt generation (programmable) done gnt# req# lholda lhold releases control of local bus whenever fifo becomes empty, local bus latency timer is enabled and expires, lholdreq is asserted, or direct pci-to-local bus request is pending. rearbitrates for control of local bus when preprogrammed number of entries becomes available in fifo or pci terminal count is reached. if local bus waits until local bus pause timer expires. latency timer is enabled and expires, section 7 dma channels 0 and 1 dma operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 7-7 section 7 ? dma operation 7.1.8 demand mode/fast terminate the dma fast/slow terminate mode select bit(s) (c0mode[15] and/or c1mode[15]) determines whether blast# is asserted after the dma controller dreq[1:0]# input is de-asserted. if blast# output is not required for the last lword of a dma transfer (bit [15]=1), the dma controller releases the data bus after it receives an external ready# or the internal wait state counter decrements to 0 for the current lword. if the dma controller is currently bursting data, which is not the last data phase for the burst, blast# is not asserted. if blast# output is required for the last lword of the dma transfer (bit [15]=0), the dma controller transfers one or two lwords. if dreq[1:0]# is de-asserted during the address phase of the first transfer in the iop 480 local bus ownership, the dma controller completes the current lword, and one additional lword (this allows blast# output to be asserted during the final lword). if the dma fifo is full/empty after the data phase in which dreq[1:0]# is de-asserted, the second lword is not transferred. dreq[1:0]# controls only the number of lword transfers. for an 8-bit bus, the iop 480 releases the bus after transferring the last byte of the lword. for a 16-bit bus, the iop 480 releases the bus after transferring the last word of the lword. 7.1.9 local bus eot the dma controller terminates a transfer on an lword boundary after eot# is asserted. for an 8-bit bus, the iop 480 terminates after transferring the last byte of the lword. for a 16-bit bus, the iop 480 terminates after transferring the last word of the lword. for scatter/gather dma (channels 0 and 1), a bit exists for continuing the dma transfer of next links after eot# is asserted (c0mode[20] and/or c1mode[20]). if this bit is set to 1, next links are transferred after eot# is asserted. if this bit is set to 0, eot# stops all links of dma. during the descriptor loading from the local bus, assertion of eot# causes a complete descriptor load and no subsequent data transfer; however, this is not recommended. this has no effect when the descriptor is loaded from the pci bus. the dma fast/slow terminate mode select bit(s) (c0mode[15] and/or c1mode[15]) determines whether blast# is asserted after a dma controller detects eot# input. if blast# output is not required for the last lword of the dma transfer (c0mode[15]=1 and/or c1mode[14]=1, the dma controller releases the data bus and terminates dma after it receives an external ready#. when used, the internal wait state counter decrements to 0 for the current lword. if the dma controller is currently bursting data that is not the last data phase for the burst, blast# output is not asserted. if blast# output is required for last lword of the dma transfer (c0mode[15]=1 and/or c0mode[15]=1), the dma controller transfers one or two lwords. if eot# is asserted, the dma controller completes the current lword and one additional lword if blast# is not already being asserted (this allows blast# output to be asserted during the final lword). eot# can be used to end all transfers on the current channel or to simply skip to the next link in a chain (c0mode[20] and/or c1mode[20]). when eot# is used to end a scatter/gather dma cycle, the number of bytes remaining to be transferred can automatically be written to the descriptor transfer count field by enabling the dma clear count mode bit(s) (c0mode[16]=1 and/or c1mode[16]=1). 7.1.10 dma abort dma transfers can be aborted, in addition to using the eot# signal, by performing the following sequence: 1. set the channel enable bit(s) (c0csr[0]=1 and/or c1csr[0]=1). 2. set the channel start bit(s) (c0csr[1]=1 and/or c1csr[1]=1). 3. clear the dma channel enable bit(s) (c0csr[0]=0 and/or c1csr[0]=0). 4. abort dma by setting the channel abort bit(s) (c0csr[2]=1 and/or c1csr[2]=1). 5. wait until the channel done bit(s) is set (c0csr[4]=1 and/or c1csr[4]=1). note: one to two data transfers occur after the abort bit is set. aborting when no dma cycles are in progress causes the next dma to abort. section 7 dma operation dma channels 0 and 1 iop 480 data book r2.0 7-8 ? 2000 plx technology, inc. all rights reserved. 7.1.11 local bus latency and pause timers the local bus latency and pause timers are programmable using the local bus timers register (loctmr[7:0] and/or loctmr[23:16], respectively). if the local bus latency timer is enabled and expires (loctmr[7:0]=0h), the iop 480 completes the current lword transfer and releases lhold. after the programmable pause timer expires (loctmr[23:16]=0h), it re-asserts lhold. it continues to transfer when it receives lholda. the pci bus transfer continues until the fifo is empty for a local-to-pci transfer or full for a pci-to-local transfer. 7.1.12 dma unaligned transfers as a local bus master, the iop 480 supports unaligned transfers. for a 32-bit bus, if a dma transfer does not start at an address with lad[3:2] = 00, then a single lword transfer is first performed, followed by lword bursts. for a 16-bit bus, if the dma transfer does not start at an address with lad[2:1] = 00, then a byte transfer is first performed, followed by word bursts. for an 8-bit bus, a dma transfer may start bursting at any address. for unaligned local-to-pci transfers, the iop 480 reads a partial lword from the local bus. it continues to read lwords from the local bus. lwords are assembled, aligned to the pci bus address, and loaded into the fifo. for pci-to-local transfers, lwords are read from the pci bus and loaded into the fifo. on the local bus, lwords are assembled from the fifo, aligned to the local bus address and written to the local bus. on both the pci and local buses, the byte enables for writes determine lad[1:0] for the start of a transfer. for the last transfer, byte enables specify the bytes to be written. all reads are lwords. 7.1.13 pci memory write and invalidate (mwi) the iop 480 can be programmed to perform memory write and invalidate cycles (mwi) to the pci bus for dma transfers, as well as direct master transfers. the iop 480 supports memory write and invalidate transfers for cache line sizes of 8 or 16 lwords. size is specified in the system cache line size bits (pciclsr[7:0]). if a size other than 8 or 16 is specified, the iop 480 performs write transfers rather than memory write and invalidate transfers. dma memory write and invalidate transfers are enabled when the dma controller memory write and invalidate enable bit(s) (c0mode[13] and/or c1mode[13]) and the pci memory write and invalidate enable bit (pcicr[4]) are set. in memory write and invalidate mode, the iop 480 waits until the number of lwords required for specified cache line size are read from the local bus before starting the pci access. this ensures a full cache line write can complete in one pci bus ownership. if a target disconnects before a cache line completes, the iop 480 completes the remainder of that cache line, using normal writes, before resuming memory write and invalidate transfers. if a memory write and invalidate cycle is in progress, the iop 480 continues to burst into the next cache line if the data is in the fifos. otherwise, the iop 480 terminates the burst and waits for the next cache line to be read from the local bus. if the final transfer is not a full cache line, the iop 480 completes the dma transfer using normal writes. 7.1.14 dma descriptor ring management (valid mode) in scatter/gather dma mode, when the valid mode enable bit (c0mode[18] and/or c1mode[18]) is set to 0, the valid bit (bit 31 of transfer count) is ignored. when the valid mode enable bit (c0mode[18] and/or c1mode[18]) is set to 1, the dma descriptor proceeds only when the valid bit is set. if the valid bit is set, the transfer count is 0, and the descriptor is not the last descriptor, then the dma controller moves on to the next descriptor in the chain. section 7 dma channels 0 and 1 dma operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 7-9 section 7 ? dma operation when the valid stop control bit (c0mode[19] and/or c1mode[19]) is set to 0, the dma scatter/gather controller continuously polls the descriptor with the valid bit set to 0 (invalid descriptor) until the valid bit is read to be a 1. when the valid stop control bit (c0mode[19] and/or c1mode[19]) is set to 1, the dma scatter/gather controller pauses if a valid bit with a value of 0 is detected. in this case, the iop 480 cpu must restart the dma controller by setting bit 1 of the dma control/status register (c0csr[1] and/or c1csr[1]). when the dma clear count mode bit(s) is set (c0mode[16]=1 and/or c1mode[16]=1), the valid bit is cleared at the completion of each descriptor. 7.1.15 dma priority the dma channel priority bits (larbr[5:4]) can be used to specify the following priorities: rotating (larbr[5:4]=00) dma channel 0 (larbr[5:4]=01) dma channel 1 (larbr[5:4]=10) 7.1.16 local bus arbitration the iop 480 dma controller releases control of the local bus (de-asserts lhold) when one of the following conditions occurs: local bus latency timer is enabled and expires (loctmr[7:0]) lholdreq is asserted (lholdreq can be enabled or disabled, or gated with a local bus latency timer before the iop 480 releases the local bus) direct slave access is pending (only in direct slave high-priority mode) eot# input is received (if enabled) 7.1.17 pci bus arbitration the dma controller releases control of the pci bus when one of the following conditions occurs: fifos are full or empty pci bus latency timer expires (pciltr[7:0]) ? and the iop 480 loses the pci gnt# signal target disconnect response is received the dma controller de-asserts its pci bus request (req#) for a minimum of two pci clocks. 7.1.18 dma local bus arbitration 7.1.18.1 local latency and pause timers the local bus latency and pause timers are programmable using the local bus timers register (loctmr[7:0] and/or loctmr[23:16], respectively). the dma controller completes the current lword transfer and releases the bus if the local latency timer expires. after its programmable pause timer expires, it re-requests the local bus. when it is granted the local bus, it continues with the transfer. 7.1.18.2 dram refresh timers the iop 480 has built-in programmable memory refresh timers. if the refresh timers expire (dramctl[22:12]), the dma controller completes the current lword transfer and releases the bus. after its programmable pause timer expires, it re-requests the local bus. when it is granted the local bus, it continues with the transfer. 7.1.18.3 local arbiter priority if direct slave accesses are programmed to have a higher priority than dma accesses (larbr[3:1]), the direct slave access preempts dma. when a direct slave access occurs, the dma controller releases the local bus within two word transfers. after its programmable pause timer expires, it again requests the local bus. when it is granted the local bus, it continues with the transfer. 7.1.19 dma master command codes the iop 480 dma controllers can assert the following memory cycles. table 7-2. dma master command codes command type code (c/be[3:0]#) memory read 0110 (6h) memory write 0111 (7h) memory read multiple 1100 (ch) dual address cycle 1101 (dh) memory read line 1110 (eh) memory write and invalidate 1111 (fh) section 7 dma operation dma channel 2 iop 480 data book r2.0 7-10 ? 2000 plx technology, inc. all rights reserved. 7.2 dma channel 2 7.2.1 overview the iop 480 dma channel 2 controller supports transferring data between two local bus memory regions or flyby data transfers between local memory and a local i/o device. it supports an end of transfer pin (eot2#) and demand mode dma transfers. master mode must be enabled with the master enable bit (pcicr[2]=1) before the iop 480 can become a pci bus master. dma channel 2 has a programmable 4-lword bidirectional fifo. additionally, dma channel 2 can be programmed to: operate in 8-, 16-, or 32-bit local bus widths use from 0 to 15 internal wait states (local bus) enable/disable internal wait states (local bus) enable/disable local bus burst capability local bus burst to four limit hold local address constant (local target is fifo) or increment pause local transfer with/without blast# (dma fast/slow termination) assert pci interrupt (inta#) or local interrupt (into) when dma transfer is complete the local latency timer determines the number of local clocks the iop 480 can own the bus before relinquishing the local bus. the local pause timer sets how soon dma channel 2 can request the local bus. the local pause timer starts after lholda is de-asserted. 7.2.2 dma register access 7.2.2.1 access from the local bus the internal iop 480 cpu or a local processor can access the iop 480 dma registers through the base address specified in the local base address for configuration register access register (cfgba). 7.2.2.2 access from the primary pci bus a pci master can access the dma registers through the address specified in the pci base address for memory accesses to configuration registers and local space 0 register (pcibar0). 7.2.3 local-to-local mode dma the initiator designates the local source address, local destination address, and transfer count. the initiator then sets a control bit to initiate the transfer. once the transfer completes, the iop 480 can generate an interrupt (programmable). the transfer terminates when one of the following occurs: number of bytes specified in the transfer count register have been transferred eot2# input is asserted dma is aborted the source and destination memory regions are independent. the bus width, type, and performance characteristics of the bus regions can be different. (refer to figure 7-10.) section 7 dma channel 2 dma operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 7-11 section 7 ? dma operation 7.2.4 demand mode the source and destination demand mode bits (c2mode[12:11]) can be used to specify that the channel operates in demand mode. in demand mode, the user sets up the dma controller ? s configuration registers and initiates a transfer. data is transferred when the dma channels dreq2# input is asserted. the iop 480 asserts dack2# to indicate that the current local bus transfer is in response to the dreq2# input. the minimum transfer size per dreq2# input is one lword (32 bits). this may result in multiple transfers for an 8- or 16-bit bus. note: the above transfer information is correct, unless the transfer size is less than one lword. when set to 1, the source demand mode bit (c2mode[12]) causes the dma controller to operate in demand mode while reading source data. in demand mode, the dma controller transfers data when its dreq2# input is asserted. the iop 480 asserts dack2# to indicate the current local bus transfer is in response to the dreq2# input. the dma controller transfers lwords (32 bits) of data. this may result in multiple transfers for an 8- or 16-bit bus. when set to 1, the destination demand mode bit (c2mode[11]) causes the dma controller to operate in demand mode while writing destination data. in demand mode, the dma controller transfers data when its dreq2# input is asserted. the iop 480 asserts dack2# to indicate the current local bus transfer is in response to the dreq2# input. the dma controller transfers lwords (32 bits) of data. this may result in multiple transfers for an 8- or 16-bit bus. figure 7-10. local-to-local dma initialization local source memory memory block to transfer memory block to receive local destination memory mode register (c2mode) control/status register (c2csr) set dma mode to block set up transfer parameters set enable and go bits in dma control/status registers to initiate dma transfer transfer size (byte count) register (c2count) local source register (c2srcadr) local destination address register (c2destadr) section 7 dma operation dma channel 2 iop 480 data book r2.0 7-12 ? 2000 plx technology, inc. all rights reserved. 7.2.5 fast terminate mode c2mode[15] can be used to specify fast/slow terminate mode. when set to 0 and eot# is asserted, or dreq2# or blast# is de-asserted, the dma controller completes the current lword transfer and then asserts blast# and completes the next lword transfer. if blast# is asserted when eot# or dreq# are asserted, then the dma controller transfers only one lword. when set to 1, the dma controller stops transferring data after the current lword, even if a new blast# is asserted. (refer to table 7-3.) 7.2.6 dma abort dma transfers can be aborted, in addition to using the eot# signal, by performing the following sequence: 1. set the channel enable bit (c2csr[0]=1). 2. set the channel start bit (c2csr[1]=1). 3. clear the dma channel enable bit (c2csr[0]=0). 4. abort dma by setting the channel abort bit (c2csr[2]=1). 5. wait until the channel done bit is set (c2csr[4]=1). note: one to two data transfers occur after the abort bit is set. aborting when no dma cycles are in progress causes the next dma to abort. 7.2.7 flyby dma the iop 480 flyby mode is the most efficient dma mode because it combines read/write into a single bus access. setting the flyby mode bit (c2mode[10]=1) specifies the transfer direction and the transfer count. in flyby mode, the transfer direction designates whether the destination address is read or the destination address is written (c2mode[9]). set the start and enable bits (c2csr[1:0]=1, respectively) to initiate the transfer. the transfer starts when a local i/o device asserts the dreq2# input (c2mode[11]=1). alternatively, flyby mode can also work without being in demand mode, in which case transfers start immediately (c2csr[1:0]) without requiring dreq2# input (c2mode[11]=0). the iop 480 asserts ads#, ale, and dack2#, and drives the memory address onto the local bus for one clock cycle. the dma controller then floats lad[31:0]. dack2# indicates that the flyby dma is in progress. a turnaround cycle must be provided by the source before data may be driven onto the local address/ data bus. dack2#, being asserted along with the ready# output, indicates to the i/o device that read data is available or write data has been accepted. once the transfer completes, the iop 480 can generate an interrupt (programmable). the transfer terminates when the number of bytes specified in the transfer count register have been transferred or the eot2 input is asserted, or the dma is aborted. the data continues to be transferred when the dreq2# input is asserted. the minimum transfer size per dreq2# input is one lword (32 bits). this may result in multiple transfers for an 8- or 16-bit bus. for flyby data transfers, the source and destination bus widths must be the same. for best performance, the bterm and burst mode bits should be enabled for the destination bus region address. table 7-3. stop transfer modes register (c2mode[15]) blast# signal number of lwords transferred 012 001 1x1 section 7 dma channel 2 dma operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 7-13 section 7 ? dma operation 7.2.8 local bus arbitration the iop 480 dma controller releases control of the local bus (de-asserts lhold) when one of the following conditions occurs: local bus latency timer is enabled and expires (loctmr[7:0]) lholdreq is asserted (lholdreq can be enabled or disabled, or gated with a local bus latency timer before the iop 480 releases the local bus) direct slave access is pending (only in direct slave high-priority mode) eot# input is received (if enabled) 7.2.9 dma unaligned transfers as a local bus master, the iop 480 supports unaligned transfers. for a 32-bit bus, if a dma transfer does not start at an address with lad[3:2] = 00, then single lword transfers are first performed, followed by lword bursts. for a 16-bit bus, if the dma transfer does not start at an address with lad[2:1] = 00, then single word transfers are first performed, followed by word bursts. for an 8-bit bus, a dma transfer may start bursting at any address. on the local bus, the byte enables for writes determine lad[1:0] for the start of a transfer. for the last transfer, byte enables specify the bytes to be written. all reads are lwords. 7.2.10 dma local bus arbitration 7.2.10.1 local bus latency and pause timers the local bus latency and pause timers are programmable using the local bus timers register (loctmr[7:0] and/or loctmr[23:16], respectively). if the local bus latency timer is enabled and expires (loctmr[7:0]), the iop 480 completes the current lword transfer and releases lhold. after its programmable pause timer expires (loctmr[23:16]), it re-asserts lhold. it continues to transfer when it receives lholda. 7.2.10.2 dram refresh timers the iop 480 has built-in programmable memory refresh timers. if the refresh timers expire (dramctl[22:12]), the dma controller completes the current word transfer and releases the bus. after its programmable pause timer expires, it re-requests the local bus. when it is granted the local bus, it continues with the transfer. 7.2.10.3 local arbiter priority if direct slave accesses are programmed to have a higher priority than dma accesses (larbr[3:1]), a direct slave access preempts dma. when a direct slave access occurs, the dma controller gives up the local bus within two word transfers. after its programmable pause timer expires, the dma controller again requests the local bus. when it is granted the local bus, it continues the transfer. section 7 dma operation timing diagrams iop 480 data book r2.0 7-14 ? 2000 plx technology, inc. all rights reserved. 7.3 timing diagrams timing diagram 7-1. dma from pci-to-local, bterm disabled a d e 0 d a d d a d d a d d a d d 0 0ns 500ns 1000ns 1500ns pclk req# gnt# ad[31:0] c/be[3:0]# frame# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ads# lwr# ready# blast# section 7 timing diagrams dma operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 7-15 section 7 ? dma operation timing diagram 7-2. dma from pci-to-local, bterm enabled a d e 0 d a d 0 d 0ns 500ns 1000ns 1500ns pclk req# gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ads# lwr# ready# blast# section 7 dma operation timing diagrams iop 480 data book r2.0 7-16 ? 2000 plx technology, inc. all rights reserved. timing diagram 7-3. dma demand mode, write from pci-to-local a d d e 0 0 a d 0ns 250ns 500ns pclk req# gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ads# lwr# ready# blast# dreq0# dack0# section 7 timing diagrams dma operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 7-17 section 7 ? dma operation timing diagram 7-4. dma demand mode, write four lwords from pci-to-local a d3 d0 e 0 0 a d0 d1 d2 d1 d2 d3 0ns 250ns 500ns 750ns pclk req# gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ads# lwr# ready# blast# dreq0# dack0# section 7 dma operation timing diagrams iop 480 data book r2.0 7-18 ? 2000 plx technology, inc. all rights reserved. timing diagram 7-5. dma scatter/gather with descriptor on local memory a d d 0 0 a d0 d7 a d0 d 0 7 1 2 3 4 5 6 1 2 3 4 5 6 0ns 250ns 500ns 750ns 1000ns pclk req# gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ads# lwr# ready# blast# section 7 timing diagrams dma operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 7-19 section 7 ? dma operation timing diagram 7-6. dma scatter/gather with descriptor on pci memory a d d 6 0 a d0 d7 7 0 0 a d0 d7 1 2 3 4 5 6 1 2 3 4 5 6 0ns 250ns 500ns 750ns 1000ns 12 5 pclk req# gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ads# lwr# ready# blast# section 7 dma operation timing diagrams iop 480 data book r2.0 7-20 ? 2000 plx technology, inc. all rights reserved. timing diagram 7-7. dma2 demand mode cycle 5a5a5a5a 5 fffffffff ffffffff 05e4 ffffffff 0005 05c4 05c5 05c6 05c7 f 0 0ns 100ns 200ns 300ns pclk gnt0#/req# req0#/gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# devsel# stop# lock# lclk ads# ale lad[31:0] ma[12:0] lbe[3:0]# blast# ready# bterm# lwr# rd# lholdack0/ldreq lholdack1/breq lholdreq0/lholdack lholdreq1 llock# dack[2:1]# dreq[2:1]# section 7 timing diagrams dma operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 7-21 section 7 ? dma operation timing diagram 7-8. dma2 non-flyby 5a5a5a5a 5 d0 d1 d2 d3 addr1 d0 d1 d2 d3 ffffffff addr2 43424140 53525150 63626160 73727170 0005 05c4 05c5 05c6 05c7 05c8 0005 05e4 05e5 05e6 05e7 05e4 0 0ns 250ns pclk gnt0#/req# req0#/gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# devsel# stop# lock# lclk ads# ale lad[31:0] ma[12:0] lbe[3:0]# blast# ready# bterm# lwr# rd# lholdack0/ldreq lholdack1/breq lholdreq0/lholdack lholdreq1 llock# section 7 dma operation timing diagrams iop 480 data book r2.0 7-22 ? 2000 plx technology, inc. all rights reserved. timing diagram 7-9. dma2 unaligned transfer 000000003 ffffffff 5a5a5a5a 0 f 5 ffffffff 00001703 07060504 0b0a0908 0f0e0d0c 05e6 0005 05c1 05c2 05c3 f e 7 0 0ns 50ns 100ns 150ns pclk gnt0#/req# req0#/gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# devsel# stop# lock# lclk ads# ale lad[31:0] ma[12:0] lbe[3:0]# blast# ready# bterm# lwr# rd# lholdack0/ldreq lholdack1/breq lholdreq0/lholdack lholdreq1 llock# section 7 timing diagrams dma operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 7-23 section 7 ? dma operation timing diagram 7-10. dma2 local-to-local, 8 lwords, 32-bit ram transfer 0 a d4 d5 d6 d7 d7 d6 d5 d4 a d3 d2 d1 a d0 d1 d2 d3 a d0 a d 7 0 aa1 ab1 aa2 ab2 0ns 250ns 500ns 750ns 1000ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ads# ale lwr# blast# ready# section 7 dma operation timing diagrams iop 480 data book r2.0 7-24 ? 2000 plx technology, inc. all rights reserved. timing diagram 7-11. flyby dma2 load data to 32-bit local fifo a d0 d d d a d d d d a d d 0 a d 0 0ns 250ns 500ns 750ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ads# ale lwr# blast# ready# dack12# section 7 timing diagrams dma operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 7-25 section 7 ? dma operation timing diagram 7-12. flyby dma2 continue ? write data to 32-bit local ram a d0 d d d a d d d d a d d9 0 a d 0 0ns 250ns 500ns 750ns pclk frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ads# ale lwr# blast# ready# dack12# section 7 dma operation timing diagrams iop 480 data book r2.0 7-26 ? 2000 plx technology, inc. all rights reserved. timing diagram 7-13. dma write from local-to-pci, local interrupt done bit a d0 d5 0 a d0 d5 7 0 d1 d2 d3 d4 d1 d2 d3 d4 0ns 250ns 500ns pclk req# gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# lclk lad[31:0] lbe[3:0]# ads# ale lwr# ready# blast# into section 7 timing diagrams dma operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 7-27 section 7 ? dma operation timing diagram 7-14. dma write from pci-to-local, pci interrupt done bit a d5 d e 0 a d0 d5 0 d0 d1 d2 d3 d4 d1 d2 d3 d4 0ns 250ns 500ns 750ns pclk req# gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# stop# devsel# inta# lclk lad[31:0 lbe[3:0]# ads# ale lwr# ready# blast# iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 8-1 section 8 ? lb internal arbiter 8 local bus internal arbiter 8.1 overview the iop 480 supports an external or internal local bus arbiter. the default is for the internal local bus arbiter to be enabled. if an external bus arbiter is used, then a serial eeprom must be used to configure the iop 480. the iop 480 has an internal bus arbiter for the local bus (larbr[0]). the following sources can request use of the local bus (larbr[5:1]): internal iop 480 cpu direct slave controller internal pci/local dma controllers (ch0) internal pci/local dma controllers (ch1) internal local-to-local dma controller (ch2) lholdreq0/lholdack pin (external master) lholdreq1 pin (external master) 8.2 initialization after reset, the iop 480 performs a serial eeprom check, and then boots the iop 480 cpu. the iop 480 cpu boot uses the local bus; therefore, the local bus must be up and ready after the serial eeprom check. by default, the internal local arbiter is enabled. if the external preempt enable bit is set (larbr[7]=1), the internal local arbiter supports only one external local master, which is master 0 because breq and lholdack1 share the same output pin (lholdack1/breq). 8.3 round-robin mode the seven sources of local bus requests are serviced in a round-robin priority, or one of the requests can be given priority. the selection is made in larbr, a local arbitration register. when round-robin is selected, each requester has equal priority. after a requester has been granted the bus, it is rotated to last priority, and other active requests are rotated towards top priority. (refer to timing diagram 8-1.) 8.4 high-priority mode if a single requester is given priority, then other requesters still participate in round-robin arbitration. the bus is granted alternately between the single high priority requester and the highest priority requester of the round-robin arbiter. (refer to timing diagram 8-2.) the direct slave controller only preempts dma controllers if the arbiter mode is set in direct slave high-priority mode (larbr[3:1]=011b). when dma channels 0 and 1 priority are chosen, (larbr[3:1]=010b), larbr[5:4] can be set to maintain a rotational priority scheme between the following: dma0 and dma1 dma0 has priority dma1 has priority refresh cycle and latency timer expiration (if enabled) automatically preempt the internal iop 480 cpu, direct slave controller, and internal dma (channel 0, 1, and 2) controllers. if the external preempt enable bit is disabled (larbr[7]=0), the refresh cycle and local latency timer cannot preempt external local masters. if the external preempt enable bit is enabled (larbr[7]=1), and there is a refresh cycle or local latency timer expiration, lholdack1/breq output is asserted to request that an external local master release the local bus. when the external preempt enable bit is enabled (larbr[7]=1), only master 0 should be connected to the iop 480 internal local arbiter. section 8 local bus internal arbiter performance tuning iop 480 data book r2.0 8-2 ? 2000 plx technology, inc. all rights reserved. 8.5 performance tuning depending on applications, arbiter modes (round-robin or high-priority), and latency timer value should be appropriately selected to retain a high bandwidth. for example , to favor the dma channel 0 controller, select dma 0/1 high-priority mode (larbr[3:1]= 010b) and set the dma channel priority bits to dma channel 0 priority (larbr[5:4]=01b). the external preempt enable bit (larbr[7]) and lholdack1/breq output is used by an external local master to retain or release the local bus. 8.6 timing diagrams timing diagram 8-1. round-robin priority arbitration (three active requesters) timing diagram 8-2. high-priority arbitration (lholdreq0/lholdack has priority) 0ns 50ns 100ns 150ns 200 n lclk lholdreq0/lholdack lholdack0/ldreq lholdreq1 lholdack1/breq iop 480 cpu req (internal) iop 480 ack (internal) 0ns 50ns 100ns 150ns 200ns 2 5 lclk lholdreq0/lholdack lholdack0/ldreq lholdreq1 lholdack1/breq iop 480 cpu req (internal) iop 480 cpu ack (internal) iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 9-1 section 9 ? pb internal arbiter 9 pci bus internal arbiter 9.1 overview the iop 480 can use an internal or external pci arbiter. the default is an external pci arbiter. (refer to pcictl[16].) the iop 480 has an internal bus arbiter for the pci bus. the following sources can request use of the pci bus: iop 480 internal pci controller three external pci controllers 9.2 initialization by default, the internal pci arbiter is disabled. it can only be enabled from the serial eeprom, the iop 480 cpu, or an external local master. the pci arbiter enable bit (pcictl[16]) should not be written from the pci bus. 9.3 priority mode the internal arbiter provides support for: two operation modes ? priority or round-robin (pcictl[17]) give grant on idle or busy (pcictl[18]) park option ? arbiter parks a grant on the current master or on the iop 480 when the pci bus is idle (pcictl[19]) the internal arbiter can be disabled, enabling the iop 480 to be used with an external arbiter. the selection is made in the pci arbiter enable bit (pcictl[16]). 9.3.1 priority and round-robin modes the four sources of pci bus requests are serviced in round-robin priority, or the iop 480 pci controller can be given priority. the selection is made in the iop 480 high priority bit (pcictl[17]). when round- robin is selected, each requester has equal priority. after a requester is granted the bus, the request is rotated to last priority, and the other active requests are rotated toward top priority. (refer to figure 9-2.) if the iop 480 pci controller is given priority, then the other requesters continue to participate in a lower level round-robin arbitration. the bus is alternately granted between the iop 480 pci controller and the winner of the round-robin arbitration. (refer to figure 9-1.) gnt# is asserted in the pci idle state (frame# and irdy# are both high) or in the busy state. the internal arbiter can park a grant on the current master or on the iop 480 pci controller (pcictl[19]). if the grant_on_idle bit is disabled in the pci bus control register (pcictl[18]=0), the current gnt# is de-asserted when frame# is asserted. when there are multiple requests, and a request is granted the bus, if frame# is not asserted on the next clock after gnt# is asserted, the arbiter passes the grant to the next request. if there is a reset when in internal arbiter mode, the iop 480 pci controller receives the first grant. figure 9-1. priority mode figure 9-2. round-robin mode w 3 2 1 0 iop 480 3 0 2 1 0 section 9 pci bus internal arbiter grant on idle mode iop 480 data book r2.0 9-2 ? 2000 plx technology, inc. all rights reserved. 9.4 grant on idle mode when the early grant release bit is set to one (pcictl[18]=1), the internal pci arbiter gives a grant in the pci idle state. when the bit is set to zero (pcictl[18]=0), a new grant is assigned to a new pci master as a current master asserts frame#. 9.5 park on iop 480 mode when the pci arbiter parking on iop 480 bit is set to one (pcictl[19]=1), the internal pci arbiter parks a grant on the iop 480. when the bit is set to zero (pcictl[19]=0), the internal pci arbiter parks a grant on the current master. 9.6 performance tuning any master that delays asserting frame# on the next clock after receiving a grant has the possibility of losing the grant. to minimize pci bus latency when the iop 480 is a pci bus master, use a combination of grant_on_idle, parkk_on_iop 480, and iop 480 priority (pcictl[19:17] =111b). after asserting a pci request, in the worst case, the iop 480 pci controller waits only one external master pci latency. iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 10-1 section 10 ? reset & init 10 reset and initialization 10.1 overview the iop 480 initialization procedure follows these steps: 1. power-on. 2. reset. 3. serial eeprom. 4. boot the iop 480 cpu. 5. initialize the iop 480 registers. 6. dram initialization. 10.2 power-on the typical order of events for power-on is as follows: 1. power-on. 2. pci and local clocks start. 3. master reset asserts (this can be pci, if in adapter mode, or local, if in host mode). 4. master reset de-asserts. note: it is possible for step 3 can occur prior to step 2. 10.3 reset the iop 480 reset behavior is determined by the hmode pin. when this pin is low , the iop 480 is in adapter mode, and when high , in host mode. the hmode pin cannot be dynamically changed. depending on hmode, various reset sources have a different effect, as illustrated in the following table. table 10-1. adapter and host mode resets mode reset type description adapter (local reset pin becomes an output only; pci reset pin is an input only; inta# is an output only) pci resets all logic software local bus reset only power management resets all logic iop 480 cpu for adapter same as reset pin host (local reset pin is an i/o only; pci reset pin becomes an output only; inta# is an input only) local resets all logic software pci bus reset only iop 480 cpu resets all logic iop 480 cpu power management no effect section 10 reset and initialization reset iop 480 data book r2.0 10-2 ? 2000 plx technology, inc. all rights reserved. 10.3.1 adapter mode 10.3.1.1 pci reset pci rst# input causes all pci bus outputs to float, resets the entire iop 480, and causes the local reset# pin to be asserted. 10.3.1.2 software reset a host on the pci bus can set the pci adapter software reset bit (devinit[30]=1) to reset the iop 480 and assert reset# output. reset# remains asserted for 62 clocks, or until the software reset bit is cleared, whichever occurs last. all local configuration registers are reset; however, the pci configuration registers, dma registers, shared runtime registers, and the local init status bit (devinit[31]) are not reset. when the software reset bit (devinit[30]) is set, the iop 480 responds to pci accesses, but not to local bus accesses. the iop 480 remains in this reset condition until the pci host clears the bit. the serial eeprom is reloaded if the reload configuration registers bit is set (devinit[29]=1). note: the local bus cannot clear this reset bit because the local bus is in a reset state, even if a local processor does not use reset# to reset. 10.3.1.3 power management reset when the power management reset is asserted (transition from d 3 to any other state), the iop 480 resets as if a pci reset was asserted. (refer to section 16, ? power management. ? ) 10.3.1.4 local reset# the local reset# output is driven when one of the following occurs: pci rst# is asserted software reset bit is set iop 480 cpu initiates an external reset power management transitions from state d 3 10.3.1.5 iop 480 cpu chip reset a reset can be executed from the iop 480 cpu processor via software or risc watch. the chip reset causes the entire iop 480 to be reset. when the iop 480 cpu executes a system-reset instruction, or detects reset input, it drives the local reset# pin for at least 62 clocks and then fetches its first instruction from 0xfffffffc. refer to the iop 480 cpu description for more details on asserting chip reset. 10.3.2 host mode 10.3.2.1 pci reset the pci bus rst# output is driven when the local reset# is asserted, the software reset bit is set, or the iop 480 cpu initiates an external reset. 10.3.2.2 local reset# when the local reset# pin is asserted by an external source, the local bus interface circuitry, the configuration registers, and the iop 480 cpu are reset. the iop 480 cpu drives the local reset# pin for 62 clocks after it detects a low input on this pin for two clocks. 10.3.2.3 software reset when the software reset bit is set to one (devinit[30]=1), the following occurs: pci master logic is held reset local bus logic is held reset iop 480 cpu is held reset fifos are reset pci rst# pin is asserted the configuration registers are not reset. a software reset can only be cleared from another host on the local bus, and the iop 480 remains in this reset condition until a local host clears the bit. note: the pci bus cannot clear this reset bit because the pci bus is in a reset state. 10.3.2.4 power management reset power management reset is not applicable for host mode. section 10 serial eeprom reset and initialization iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 10-3 section 10 ? reset & init 10.3.3 iop 480 cpu chip reset a reset can be executed from the iop 480 cpu processor via software or risc watch. the chip reset causes the entire iop 480 to be reset. when the iop 480 cpu executes a system-reset instruction, or detects reset input, it drives the local reset# pin for at least 62 clocks and then fetches its first instruction from 0xfffffffc. refer to the iop 480 cpu description for more details on asserting chip reset. 10.4 serial eeprom after reset, the iop 480 attempts to read the serial eeprom to determine its presence. while the serial eeprom is being checked, and during the serial eeprom load, the following occurs: pci accesses are retried local accesses are held off by not asserting ready# iop 480 cpu is held in reset an active start bit set to 0 indicates a serial eeprom is present. the first lword is then checked to verify whether the serial eeprom is programmed. if the first lword (32 bits) is all ones, a blank serial eeprom is present. the iop 480 reverts to default values. if the first lword is not all ones, then the complete serial eeprom load is performed. if no serial eeprom is present, eedata input should be set to 1. the 3.3v serial eeprom clock (eesk) is derived from the pci clock. the iop 480 asserts the serial eeprom clock by internally dividing the pci clock by 132. the iop 480 uses the fairchild 93cs66len serial eeprom. 10.4.1 iop 480 initialization from the local bus the internal iop 480 cpu processor or a local processor can access all iop 480 internal registers through the base address specified in the local base address for configuration register access register (cfgba). the access must be in a 32-bit-wide bus access. 10.4.2 serial eeprom load the registers listed in table 10-3 are loaded from the serial eeprom after a reset is de-asserted. the serial eeprom is organized in words (16 bits). the iop 480 first loads the most significant word bits (msw[31:16]), starting from the most significant bit ([31]). the iop 480 then loads the least significant word bits (lsw[15:0]), starting again from the most significant bit ([15]). for a description of each register, refer to section 17, ? register summary. ? 10.4.3 selectively accessing the serial eeprom the serial eeprom can be read or written from the pci or local buses. the serial eeprom control register bits (devinit[28:24]) control the iop 480 pins that enable reading or writing of serial eeprom data bits. (refer to manufacturer ? s data sheet for the particular serial eeprom being used.) it is recommended that the fairchild 93cs66len be used. the serial eeprom can also be read or written using the vpd function (refer to section 15.3, ? serial eeprom vpd partitioning, ? on page 15-1). 10.4.4 iop 480 initialization without a serial eeprom or with a blank eeprom if a boot memory device other than a serial eeprom is used to initialize the iop 480, which uses the ma[16:13] as its addresses, then external pull-up resistors are required on the floated address lines during the boot-up process. these external pull-up resistors are required because, upon power-up, the data parity dp[3:0] signals of the ma[16:13]/dp[3:0] pins are disabled and the ma[16:13] signals are floated. the pulled-up ma[16:13]/dp[3:0] signals allow the iop 480 to issue valid addresses for ma[16:13] and fetch instructions from the boot memory device. at boot-up, the iop 480 must enable ma mode for the lcs0 memory region by writing a 0 to the parity checking bit (lcs0brd[12]=0). the cpu instructions to accomplish this must be within address range 0xffff_8000 and ffff_fffc of the boot memory device because ma[16:13] are pulled high. section 10 reset and initialization serial eeprom iop 480 data book r2.0 10-4 ? 2000 plx technology, inc. all rights reserved. a blank eeprom causes the iop 480 to load its default values. the default is to enable the internal local bus arbiter. if an external local bus arbiter is being used in pci host mode, then a jumper is required to allow a blank serial eeprom to be programmed. the jumper is used to put the iop 480 in pci adapter mode (hmode = 0, pulled low). table 10-2. serial eeprom guidelines mode serial eeprom iop 480 register internal local arbiter iop 480 cpu pci host blank default enabled boots none default enabled boots programmed programmed programmed programmed pci adapter blank default enabled held in reset none default enabled boots programmed programmed programmed programmed table 10-3. serial eeprom load registers serial eeprom offset description register bits affected 0h msw of local bus control locctl[31:16] 2h lsw of local bus control locctl[15:0] 4h msw of local bus timeout loctmo[31:16] 6h lsw of local bus timeout loctmo[15:0] 8h msw of local bus timer loctmr[31:16] ah lsw of local bus timer loctmr[15:0] ch msw of local/dma arbitration larbr[31:16] eh lsw of local/dma arbitration larbr[15:0] 10h msw of big/little endian bigend[31:16] 12h lsw of big/little endian bigend[15:0] 14h msw of pci bus control pcictl[31:16] 16h lsw of pci bus control pcictl[15:0] 18h msw of range for pci-to-local address space 0 las0rr[31:16] 1ah lsw of range for pci-to-local address space 0 las0rr[15:0] 1ch msw of local base address (remap) pci-to-local space 0 las0ba[31:16] 1eh lsw of local base address (remap) pci-to-local space 0 las0ba[15:0] 20h msw of range for pci-to-local address space 1 las1rr[31:16] 22h lsw of range for pci-to-local address space 1 las1rr[15:0] 24h msw of local base address (remap) pci-to-local space 1 las1ba[31:16] 26h lsw of local base address (remap) pci-to-local space 1 las1ba[15:0] 28h msw of range for pci-to-local address space 2 las2rr[31:16] 2ah lsw of range for pci-to-local address space 2 las2rr[15:0] 2ch msw of local base address (remap) pci-to-local space 2 las2ba[31:16] 2eh lsw of local base address (remap) pci-to-local space 2 las2ba[15:0] section 10 serial eeprom reset and initialization iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 10-5 section 10 ? reset & init 30h reserved msw of 'h0b8 register 32h reserved lsw of 'h0b8 register 34h reserved msw of 'h0bc register 36h reserved lsw of ? h0bc register 38h msw of range for expansion rom eromrr[31:16] 3ah lsw of range for expansion rom eromrr[15:0] 3ch msw of local base address (remap) pci-to-local erom eromba[31:16] 3eh lsw of local base address (remap) pci-to-local erom eromba[15:0] 40h msw of range for direct master-to-pci dmrr[31:16] 42h lsw of range for direct master-to-pci dmrr[15:0] 44h msw of local base address for direct master-to-pci memory dmlbam[31:16] 46h lsw of local base address for direct master-to-pci memory dmlbam[15:0] 48h msw of pci base address (remap) for direct master-to-pci (lower 32 bits) dmpbam[31:16] 4ah lsw of pci base address (remap) for direct master-to-pci (lower 32 bits) dmpbam[15:0] 4ch msw of direct master dual address cycle upper address dmdac[31:16] 4eh lsw of direct master dual address cycle upper address dmdac[15:0] 50h msw of local base address for direct master-to-pci io/cfg dmlbai[31:16] 52h lsw of local base address for direct master-to-pci io/cfg dmlbai[15:0] 54h msw of pci configuration address for direct master-to-pci io/cfg dmcfga[31:16] 56h lsw of pci configuration address for direct master-to-pci io/cfg dmcfga[15:0] 58h msw of configuration base address cfgba[31:16] 5ah lsw of configuration base address cfgba[15:0] 5ch msw of uart base address uartba[31:16] 5eh lsw of uart base address uartba[15:0] 60h msw of lcs0 bus region descriptor lcs0brd[31:16] 62h lsw of lcs0 bus region descriptor lcs0brd[15:0] 64h msw of lcs0 write timing register lcs0wt[31:16] 66h lsw of lcs0 write timing register lcs0wt[15:0] 68h msw of lcs0 read timing register lcs0rt[31:16] 6ah lsw of lcs0 read timing register lcs0rt[15:0] 6ch msw of lcs0 base address lcs0base[31:16] 6eh lsw of lcs0 base address lcs0base[15:0] 70h msw of lcs0 range lcs0range[31:16] 72h lsw of lcs0 range lcs0range[15:0] 74h msw of lcs1 bus region descriptor lcs1brd[31:16] 76h lsw of lcs1 bus region descriptor lcs1brd[15:0] 78h msw of lcs1 write timing register lcs1wt[31:16] table 10-3. serial eeprom load registers (continued) serial eeprom offset description register bits affected section 10 reset and initialization serial eeprom iop 480 data book r2.0 10-6 ? 2000 plx technology, inc. all rights reserved. 7ah lsw of lcs1 write timing register lcs1wt[15:0] 7ch msw of lcs1 read timing register lcs1rt[31:16] 7eh lsw of lcs1 read timing register lcs1rt[15:0] 80h msw of lcs1 base address lcs1base[31:16] 82h lsw of lcs1 base address lcs1base[15:0] 84h msw of lcs1 range lcs1range[31:16] 86h lsw of lcs1 range lcs1range[15:0] 88h msw of lcs2 bus region descriptor lcs2brd[31:16] 8ah lsw of lcs2 bus region descriptor lcs2brd[15:0] 8ch msw of lcs2 write timing register lcs2wt[31:16] 8eh lsw of lcs2 write timing register lcs2wt[15:0] 90h msw of lcs2 read timing register lcs2rt[31:16] 92h lsw of lcs2 read timing register lcs2rt[15:0] 94h msw of lcs2 base address lcs2base[31:16] 96h lsw of lcs2 base address lcs2base[15:0] 98h msw of lcs2 range lcs2range[31:16] 9ah lsw of lcs2 range lcs2range[15:0] 9ch msw of lcs3 bus region descriptor lcs3brd[31:16] 9eh lsw of lcs3 bus region descriptor lcs3brd[15:0] a0h msw of lcs3 write timing register lcs3wt[31:16] a2h lsw of lcs3 write timing register lcs3wt[15:0] a4h msw of lcs3 read timing register lcs3rt[31:16] a6h lsw of lcs3 read timing register lcs3rt[15:0] a8h msw of lcs3 base address lcs3base[31:16] aah lsw of lcs3 base address lcs3base[15:0] ach msw of lcs3 range lcs3range[31:16] aeh lsw of lcs3 range lcs3range[15:0] b0h msw of dram bus region descriptor drambrd[31:16] b2h lsw of dram bus region descriptor drambrd[15:0] b4h msw of dram control dramctl[31:16] b6h lsw of dram control dramctl[15:0] b8h msw of dram initialization draminit[31:16] bah lsw of dram initialization draminit[15:0] bch msw of dram timing dramtim[31:16] beh lsw of dram timing dramtim[15:0] table 10-3. serial eeprom load registers (continued) serial eeprom offset description register bits affected section 10 serial eeprom reset and initialization iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 10-7 section 10 ? reset & init c0h msw of dram base address drambase[31:16] c2h lsw of dram base address drambase[15:0] c4h msw of dram range dramrange[31:16] c6h lsw of dram range dramrange[15:0] c8h msw of default bus region descriptor dfltbrd[31:16] cah lsw of default bus region descriptor dfltbrd[15:0] cch msw of mailbox 0 mbox0[31:16] ceh lsw of mailbox 0 mbox0[15:0] d0h msw of mailbox 1 mbox1[31:16] d2h lsw of mailbox 1 mbox1[15:0] d4h device id pcidid[15:0] d6h vendor id pcivid[15:0] d8h base class code, subclass code pcirev[31:16] dah register level programming interface, revision id pcirev[15:0] dch pci subsystem id pcisvid[31:16] deh pci subsystem vendor id pcisvid[15:0] e0h msw of capability list pointer cap_ptr[31:16] e2h lsw of capability list pointer cap_ptr[15:0] e4h pci max_lat, pci min_gnt pciilr[31:16] e6h pci interrupt pin, pci interrupt line pciilr[15:0] e8h power management capabilities pmc[15:0] eah power management next item pointer, power management capability id pmcapid[15:0] ech msw of power management data scale values pmscale[31:6] eeh lsw of power management data scale values pmscale[15:0] f0h msw of power consumed values pwrcon[31:16] f2h lsw of power consumed values pwrcon[15:0] f4h msw of power dissipated values pwrdis[31:16] f6h lsw of power dissipated values pwrdis[15:0] f8h hot swap control/status hscsr[15:0] fa h hot swap next capability pointer, hot swap capability id hsnext[7:0] / hscapid[7:0] 1 fch msw of device initialization devinit[31:16] feh lsw of device initialization devinit[15:0] 1. together, the two make a 16-bit serial eeprom word. table 10-3. serial eeprom load registers (continued) serial eeprom offset description register bits affected section 10 reset and initialization iop 480 cpu boot iop 480 data book r2.0 10-8 ? 2000 plx technology, inc. all rights reserved. 10.5 iop 480 cpu boot this subsection describes the initial state of the iop 480 cpu after a reset, and contains an example of the initialization code required to begin executing application code. initialization of external system components or system-specific chip facilities may also need to be performed in addition to the basic initialization described in this section. the iop 480 cpu, after reset and the serial eeprom check, begins fetching instructions from local address 0xfffffffc. this address, by default, lies under the lcs0 bus region descriptor control (lcs0brd), and is, by default, an 8-bit-wide region. if this needs to be changed, then a serial eeprom is needed to change the default values. the iop 480 cpu is a powerpc risc microprocessor, and should be initialized as such. in addition, there are internal iop 480 registers outside of the cpu that may be initialized by the iop 480 cpu. refer to section 4, ? direct slave operation, ? and section 5, ? direct master operation, ? for more information regarding the initialization of these registers. one particular register bit that ought to be set either by the serial eeprom or by the iop 480 cpu is devinit[31], the local init. status bit. once devinit[31] is set to 1, the iop 480 stops retrying all pci accesses. 10.5.1 processor state after reset after a reset, the contents of special purpose registers (sprs) control the initial processor state. section 29, ? iop 480 cpu register summary, ? contains descriptions of the registers. in general, the contents of sprs are undefined after a reset. reset initializes the minimum number of spr fields required for allow successful instruction fetching. system software fully configures the processor. the mci field of the exception syndrome register (esr) is cleared so that it can be determined if there has been a machine check during initialization, before machine check exceptions are enabled. two sprs contain status on the type of reset that has occurred. the dbsr contains the most recent reset type. the tsr contains the most recent watchdog reset. table 10-4 lists the reset state of the initialized spr fields. 10.5.2 iop 480 cpu initial processor sequencing after any reset, the processor core fetches the word at address 0xfffffffc and attempts to execute it. the instruction at 0xfffffffc is typically a branch to initialization code. because the processor is initialized in big endian mode, initialization code must be in big endian format until the sler is configured otherwise. unless the instruction at 0xfffffffc is an unconditional branch, fetching can wrap to address 0x00000000 and attempt to execute the instruction at this location. the system must provide non-volatile memory or memory initialized by some other mechanism, external to the processor, at location 0xfffffffc and at the location of the initialization code, before a reset. section 10 iop 480 cpu boot reset and initialization iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 10-9 section 10 ? reset & init table 10-4. contents of registers after reset register field core reset comment msr ape 0 auxiliary processor exception disabled we 0 wait state disabled ce 0 critical interrupts disabled ee 0 external interrupts disabled pr 0 supervisor mode me 0 machine check interrupts disabled de 0 debug interrupts disabled ir 0 instruction translation disabled le 0 little endian disabled (big endian) cdbcr iocm value on tie_isocmmode instruction-side on-chip memory (ocm) mode dbcr edm 0 debug mode and events disabled rst 00 no reset action dbsr mrr most recent reset type most recent reset type esr mci 0 machine check exception has not occurred iccr s[0:31] 0x00000000 instruction cache is disabled pvr fam mem core chip 0x002 0x 0x0 0xnnn processor family sgr g[0:31] 0xffffffff storage is guarded skr k[0:31] 0x00000000 storage is not compressed sler s[0:31] 0x00000000 storage is big endian tcr wrc 00 watchdog timer reset disabled tsr wrs copy of tcr[wrc] if reset caused by watchdog timer undefined after power-on unchanged if reset not caused by watchdog timer section 10 reset and initialization iop 480 cpu boot iop 480 data book r2.0 10-10 ? 2000 plx technology, inc. all rights reserved. 10.5.3 initialization requirements when any reset is performed, the processor is initialized to a minimum configuration to start executing initialization code. initialization code is necessary to complete the processor and system configuration. the initialization code example in this section performs the configuration tasks required to prepare the iop 480 cpu to boot an operating system or run an application program. some portions of the initialization code work with system components that are beyond the scope of this data book. initialization code should perform the following tasks to configure the processor resources. to improve instruction fetching performance, initialize the sgr appropriately for guarded or unguarded storage. since all storage is initially guarded and speculative fetching is inhibited to guarded storage, reprogramming the sgr improves performance for unguarded regions. configure the following storage attribute control registers, if necessary: initialize the sler to configure the storage byte ordering initialize the skr to configure storage compression before executing instructions as cacheable: invalidate the instruction cache initialize the iccr to configure instruction cacheability before using storage access instructions: invalidate the data cache initialize cdbcr to determine if a store miss results in a line fill (woa) initialize the dcwr to select copy-back or write-through caching initialize the dccr to configure data cacheability before allowing interrupts (synchronous or asynchronous): initialize the evpr to point to vector table provide vector table with branches to interrupt handlers initialize msr(ile) bit for big endian or powerpc little endian mode for interrupt handlers before enabling asynchronous interrupts: initialize timer facilities initialize msr to enable appropriate interrupts initialize other processor features, such as the mmu, cache line locking, debug, apu (if implemented), and trace. initialize non-processor resources: initialize system memory as required by the operating system or application code initialize off-chip system facilities start the execution of operating system or application code section 10 initialization code example reset and initialization iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 10-11 section 10 ? reset & init 10.6 initialization code example the following initialization code example illustrates the steps that should be taken to initialize the processor before an operating system or user program begins execution. the example is presented in pseudo-code, function calls are named similarly to the iop 480 cpu mnemonics where appropriate. specific implementations may require different ordering of these sections to ensure proper operation. (refer to appendix c, ? real code example. ? ) /* ?????????????????????????????????????????????????????????????????*/ /*iop 480 cpu initialization pseudo code*/ /* ?????????????????????????????????????????????????????????????????*/ @0xfffffffc:/* initial instruction fetch from 0xfffffffc*/ ba(init_code);/* branch from initial address to initialization code*/ @init_code: /* ???????????????????????????????????????????????????????????????*/ /* configure guarded attribute for performance and cacheability.*/ /* ???????????????????????????????????????????????????????????????*/ mtspr(sgr, guarded_attribute); /* ???????????????????????????????????????????????????????????????*/ /* configure endianness and compression.*/ /* ???????????????????????????????????????????????????????????????*/ mtspr(sler, endianness); mtspr(skr, compression_attribute); /* ??????????????????????????????????????????? */ /* invalidate the instruction cache and enable cacheability*/ /* ??????????????????????????????????????????? */ address=0;/* start at first line */ for (line=0; line < n_lines; line++)/* i-cache has n_lines congruence classes */ { iccci(address);/* invalidate congruence class */ address += 16;/* point to the next congruence class */ } mtspr(iccr, i_cache_cacheability);/* enable i-cache*/ isync; section 10 reset and initialization initialization code example iop 480 data book r2.0 10-12 ? 2000 plx technology, inc. all rights reserved. /* ??????????????????????????????????????????????????????????????? */ /* invalidate the data cache and enable cacheability */ /* ??????????????????????????????????????????????????????????????? */ address=0;/* start at first line */ for (line=0; line section 10 reset and initialization dram initialization iop 480 data book r2.0 10-14 ? 2000 plx technology, inc. all rights reserved. 10.7 dram initialization the dram memory controller requires an initialization time of 13200 local clocks (after reset) before dram can be accessed. refer to section 12.3, ? dram, ? for details. 10.7.1 iop 480 initialization from pci bus a pci master can access the iop 480 internal registers by way of one of the following: memory access to the address specified in the pcibar0 register (pci base address for memory accesses to configuration registers and local space 0) pci configuration access iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-1 section 11 ? interrupts 11 interrupts 11.1 overview there are multiple sources of interrupts for the iop 480, but there are only two interrupt pins, pci inta# and local into. each pin has a global enable or disable bit. in addition, each source for an interrupt has a particular enable or disable, as well as a particular status bit indicating which interrupt source is active. 11.2 pci interrupts an iop 480 pci interrupt (inta#) can be asserted by one of the following: local-to-pci doorbell interrupt local interrupt input (inti) master/target abort interrupt dma pci interrupts messaging outbound post queue interrupt 256 consecutive pci retries inta#, or individual sources of an interrupt, can be enabled or disabled with the iop 480 interrupt enable register (pintenb). the register provides the interrupt status of each interrupt source. the iop 480 pci bus interrupt is a level output. disabling an interrupt enable bit or clearing the cause(s) of the interrupt can clear an interrupt. in adapter mode, inta# is an output only. in host mode, inta# is an input only. notes: for the above interrupts to activate inta#, the pci interrupt enable bit, pintenb[0], must be enabled. convention: pintenb[0] = active high, ~pintenb[0] = active low 11.2.1 local-to-pci doorbell interrupt a local bus master can assert a pci bus interrupt by writing to the local-to-pci doorbell register bit(s) (l2pdbell[31:0]). the pci host processor can read the pci doorbell interrupt active bit to determine whether a pci doorbell interrupt is pending (pintstat[11]), and if so, read the iop 480 local-to-pci doorbell register. each bit in the local-to-pci doorbell register is individually controlled. the local bus can only set bits in the local-to-pci doorbell register. from local bus, writing 1 to any bit position sets that bit and writing 0 has no effect. bits in the local-to-pci doorbell register can only be cleared from the pci bus. from the pci bus, writing 1 to any bit position clears that bit and writing 0 has no effect. interrupts remain set as long as any local-to-pci doorbell register bits are set and the pci doorbell interrupt enable bit (pintenb[11]) is set. to prevent race conditions from occurring when the pci bus is accessing the local-to-pci doorbell register (or any configuration register), the iop 480 automatically de-asserts ready# output to prevent local bus configuration accesses. 11.2.2 local interrupt input (inti) asserting the local interrupt input inti can assert a pci bus interrupt. the pci host processor can read the iop 480 status register (pintstat) to determine whether an interrupt is pending as a result of inti being asserted (pintstat[12]). the interrupt remains asserted as long as inti input is asserted and the local interrupt input is enabled. the pci host processor can take adapter-specific action to cause the local bus to release inti. if the pci interrupt enable bit is cleared (pintenb[12]=0), the pci interrupt (inta#) is de-asserted; however, the local interrupts (inti) and the status bit remain active. 11.2.3 master/target abort interrupt the iop 480 sets the received master/target abort bit (pintstat[13]=1) when it detects a master or target abort. this status bit causes pci inta# to be asserted if interrupts are enabled. the interrupt remains set as long as the received master abort or target abort bit remains set and the master/target abort interrupt is enabled. the received master/target abort interrupt bit (pintstat[13]=0) can be cleared by writing a 1 to the appropriate bit in the pci status register (pcisr[13] for master aborts or pcisr[12] for target aborts). section 11 interrupts pci interrupts iop 480 data book r2.0 11-2 ? 2000 plx technology, inc. all rights reserved. use pci type 0 configuration or local accesses to clear the received master/target abort interrupt bit (pintstat[13]=0). the interrupt control/status register bits (pintstat[18:16] are latched at the time of a master or target abort interrupt. these bits provide information as to which device was the master when the abort occurred. the iop 480 updates these bits only when an abort occurs. 11.2.4 dma pci interrupts each of the three dma channels can generate a pci inta# interrupt. a dma ? done ? interrupt occurs at the end of a single dma transfer if it is not in scatter/ gather mode, or at the completion of a group of scatter/gather dma transfers. the ? done ? interrupt is enabled by setting c0mode[10]/c1mode[10], and/or c2mode[13]. dma channels 0 and 1 can also be programmed to generate an interrupt after a transfer corresponding to a scatter/gather descriptor is completed. c0descptr[2]/c1descptr[2] (loaded from descriptor memory) determines whether to assert an interrupt at the end of the transfer for the current descriptor. the pci host processor can then read the pintstat register to determine which dma channel has a pending interrupt. the ? done ? status bit in the dma control/status register can be used to determine if the interrupt is a done interrupt or is the result of a transfer for a descriptor in scatter/gather mode. a dma interrupt is cleared by writing a 1 to bit 3 of the corresponding dma control/status register. 11.2.5 messaging unit outbound post queue interrupt when the outbound post queue is not empty, a pci inta# interrupt can be generated. this interrupt is enabled by clearing the outbound post queue interrupt mask bit (opqim[3]=0). the interrupt is cleared when the outbound post queue become empty. also, if the outbound option interrupt mask bit is enabled (qsr[8]=0), this interrupt is asserted if the hostoutidx and iopoutidx registers are not equal. 11.2.6 256 consecutive pci retries the iop 480 can be configured to respond to 256 consecutive pci retries as a target abort by setting the treat 256 pci retries as abort bit to 1 (pcictl[21]=1). when this function is enabled and 256 consecutive retries are detected, the iop 480 generates a target abort and sets the target abort generated bit (pintstat[19]=1). writing a 1 to the target abort bit (pcicsr[11]=1) clears the bit (pintstat[19]=0). 11.2.7 pci interrupt output (inta#) table 11-1 describes the pci interrupts (inta#). table 11-1. pci interrupts (inta#) interrupt source description register enable bit invoke interrupt clear interrupt interrupt status local-to-pci doorbell interrupt pintenb[11] l2pdbell[31:0] (write a 1 to any bit set from the local bus) l2pdbell[31:0] (write a 1 to bit set from the pci bus) pintstat[11] local interrupt input (inti) pintenb[12] inti ~inti pintstat[12] master/target abort interrupt pintenb[13] pcisr[12] / pcisr[13] pcisr[12] / pcisr[13] pintstat[13] dma ch 0 terminal count reached dma ch 1 terminal count reached pintenb[8] pintenb[9] c0descptr[2] c1descptr[2] c0csr[3] c1csr[3] pintstat[8] pintstat[9] dma ch 0 done dma ch 1 done dma ch 2 done pintenb[8] pintenb[9] pintenb[10] c0mode[10] c1mode[10] c2mode[12] c0csr[3] c1csr[3] c2csr[3] pintstat[8] pintstat[9] pintstat[10] messaging outbound post queue interrupt ~ opqim[3] ~qsr[8] outbound post queue not empty hostoutidx != iopoutidx outbound post queue becomes empty opqis[3] 256 consecutive pci retries pcictl[21] pcisr[11] pcisr[11] pintstat[19] section 11 pci system error output (serr#) interrupts iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-3 section 11 ? interrupts 11.3 pci system error output (serr#) the iop 480 generates an serr# pulse if parity checking is enabled in the pci command register and it detects an address parity error or the generate serr# bit (pintstat[0]) is changed from a 0 to a 1. the serr# output can be enabled or disabled through the serr# enable bit (pcicr[8]). 11.4 local interrupts a local interrupt can be asserted when any one of the following events occur: mailbox interrupt pci enum# interrupt pci pme# interrupt pci inta# interrupt pci serr# interrupt power management interrupt bist interrupt pci-to-local doorbell interrupt dma channel 0, 1, or 2 interrupt inti interrupt input pin asserted local bus parity error serial port interrupts local bus timeout pci bus parity error messaging unit outbound free queue overflow interrupt messaging unit inbound post queue not empty interrupt pci master or target abort cint critical interrupt refresh interrupt individual sources of the local interrupt can be enabled or disabled through the local interrupt output enable bit (lintenb[0]=1). the local interrupt status register (lintstat) provides status for each source of the interrupt. the local interrupt is connected to the following: extint interrupt input of the internal iop 480 cpu into local interrupt output pin pci inta# output interrupt the polarity of the into pin is controlled by lintenb[17]. 11.4.1 mailbox interrupt a local interrupt can be asserted when the pci host writes to one of the mailbox registers. each mailbox register has an associated interrupt enable bit in the local interrupt enable register (lintenb[31:24]). a local mailbox interrupt remains asserted until the mailbox is read by the internal or local cpu. the status of the mailbox interrupts is determined by reading the local interrupt status register (lintstat[31:24]). all byte enables must be active to generate an interrupt. 11.4.2 pci enumerate input (enum#) a pci hot swap enumerate interrupt (enum#) input can be serviced when the iop 480 is operating in pci host mode. if enum# is asserted, a local interrupt can be generated if enabled (lintenb[16, 0]=high). the local interrupt remains asserted as long as enum# is asserted and the interrupt is enabled. when operating in host mode, the enum# output should be disabled by writing a zero to the enum# interrupt mask bit (hscsr[1]=0). section 11 interrupts local interrupts iop 480 data book r2.0 11-4 ? 2000 plx technology, inc. all rights reserved. 11.4.3 pci power management event input (pme#) a pci power management event interrupt (pme#) input can be serviced when the iop 480 is operating in pci host mode. if pme# is asserted, a local interrupt can be generated if enabled (lintenb[15, 0]=high). the local interrupt remains asserted as long as pme# is asserted and the interrupt is enabled. when operating in host mode, the pme# output should be disabled by writing a zero to the pme_en bit (pmcsr[8]=0). 11.4.4 pci interrupt input (inta#) a pci interrupt (inta#) input can be serviced when the iop 480 is operating in pci host mode. if inta# is asserted, a local interrupt can be generated if enabled (lintenb[14, 0]=high). the local interrupt remains asserted as long as inta# is asserted and the interrupt is enabled. when operating in host mode, the inta# output should be disabled by writing a zero to the pci interrupt output enable bit (pintenb[0]=0). 11.4.5 pci system error input (serr#) a pci system error (serr#) input can be serviced when the iop 480 is operating in pci host mode. if serr# is asserted, a local interrupt can be generated if enabled lintenb[20, 0]=high). the local interrupt remains asserted as long as serr# is asserted or lintstat[20] is not clear and the interrupt is enabled. to clear the serr# interrupt, write a 1 to lintstat[20]. when operating in host mode, the serr# output should be disabled by writing a zero to the serr# enable bit (pcicr[8]=0). 11.4.6 power management interrupt a change in the power management state can cause a local interrupt if enabled lintenb[13, 0]=high). the power management state is changed when the host writes to the power state bits (pmcsr[1:0]). the status of this interrupt can be read from the power management interrupt bit (lintstat[13]), and is cleared by writing a 1 to this bit [lintstat[13]=1). 11.4.7 built-in self test interrupt (bist) a pci bus master can generate a local bus interrupt by performing a pci type 0 configuration write to the bist start bit (pcibistr[6]). the local processor can then read the bist interrupt bit (lintstat[12]) to determine that a bist interrupt is pending. the local interrupt remains asserted as long as pcibistr[6] is set and the bist interrupt is enabled. the local bus should reset the bit when bist is complete. the pci host software may fail the device if the bit is not reset after two seconds. 11.4.8 pci-to-local doorbell interrupt a pci bus master can generate a local bus interrupt by writing to the pci-to-local doorbell register. the local processor can then read the local doorbell interrupt bit (lintstat[11]) to determine that a doorbell interrupt is pending. it can then read the pci-to-local doorbell (p2ldbell) register. each bit in the pci-to-local doorbell register is individually controlled. bits in the doorbell register can only be set by the pci bus. from the pci bus, writing a 1 to any bit position sets that bit and writing a 0 to a bit position has no effect. bits in the pci-to-local doorbell register can only be cleared from the local bus. from the local bus, writing a 1 to any bit position clears that bit and writing a 0 to a bit position has no effect. if the local bus cannot clear the doorbell interrupt, do not use the pci-to-local doorbell register. the interrupt remains asserted as long any of the pci-to-local doorbell registers bits are set and the local doorbell interrupt is enabled. to prevent race conditions from occurring when the local bus is accessing the p2ldbell register (or any other configuration register), the iop 480 automatically issues a retry to the pci bus. section 11 local interrupts interrupts iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-5 section 11 ? interrupts 11.4.9 dma local interrupts each of the three dma channels can generate a local interrupt. a dma ? done ? interrupt occurs at the end of a single dma transfer if not in scatter/gather mode, or at the completion of a group of scatter/gather dma transfers. the ? done ? interrupt is enabled by setting the done interrupt enable bit(s) (c0mode[10]/ c1mode[10] and/or c2mode[13]). dma channels 0 and 1 can also be programmed to generate an interrupt after a transfer corresponding to a scatter/gather descriptor is completed. the interrupt after terminal count bit(s) (c0descptr[2] and/or c1descptr[2]), loaded from descriptor memory, determines whether to assert an interrupt at the end of the transfer for the current descriptor. the local host processor can then read the lintstat register to determine which dma channel has a pending interrupt. the ? done ? status bit in the dma control/status register can be used to determine if the interrupt is a done interrupt or is the result of a transfer for a descriptor in scatter/gather mode. a dma interrupt is cleared by writing a 1 to bit 3 of the corresponding dma control/status register. 11.4.10 local interrupt input asserting the inti pin can cause a local interrupt. this interrupt is enabled by setting the inti interrupt enable bit (lintenb[7]), and status is reported on the inti interrupt bit (lintstat[7]). the interrupt remains asserted as long as the inti pin is asserted and the local interrupt input is enabled. the polarity of the inti pin is controlled by lintenb[18]. 11.4.11 local bus parity error a data parity error detected on the local data bus can cause a local interrupt. this interrupt is enabled by setting the local parity error interrupt enable bit (lintenb[6]), and status is reported on the local bus parity error bit (lintstat[6]). the interrupt is cleared by writing a 1 to lintstat[6]. parity error checking is selectively enabled in each of the six bus region descriptor registers in the memory controller. 11.4.12 serial port interrupts the internal serial port can generate two interrupts which can cause a local interrupt. these interrupts are enabled by setting the serial port interrupt 2 and 1 enable bits (lintenb[5:4], respectively), and status is reported on lintstat[5:4]. 11.4.13 local bus timeout a timeout detected on the local data bus can cause a local interrupt to be asserted. this interrupt is enabled by setting the local timeout interrupt enable bit (lintenb[3]), and status is reported on the local bus timeout interrupt bit (lintstat[3]). the interrupt is cleared by writing a 1 to lintstat[3]. the local bus timeout timer is loaded with the value in loctmr[14:0] at the beginning of every local access. if the counter decrements to zero before a ready# is detected, a timeout is generated. 11.4.14 pci bus parity errors pci bus parity errors can be enabled to cause a local interrupt. if either the master data parity error detected bit (pcisr[8]) or the parity error detected bit (pcisr[15]) are set in the pci status register, then a local interrupt is generated if the pci bus parity error interrupt enable bit (lintenb[2]) is set. status for this interrupt is reported on the pci error interrupt bit (lintstat[2]). the interrupt is cleared by writing a 1 to the master data parity error detected bit (pcisr[8]) or the parity error detected bit (pcisr[15]). 11.4.15 messaging unit outbound free queue overflow interrupt an outbound free queue overflow can cause a local interrupt. this interrupt is enabled by setting the pci parity error interrupt enable bit (lintenb[2]) and clearing the outbound free queue overflow interrupt mask bit (qsr[6]). status is reported on lintstat[2]. the interrupt is cleared by writing a 1 to the outbound free queue overflow interrupt bit (qsr[7]). because this interrupt shares the same enable and status bit as pci parity errors, qsr[7:4] and pcisr[15, 8] can be read to determine the source of the interrupt. section 11 interrupts local interrupts iop 480 data book r2.0 11-6 ? 2000 plx technology, inc. all rights reserved. 11.4.16 messaging unit inbound post queue interrupt when the inbound post queue is not empty, a local interrupt can be generated. this interrupt is enabled by writing a zero to the inbound post queue interrupt mask bit (qsr[4]). the interrupt is cleared when the inbound post queue become empty. because this interrupt shares the same enable and status bit as pci parity errors, qsr[7:4] and pcisr[15, 8] can be read to determine the source of the interrupt. 11.4.17 master/target abort interrupt the iop 480 sets the master abort or target abort status bit in the pci configuration register upon detection of a master or target abort. a target abort is also assumed if the iop 480 detects 256 retry responses during a direct master cycle. these status bits cause a local interrupt to be asserted if the pci abort interrupt enable bit is enabled (lintenb[1]=1). the interrupt status can be read from the pci abort interrupt bit (lintstat[1]), and remains asserted as long as the master or target abort bits remain set in the pci configuration status register and master/target abort interrupt is enabled. the master or target abort detected bits (pintstat[18:16], respectively) are latched at the time of a target abort interrupt or a master abort interrupt. they provide information as to who was master when an abort occurred. they are updated only when an abort occurs. (refer to figure 11-1.) figure 11-1. dma, local-to-pci bus note: the figure represents a sequence of bus cycles. 11.4.18 cint critical interrupt the cint critical interrupt input can generate a local interrupt and is enabled by setting the cint/user2 pin select bit to 0 (locctl[8]=0). the polarity of cint is controlled by (linenb[19]). 11.4.19 refresh interrupt sdram refreshes can generate local interrupts if two refresh requests occur without a grant occurring between the two requests. this interrupt is enabled by setting the refresh local interrupt enable bit to 1 (lintenb[21]=1). the refresh local interrupt status can be read in the local interrupt status register (lintstat[21]). iop 480 lad, ads#, lwr# devsel#, trdy# pci bus local bus lhold lholda lad, ready# dma start (c1locadr & c1count) dma start (c1locadr & c1count) req# gnt# irdy# ad (addr & data) slave master master slave section 11 local interrupts interrupts iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-7 section 11 ? interrupts 11.4.20 local interrupt output (into) notes: for the above local interrupts to activate into, the local interrupt enable bit, lintenb[0], must be enabled. convention: lintenb[0] = active high, ~lintenb[0] = active low into polarity is determined by lintenb[17]: lintenb[17] = 1 ? into active high lintenb[17] = 0 ? into active low table 11-2. local interrupts (into) interrupt source description register enable bit invoke interrupt clear interrupt interrupt status abort interrupt lintenb[1] pcisr[12] / pcisr[13] pcisr[12] / pcisr[13] (depends on which is set) lintstat[1] bist interrupt lintenb[12] pcibistr[6] by pci ~pcibistr[6] by local lintstat[12] dma ch 0 terminal count reached dma ch 1 terminal count reached lintenb[8] lintenb[9] c0descptr[2] c1descptr[2] c0csr[3] c1csr[3] lintstat[8] lintstat[9] dma ch 0 done dma ch 1 done dma ch 2 done lintenb[8] lintenb[9] lintenb[10] c0mode[10] c1mode[10] c2mode[13] c0csr[3] c1csr[3] c2csr[3] lintstat[8] lintstat[9] lintstat[10] inti interrupt, input pin asserted lintenb[7] inti with lintenb[18] (polarity) lintstat[7] lintstat[7] local bus parity error lintenb[6] lintstat[6] lintstat[6] lintstat[6] local bus timeout lintenb[3] lintstat[6] lintstat[3] lintstat[3] mailbox interrupt (0-7) lintenb[24:31] pci host writes to the mailbox register local master reads the mailbox lintstat[24:31] messaging unit inbound post queue interrupt ~qsr[4] inbound post queue becomes non-empty inbound post queue becomes empty lintstat[2] messaging unit outbound free queue overflow interrupt lintenb[2] ~qsr[6] qsr[7] qsr[7] (write a message frame address 1) lintstat[2] pci bus parity error lintenb[2] pcisr[8] / pcisr[15] pcisr[8] / pcisr[15] (depends on which is set) lintstat[2] pci enum# interrupt lintenb[16] enum# or lintstat[16] lintstat[16] lintstat[16] pci inta# interrupt lintenb[14] inta# or lintstat[14] lintstat[14] lintstat[14] pci pme interrupt lintenb[15] pme# or lintstat[15] lintstat[15] lintstat[15] pci serr# interrupt lintenb[20] serr# or lintstat[20] lintstat[20] lintstat[20] pci-to-local doorbell interrupt lintenb[11] p2ldbell[31:0] (write a 1 to any bit from the pci bus) p2ldbell[31:0] (write a 1 to bit set from the local bus) lintstat[11] power management interrupt lintenb[13] change power state to pmcsr[1:0] lintstat[13] lintstat[13] refresh interrupt lintenb[21] lintstat[21] lintstat[21] lintstat[21] serial port interrupt 1 lintenb[4] (l_uart+'20h[31] / l_uart+'20h[4]) l_uart[5] / l_uart[6] write a 1 to the bit that invokes the interrupt (l_uart[6:5]) lintstat[4] serial port interrupt 2 lintenb[5] (l_uart+'1ch[3] / l_uart+'1ch[4]) l_uart[0] / l_uart[1] / l_uart[2] / l_uart[3] / l_uart[4] write a 1 to the bit that invokes the interrupt (l_uart[0-4]) lintstat[5] section 11 interrupts doorbell registers iop 480 data book r2.0 11-8 ? 2000 plx technology, inc. all rights reserved. 11.5 doorbell registers the iop 480 has two 32-bit doorbell interrupt/status registers. one is assigned to the pci bus interface. the other is assigned to the local bus interface. a local processor can assert a pci bus interrupt by writing any number other than all zeroes to the local-to-pci doorbell register bits (l2pdbell[31:0]=1 and pintenb[0]=1). a pci host can assert a local bus interrupt by writing any number other than all zeroes to the pci-to-local doorbell register bits (p2ldbell[31:0]=1 and lintenb[0]=1). figure 11-2. mailbox and doorbell message passing 11.6 mailbox registers the iop 480 has eight 32-bit mailbox registers that can be written to and read from both buses. these registers can be used to pass command and status information directly between the pci bus and local bus devices. a local interrupt can be asserted, if the local interrupt output enable and mailbox interrupt enable bits are enabled (lintenb[0] and lintenb[31:24], respectively), when the pci host writes to one of the eight mailbox registers. all byte enables must be active to generate an interrupt. 11.7 iop 480 exceptions, interrupts, and timers exceptions in the iop 480 cpu are generated by signals from external peripherals, instructions, the internal timer facility, debug events, and error conditions. two external interrupt signals are provided in the iop 480 cpu, one critical and one non-critical. both external interrupts are maskable. this chapter begins by defining the terminology of exceptions and interrupts in section 11.7.1, ? interrupts and exceptions. ? table 11-4 on page 11-13 lists the exceptions which are handled by the in the order of exception vector offsets. detailed descriptions of each exception follow, in the same order. table 11-4 on page 11-13 also provides an index to the descriptions. several registers support exception handling and control. section 11.7.3, ? general exception handling registers, ? on page 11-13, describes the general exception handling registers: data exception address register (dear) exception syndrome register (esr) exception vector prefix register (evpr) machine state register (msr) save/restore registers (srr0 ? srr3) critical and non-critical external interrupt signals are enabled by the msr. section 11.7.5, ? machine check exceptions, ? on page 11-20, describes machine checks. section 11.7.18, ? timer facilities, ? on page 11-28, describes the timer facilities of the iop 480 cpu, including the time base and the registers time base low register (tblo), time base low user-mode (tblu), time base high register (tbhi), and time base high user-mode (tbhu). this section also describes the timer-related registers: the timer status register (tsr) and the timer control register (tcr), and the programmable interval timer (pit) register. 11.7.1 interrupts and exceptions an interrupt is the action in which the processor saves its old context (msr and instruction pointer) and begins execution at a pre-determined interrupt-handler address, with a modified msr. exceptions are events which, if enabled, cause the processor to take an interrupt. set int0# (interrupt) inta# set doorbell registers set and clear interrupts mailbox registers can be read and/or written from both sides mailbox 0 mailbox 1 mailbox 2 mailbox 3 mailbox 4 mailbox 5 mailbox 6 mailbox 7 pci-to-local local-to-pci used for passing commands pointers status local bus local bus pci bus pci bus section 11 iop 480 exceptions, interrupts, and timers interrupts iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-9 section 11 ? interrupts 11.7.1.1 architectural definitions and behavior precise interrupts are those for which the instruction pointer saved by the interrupt must be either the address of the excepting instruction or the address of the next sequential instruction. imprecise interrupts are those for which it is possible (not required, just possible) for the saved instruction pointer to be something else, possibly prohibiting guaranteed software recovery. note: ? precise ? and ? imprecise ? are defined assuming that the interrupts are unmasked (enabled to occur) when the associated exception occurs. consider an exception that would cause a precise interrupt, were the interrupt enabled at the time of the exception, but that occurs while the interrupt is masked. some exceptions of this type can cause the interrupt to occur later, immediately upon its enabling. in such a case, the interrupt is not considered precise with respect to the enabling instruction, but imprecise ( ? delayed precise ? ) with respect to the cause of the exception. asynchronous interrupts are caused by events which are independent of instruction execution. all asynchronous interrupts are precise, and the following rules apply: 1. all instructions prior to the one whose address is reported to the exception handling routine (in the save/restore register) have completed execution. however, some storage accesses generated by these preceding instructions may not have completed. 2. no subsequent instruction has begun execution, including the instruction whose address is reported to the exception handling routine. 3. the instruction having its address reported to the exception handler may appear not to have begun execution, or may have partially completed. synchronous interrupts are caused directly by the execution (or attempted execution) of instructions. synchronous interrupts can be either precise or imprecise. for synchronous precise interrupts, the following rules apply: 1. the save/restore register addresses either the instruction causing the exception or the next sequential instruction. which instruction is addressed is determined by the interrupt type and status bits. 2. all instructions preceding the instruction causing the exception have completed execution. however, some storage accesses generated by these preceding instructions may not have completed. 3. the instruction causing the exception may appear not to have begun execution (except for causing the exception), may have partially completed, or may have completed, depending on the interrupt type. 4. no subsequent instruction has begun execution. the iop 480 cpu does not implement any imprecise interrupts. refer to the ibm powerpc embedded environment for an architectural description of imprecise interrupts. machine check interrupts are a special case typically caused by some kind of hardware or storage subsystem failure, or by an attempt to access an invalid address. a machine check can be indirectly caused by the execution of an instruction, but not recognized or reported until long after the processor has executed past the instruction that caused the machine check. as such, machine check interrupts cannot properly be thought as synchronous, nor as precise or imprecise. however, in the iop 480 cpu, machine checks are handled precisely as critical interrupts (refer to section 11.7.2, ? critical and non- critical exceptions, ? on page 11-10). for machine checks, the following general rules apply: 1. no instruction following the one whose address is reported to the machine check handler in the save/ restore register has begun execution. 2. the instruction whose address is reported to the machine check handler in the save/restore register, and all previous instructions, may or may not have completed successfully. all previous instructions that would ever complete have completed, within the context existing before the machine check interrupt. no further interrupt (other than possible additional machine checks) can occur as a result of those instructions. section 11 interrupts iop 480 exceptions, interrupts, and timers iop 480 data book r2.0 11-10 ? 2000 plx technology, inc. all rights reserved. 11.7.1.2 iop 480 cpu implementation behavior all exceptions are handled precisely. precise handling implies that the address of the excepting instruction (for synchronous exceptions other than the system call exception), or the address of the next instruction to be executed (asynchronous exceptions and the system call exception), is passed to an exception handling routine. precise handling also implies that all instructions that precede the instruction whose address is reported to the exception-handling routine have executed and that no subsequent instruction has begun execution. the specific instruction whose address is reported may not have begun execution or may have partially completed, as specified for each precise exception type. synchronous precise exceptions include most debug exceptions, program exceptions, instruction and data storage exceptions, tlb miss exceptions, system call, and alignment exceptions. asynchronous precise exceptions include the critical interrupt exception, external interrupts, internal peripherals, internal timer facility exceptions, and some debug events. the machine check exceptions, which are neither synchronous or asynchronous, are handled precisely. the synchronism of instruction-side machine checks (errors that occur while attempting to fetch an instruction from external memory) require further explanation. fetch requests to cacheable memory that miss in the instruction cache (icu) cause an instruction cache line fill (four lwords). if any lwords in the fetched line are associated with an error, an exception occurs upon attempted execution and the cache line is invalidated. it is improper to declare an exception when an erroneous lword is passed to the fetcher; the address could be the result of an incorrect speculative access. it is quite likely that no attempt will be made to execute an instruction from the erroneous address. an n instruction-side machine check exception occurs only when execution is attempted. if the exception occurs, execution is suppressed, srr2 contains the erroneous address, and the esr indicates that instruction-side machine check occurred. although such an exception is clearly asynchronous to the erroneous memory access, it is handled synchronously with respect to the attempted execution from the erroneous address. except for machine checks, all iop 480 cpu exceptions are handled precisely: the address of the excepting instruction (for synchronous exceptions, other than the system call exception) or the address of the next sequential instruction (for asynchronous exceptions and the system call exception) is passed to the exception- handling routine. all instructions that precede the instruction whose address is reported to the exception-handling routine have completed execution and that no subsequent instruction has begun execution. the specific instruction whose address is reported might not have begun execution or might have partially completed, as specified for each exception type. 11.7.1.3 exception-handling priorities in the iop 480 cpu, only one exception is handled at a time. multiple simultaneous exceptions are handled in the priority order shown in table 11-3 on page 11-12. 11.7.2 critical and non-critical exceptions the iop 480 cpu processes exceptions as non- critical and critical. six exceptions are defined as non-critical : program exception, system call exception, alignment exception, an active external interrupt input, fixed interval timer (fit) exception, and pit exception. five exceptions are defined as critical : machine check exceptions (instruction- and data-side), debug exceptions (any of the three types), exceptions caused by an active critical interrupt input, and the first timeout from the watchdog timer. when a non-critical exception is taken, save/restore register 0 (srr0) is written with the address of the excepting instruction (most synchronous exceptions) or the next sequential instruction to be processed (asynchronous exceptions and system call). if the iop 480 cpu was executing a multi-cycle instruction (load/store, multiply, divide, or cache operation), the instruction is terminated and its address is written in srr0. when load instructions terminate, the addressing registers are not updated. this ensures that the instructions can be restarted; if the addressing registers were in the range of registers section 11 iop 480 exceptions, interrupts, and timers interrupts iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-11 section 11 ? interrupts to be loaded, this would be an invalid form in any event. some target registers of a load instruction may have been written by the time of the exception; when the instruction restarts, the registers are simply written again. similarly, some of the target memory of a store instruction may have been written, and is again written when the instruction restarts. save/restore register 1 (srr1) is written with the contents of the msr; the msr is then updated to reflect the new machine context. the new msr contents take effect beginning with the first instruction of the exception handling routine. exception handling routine instructions are fetched at an address determined by the exception type. the address of the exception handling routine is formed by concatenating the 16 high-order bits of the evpr and the exception vector offset. (a user must initialize the evpr contents at power-up using an mtspr instruction.) table 11-4 on page 11-13 shows the exception vector offsets for the exception types. note that there may be multiple sources of the same exception type; exceptions of the same type are mapped to the same exception vector, regardless of source. in such cases, the exception handling routine must examine status registers to determine the exact source of the exception. at the end of the exception handling routine, execution of an rfi instruction forces the contents of srr0 and srr1 to be written to the program counter and the msr, respectively. execution then begins at the address in the program counter. critical exceptions are processed similarly. when a critical exception is taken, save/restore register 2 (srr2) and save/restore register 3 (srr3) hold the next sequential address to be processed when returning from the exception and the contents of the msr, respectively. at the end of the critical exception handling routine, execution of an rfci instruction writes the contents of srr2 and srr3 into the program counter and the msr, respectively. section 11 interrupts iop 480 exceptions, interrupts, and timers iop 480 data book r2.0 11-12 ? 2000 plx technology, inc. all rights reserved. table 11-3. exception-handling priorities priority exception type critical or non-critical causing conditions 1 machine check ? data critical external bus error during data-side access. 2 debug ? iac critical iac debug event while in internal debug mode. 3 machine check ? instruction critical attempted execution of instruction for which an external bus error occurred during fetch. 4 debug ? ude, exc critical ude or exc debug event while in internal debug mode. 5 critical interrupt input critical active level on the critical interrupt input. 6 watchdog timer ? first timeout critical posting of an enabled first timeout of the watchdog timer in the tsr. 7 instruction tlb miss non-critical attempted execution of an instruction at an address and process id for which a valid matching entry was not found in the tlb. 8 instruction storage exception ? zpr[zn]=00 non-critical instruction translation is active, execution access to the translated address is not permitted because zpr[zn]=00 in user mode, and an attempt is made to execute the instruction. 9 instruction storage exception ? tlb_entry[ex]=0 non-critical instruction translation is active, execution access to the translated address is not permitted because tlb_entry[ex]=0, and an attempt is made to execute the instruction. instruction storage exception ? tlb_entry[g]=1 non-critical instruction translation is active, the page is marked guarded, and an attempt is made to execute the instruction. 10 program non-critical attempted execution of illegal instructions, trap instruction, or privileged instruction in problem state. system call non-critical execution of the sc instruction. 11 data tlb miss non-critical valid matching entry for the effective address and process id of an attempted data access is not found in the tlb. 12 data storage exception ? zpr[zn]=00 non-critical data translation is active and data-side access to the translated address is not permitted because zpr[zn]=00 in user mode. 13 data storage exception ? tlb_entry[wr]=0 non-critical data translation is active and write access to the translated address is not permitted because tlb_entry[wr]=0. 14 data storage exception ? cache line locking non-critical msr[pr]=1, and: dcbt and cdbcr[duxe]=1; dcbz and cdbcr[dlxe]=1); icbi and cdbcr[iuxe]=1. 15 alignment non-critical misaligned data accesses in powerpc little endian mode; dcbz to non-cacheable address or write-through storage; any string or multiple instruction in powerpc little endian mode; non-lword-aligned dcread , lwarx , and stwcx as described in table 11-12 on page 11-24. 16 debug ? ic, bt, tie, dac critical ic, bt, tie, or dac debug event while in internal debug mode. 17 external interrupt input non-critical interrupts from the extint pin. 18 fixed interval timer (fit) non-critical posting of an enabled fit interrupt in the tsr. 19 programmable interval timer (pit) non-critical posting of an enabled pit interrupt in the tsr. section 11 iop 480 exceptions, interrupts, and timers interrupts iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-13 section 11 ? interrupts 11.7.3 general exception handling registers the general exception handling registers are the machine state register (msr), srr0 ? srr3, the exception vector prefix register (evpr), the exception syndrome register (esr), and the data exception address register (dear). 11.7.3.1 machine state register (msr) the msr is a 32-bit register that holds the current context of iop 480 cpu. when a non-critical interrupt is taken, the msr contents are written to srr1; when a critical interrupt is taken, the msr contents are written to srr3. when an rfi or rfci instruction executes, the contents of the msr are read from srr1 or srr3, respectively. the msr contents can be read into general purpose registers (gprs) using an mfmsr instruction. the contents of a gpr can be written to the msr using an mtmsr instruction. the msr[ee] bit may be set/ cleared atomically using the wrtee or wrteei instructions. register 11-1 illustrates the msr bits. table 11-4. exception vector offsets offset exception type exception class category page 0x0100 critical interrupt asynchronous precise critical 11-19 0x0200 machine check ? data ? critical 11-21 machine check ? instruction ? critical 11-20 0x0300 data storage exception ? msr[dr]=1 and zpr[zn]=0 or tlb_entry[wr]=0 synchronous precise non-critical 11-21 0x0400 instruction storage exception synchronous precise non-critical 11-22 0x0500 external interrupt asynchronous precise non-critical 11-23 0x0600 alignment synchronous precise non-critical 11-24 0x0700 program synchronous precise non-critical 11-24 0x0c00 system call synchronous precise non-critical 11-25 0x1000 pit asynchronous precise non-critical 11-26 0x1010 fit asynchronous precise non-critical 11-26 0x1020 watchdog timer asynchronous precise critical 11-27 0x1100 data tlb miss synchronous precise non-critical 11-27 0x1200 instruction tlb miss synchronous precise non-critical 11-27 0x2000 debug exception ? ic, bt, tie, ia1, dr1, dw1 synchronous precise critical 11-28 debug exception ? ude, exc asynchronous precise critical section 11 interrupts iop 480 exceptions, interrupts, and timers iop 480 data book r2.0 11-14 ? 2000 plx technology, inc. all rights reserved. register 11-1. machine state register (msr) 0:10 reserved 11 ape auxiliary processor exception enable 0 auxiliary processor exception disabled. 1 auxiliary processor exception enabled. 12 apa auxiliary processor available 0 auxiliary processor not available. 1 auxiliary processor available. 13 we wait state enable 0 the processor is not in the wait state. 1 the processor is in the wait state. if msr[we]=1, the processor remains in the wait state until an exception is taken, a reset occurs, or an external debug tool clears we. 14 ce critical interrupt enable 0 critical interrupts are disabled. 1 critical interrupts are enabled. controls the critical interrupt input and watchdog timer first timeout interrupts. 15 ile interrupt little endian 0 interrupt handlers execute in big endian mode. 1 interrupt handlers execute in powerpc little endian mode. copied to msr(le) when an interrupt is taken. 16 ee external interrupt enable 0 asynchronous exceptions are disabled. 1 asynchronous exceptions are enabled. controls the non-critical external interrupt input, programmable interval timer, and fixed interval timer interrupts. 17 pr problem state 0 supervisor state (all instructions allowed). 1 problem state (some instructions not allowed). 18 reserved 19 me machine check enable 0 machine check exceptions are disabled. 1 machine check exceptions are enabled. 20:21 reserved 22 de debug exception enable 0 debug exceptions are disabled. 1 debug exceptions are enabled. 23:25 reserved 26 ir instruction relocate 0 instruction address translation is disabled. 1 instruction address translation is enabled. if tie_cpummuen is 0, reading or writing this bit has no effect. 27 dr data relocate 0 data address translation is disabled. 1 data address translation is enabled. if tie_cpummuen is 0, reading or writing this bit has no effect. 28:30 reserved 31 le little endian 0 processor executes in big endian mode. 1 processor executes in powerpc little endian mode. 13 14 16 19 22 28 29 0 12 15 17 18 20 21 23 27 30 31 we pr de ce ee me ile le 26 25 ir dr 28 11 apa ape 10 section 11 iop 480 exceptions, interrupts, and timers interrupts iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-15 section 11 ? interrupts 11.7.3.2 save/restore registers 0 and 1 (srr0 ? srr1) srr0 and srr1 are 32-bit registers that hold the interrupted machine context when a non-critical interrupt is processed. on interrupt, srr0 is set to the current or next instruction address and the contents of the msr are written to srr1. when an rfi instruction is executed at the end of the interrupt handler, the program counter and the msr are restored from srr0 and srr1, respectively. the contents of srr0 and srr1 can be written into gprs using the mfspr instruction. the contents of gprs can be written to srr0 and srr1 using the mtspr instruction. register 11-2 illustrates the srr0 bits. register 11-3 illustrates the srr1 bits. 11.7.3.3 save/restore registers 2 and 3 (srr2 ? srr3) srr2 and srr3 are 32-bit registers that hold the interrupted machine context when a critical interrupt is processed. on interrupt, srr2 is set to the current or next instruction address and the contents of the msr are written to srr3. when an rfci instruction is executed at the end of the interrupt handler, the program counter and the msr are restored from srr2 and srr3, respectively. the contents of srr2 and srr3 can be written to gprs using the mfspr instruction. the contents of gprs can be written to srr2 and srr3 using the mtspr instruction. register 11-4 illustrates the srr2 bits. register 11-5 illustrates the srr3 bits. section 11 interrupts iop 480 exceptions, interrupts, and timers iop 480 data book r2.0 11-16 ? 2000 plx technology, inc. all rights reserved. . register 11-2. save/restore register 0 (srr0) 0:29 srr0 receives an instruction address when a non-critical interrupt is taken; the program counter is restored from srr0 when rfi executes. 30:31 reserved register 11-3. save/restore register 1 (srr1) . 0:31 srr1 receives a copy of the msr when a critical interrupt is taken; the msr is restored from srr1 when rfi executes. register 11-4. save/restore register 2 (srr2) 0:29 srr2 receives an instruction address when a critical interrupt is taken; the program counter is restored from srr2 when rfci executes. 30:31 reserved register 11-5. save/restore register 3 (srr3) 0:31 srr3 receives a copy of the msr when a critical interrupt is taken; the msr is restored from srr3 when rfci executes. 0 29 30 31 13 14 16 19 22 28 29 01215 17 18 20 21 23 27 30 31 we pr de ce ee me ile le 26 25 ir dr 28 11 apa ape 10 0 29 30 31 13 14 16 19 22 28 29 01215 17 18 20 21 23 27 30 31 we pr de ce ee me ile le 26 25 ir dr 28 11 apa ape 10 section 11 iop 480 exceptions, interrupts, and timers interrupts iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-17 section 11 ? interrupts 11.7.3.4 exception vector prefix register (evpr) the evpr is a 32-bit register whose high-order 16 bits contain the prefix for the address of an exception processing routines. the 16-bit exception vector offsets (shown in table 11-4, ? exception vector offsets, ? on page 11-13) are concatenated to the right of the high-order 16 bits of the evpr to form the 32-bit address of the exception processing routine. the contents of the evpr can be written to a gpr using the mfspr instruction. the contents of a gpr can be written to evpr using the mtspr instruction. register 11-6 illustrates the evpr bits. 11.7.3.5 exception syndrome register (esr) the esr is a 32-bit register whose bits help to specify the exact cause of various synchronous exceptions. these exceptions include instruction and data side machine checks, data storage exceptions, program exceptions, instruction storage exceptions, and data tlb miss exceptions. section 11.7.5.1, ? instruction machine check handling, ? on page 11-20, describes instruction machine checks. section 11.7.6, ? data storage exceptions, ? on page 11-21, describes data storage exceptions. section 11.7.10, ? program exceptions, ? on page 11-24, describes program exceptions. although exception-handling routines are not required to reset the esr, it is recommended that instruction machine check handlers reset the esr; section 11.7.5.1, ? instruction machine check handling, ? on page 11-20 describes why such resets are recommended. the contents of the esr can be written to a gpr using the mfspr instruction. the contents of a gpr can be written to the esr using the mtspr instruction register 11-7 illustrates the esr bits. in general, esr bits are set to indicate the kind of precise interrupt that occurred; other bits are cleared. the machine check ? instruction (esr[mci]) bit behaves differently, however. because instruction- side machine checks can occur without an interrupt being taken (if msr[me]=0), this bit is set even when other esr-setting exceptions (data storage, program, dtlb-miss) are occurring. thus, data storage and program exceptions leave esr[mci] alone, but clear the data storage and program exception bits that are not associated with the specific data storage or program exception that is occurring. enabled instruction-side machine checks (msr[me]=1) set esr[mci] and clear the data storage and program exception bits. if a machine check ? instruction exception occurs but is disabled (msr[me]=0), it sets esr[mci] but leaves the data storage and program exception bits alone. if a machine check ? instruction exception occurs while msr[me]=0, and the instruction upon which the machine check ? instruction exception is occurring also is some other kind of esr-setting instruction (program, dtlb-miss, or instruction storage exception), esr[mci] is set to indicate that a machine check ? instruction exception occurred; the other esr bits are set or cleared to indicate the other exception. these scenarios are summarized in table 11-5 on page 11-19. register 11-6. exception vector prefix register (evpr) 0:15 exception vector prefix 16:31 reserved 015 31 16 section 11 interrupts iop 480 exceptions, interrupts, and timers iop 480 data book r2.0 11-18 ? 2000 plx technology, inc. all rights reserved. register 11-7. exception syndrome register (esr) 0 mci machine check ? instruction 0 instruction machine check did not occur. 1 instruction machine check occurred. 1:3 reserved 4 pil program exception ? illegal 0 illegal instruction error did not occur. 1 illegal instruction error occurred. 5 ppr program exception ? privileged 0 privileged instruction error did not occur. 1 privileged instruction error occurred. 6 ptr program exception ? trap 0 trap with successful compare did not occur. 1 trap with successful compare occurred. 7 reserved 8 dst data storage exception ? store fault 0 excepting instruction was not a store. 1 excepting instruction was a store (includes dcbi , dcbz , and dccci ). 9 diz data/instruction storage exception ? zone fault 0 excepting condition was not a zone fault. 1 excepting condition was a zone fault. 10:11 dlk data storage exception ? lock fault 00 no lock exception 01 dcbf unlock exception 10 icbi unlock exception 11 dcbz lock-out exception 12 pau program exception ? auxiliary processor unavailable 0 auxiliary processor unavailable exception did not occur. 1 auxiliary processor unavailable exception occurred. 13 reserved 14 pae program exception ? auxiliary processor enabled 0 auxiliary processor enabled exception did not occur. 1 auxiliary processor enabled exception occurred. 15 reserved 16 dsk data storage exception ? compressed 0 excepting instruction did not access compressed storage. 1 excepting instruction accessed compressed storage. 17:31 reserved 0456 7 mci pil ptr ppr 9 810 dst dlk diz 11 12 13 7 pau 13 14 16 15 31 17 pa e dsk section 11 iop 480 exceptions, interrupts, and timers interrupts iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-19 section 11 ? interrupts 11.7.3.6 data exception address register (dear) the dear is a 32-bit register that contains the address of the access for which one of the following synchronous precise errors occurred ? alignment error, data tlb miss, or data storage exception. the contents of the dear can be written to a gpr using the mfspr instruction. the contents of a gpr can be written to the dear using the mtspr instruction. register 11-8 illustrates the dear bits. 11.7.4 critical interrupt exception an external source requests a critical interrupt by driving the critical interrupt input active. the critical exception is recognized if enabled by msr[ce]. msr[ce] also enables the watchdog timer first- timeout exception. however, the watchdog interrupt has a different exception vector than the critical pin interrupt. see section 11.7.14, ? watchdog timer exception, ? on page 11-27. after detecting a critical interrupt, if no synchronous precise exceptions are outstanding, the iop 480 cpu immediately takes the critical interrupt exception and writes the address of the next instruction to be executed in srr2. simultaneously, the contents of the msr are saved in srr3. msr[ce] is reset to 0 to prevent another critical interrupt or the watchdog timer first timeout exception from interrupting the critical interrupt exception handler before srr2 and srr3 get saved. msr[de] is reset to 0 to disable debug exceptions during the critical interrupt exception handler. the msr is also written with the values shown in table 11-6. the high-order 16 bits of the program counter are then loaded with the contents of the evpr and the low-order 16 bits of the program counter are loaded with 0x0100. exception processing begins at the address in the program counter. inside the exception handling routine, after the contents of srr2/srr3 are saved, critical interrupts can be enabled again by setting msr[ce]=1. executing an rfci instruction restores the program counter from srr2 and the msr from srr3, and execution resumes at the address in the program counter. table 11-5. esr alteration by various exceptions scenario esr 4:6 esr 8:9 program exception w/o mci set to type cleared enabled mci cleared cleared disabled mci, no others unchanged unchanged disabled mci+ program exception set to type cleared table 11-6. register settings during critical interrupt exceptions srr2 written with the address of the next instruction to be executed srr3 written with the contents of the msr msr ape, apa, we, pr, ce, ee, de 0 me unchanged dr, ir 0 ile unchanged le ile pc evpr[0:15] || 0x0100 register 11-8. data exception address register (dear) 0:31 address of data error (synchronous) section 11 interrupts iop 480 exceptions, interrupts, and timers iop 480 data book r2.0 11-20 ? 2000 plx technology, inc. all rights reserved. 11.7.5 machine check exceptions when an external bus error occurs on an instruction fetch, and execution of that instruction is subsequently attempted, a machine check ? instruction exception occurs. when an external bus error occurs while attempting data accesses, a machine check ? data exception occurs. when an instruction-side machine check interrupt occurs, the iop 480 cpu stores the address of the excepting instruction in srr2. when a data-side machine check occurs, the iop 480 cpu stores the address of the next sequential instruction in srr2. simultaneously, for all machine check exceptions, the contents of the msr are loaded into srr3. the msr machine check enable bit (msr[me]) is reset to 0 to disable another machine check from interrupting the machine check exception handling routine. the other msr bits are loaded with the values shown in table 11-7 and table 11-8. the high-order 16 bits of the program counter are then written with the contents of the evpr and the low-order 16 bits of the program counter are written with 0x0200. exception processing begins at the new address in the program counter. executing an rfci instruction restores the program counter from srr2 and the msr from srr3, and execution resumes at the address in the program counter. 11.7.5.1 instruction machine check handling when a machine check occurs on an instruction fetch, and execution of that instruction is subsequently attempted , a machine check ? instruction exception occurs. if enabled by msr[me], the processor reports the machine check ? instruction exception by vectoring to the machine check handler (evpr[0:15] || 0x0200), setting esr[mci]. note that only a bus error can cause a machine check ? instruction exception. taking the vector automatically clears msr[me] and the other msr fields. it is improper to declare a machine check ? instruction exception when the instruction is fetched, because the address is possibly the result of an incorrect speculation by the fetcher. it is quite likely that no attempt will be made to execute an instruction from the erroneous address. the exception occurs only if execution of the instruction is subsequently attempted. when a machine check occurs on an instruction fetch, the erroneous instruction is never written to the instruction cache unit (icu). fetch requests to cacheable memory that miss in the icu cause an instruction cache line fill (four lwords). if any lwords in the fetched line are associated with an error, an exception occurs upon attempted execution and the cache line is invalidated. if any lword in the line is in error, the cache line is invalidated after the line fill. esr[mci] is set, even if msr[me]=0. this means that if a machine check ? instruction exception occurs while running in code in which msr[me] is disabled, the machine check ? instruction exception is recorded in the esr, but no interrupt occurs. software running with msr[me] disabled can sample esr[mci] to determine whether at least one machine check ? instruction exception occurred during the disabled execution. after msr[me] is enabled again, if a new machine check ? instruction exception occurs, it is recorded in esr[mci] and the machine check ? instruction exception handler is invoked. however, enabling msr[me] again does not cause a machine check interrupt to occur simply due to the presence of esr[mci] indicating that a machine check ? instruction exception occurred while msr[me] was disabled. the machine check ? instruction exception must occur while msr[me] is enabled for the machine check interrupt to be taken. software should, in general, clear the esr bits before returning from a machine check interrupt, to avoid any ambiguity when handling subsequent machine check exceptions. table 11-7. register settings during machine check ? instruction exceptions srr2 written with the address that caused the machine check. srr3 written with the contents of the msr msr ape, apa, we, pr, ce, ee, me, de 0 dr, ir 0 ile unchanged le ile pc evpr[0:15] || 0x0200 esr mci 1 section 11 iop 480 exceptions, interrupts, and timers interrupts iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-21 section 11 ? interrupts 11.7.5.2 data machine check handling when a machine check occurs on an data access, a machine check ? data exception occurs. the handling of machine check ? data exceptions is implementation-specific. 11.7.6 data storage exceptions the data storage exception occurs on a cache line locking error or is generated when the desired access to the effective address is not permitted for any of the following reasons: 1. in problem state with data translation enabled a zone fault , which is any user-mode storage access (data load, store, icbi , dcbz , dcbst , or dcbf ) with an effective address with (zpr field)=00. ( dcbt and dcbtst no-op in this situation, rather than cause an exception. the instructions dcbi , dccci , icbt , and iccci , being privileged, cannot cause zone fault data storage exceptions.) data store or dcbz to an effective address with the wr bit clear and (zpr field) 11. (the privileged instructions dcbi and dccci are treated as ? stores ? , but cause privileged program exceptions, rather than data storage exceptions.) 2. in supervisor state with data translation enabled: data store, dcbi , dcbz , or dccci to an effective address with the wr bit clear and (zpr field) other than 11 or 10. note: the icbi , icbt , and iccci instructions are treated as loads from the addressed byte with respect to address translation and protection. instruction cache ops use msr[dr], not msr[ir], to determine translation of their operands. instruction storage exceptions and instruction-side tlb miss exceptions are associated with the fetching of instructions, not with the execution of instructions. data storage exceptions and data tlb miss exceptions are associated with the execution of instruction cache ops. when a data storage exception is detected, the iop 480 cpu suppresses the instruction causing the exception and writes the instruction address in srr0. the data exception address register (dear) is loaded with the data address that caused the access violation. exception syndrome register (esr) bits are loaded as shown in table 11-9 to provide further information about the error. the current contents of the msr are loaded into srr1, and msr bits are then loaded with the values shown in table 11-9. the high-order 16 bits of the program counter are then loaded with the contents of the evpr and the low- order 16 bits of the program counter are loaded with 0x0300. exception processing begins at the new address in the program counter. executing the return from interrupt instruction ( rfi ) restores the contents of the program counter and the msr from srr0 and srr1, respectively. the iop 480 cpu resumes execution at the new program counter address. for instructions that can simultaneously generate program exceptions (privileged instructions executed in problem state) and data storage exceptions, the program exception has priority. table 11-8. register settings during machine check ? data exceptions srr2 written with the address of the next sequential instruction. srr3 written with the contents of the msr msr ape, apa, we, pr, ce, ee, me, de 0 dr, ir 0 ile unchanged le ile pc evpr[0:15] || 0x0200 esr mci 0 section 11 interrupts iop 480 exceptions, interrupts, and timers iop 480 data book r2.0 11-22 ? 2000 plx technology, inc. all rights reserved. the following registers will be modified to the specified values: the cache line locking errors occur when certain cache control instructions attempt to access a cache line, in user mode , when the lock exception bits are enabled in the cache debug control register (cdbcr). the data storage exception occurs regardless of whether the cache line is locked. section 25.5, ? cache line locking, ? on page 25-11, describes cache line locking, including resulting exceptions. the following cache line locking errors occur in user mode: if dcbf attempts to access a cache line while the dcu unlock exception is enabled (cdbcr[duxe]=1). if dcbz references a cacheable address while the dcu lockout exception is enabled (cdbcr[dlxe]=1). an alignment error also occurs; however, in this case, the data storage exception takes priority. if dcbz references a non-cacheable address while the dcu unlock exception is enabled (cdbcr[duxe]=1). an alignment error, which takes priority, also occurs. if icbi attempts to invalidate a locked cache line, while the icu unlock exception is enabled (cdbcr[iuxe]=1). when a data storage exception occurs, the iop 480 cpu suppresses execution of the instruction causing the exception and writes the ea of the instruction address in srr0. the current contents of the msr are saved into srr1. the dear is written with the ea of the failed access. esr[dlk] is set to indicate the cause of the exception. the high-order 16 bits of the program counter are then written with the contents of the evpr and the low- order 16 bits of the program counter are written with 0x0300. exception processing begins at the new address in the program counter. 11.7.7 instruction storage exception the instruction storage exception is generated when instruction translation is active and execution is attempted for an instruction whose fetch access to the effective address is not permitted for any of the following reasons: in problem state instruction fetch from an effective address with (zpr field)=00. instruction fetch from an effective address with the ex bit clear and (zpr field) 11. instruction fetch from an effective address contained within a guarded region (g=1). in supervisor state instruction fetch from an effective address with the ex bit clear and (zpr field) other than 11 or 10. instruction fetch from an effective address contained within a guarded region (g=1). srr0 saves the address of the instruction causing the instruction storage exception. esr is set to indicate the following conditions: if esr[diz]=1, the excepting condition was a zone fault: the attempted execution of an instruction address fetched in user-mode with (zpr field)=00. if esr[diz]=0, then the excepting condition was either ex=0 or g=1. table 11-9. register settings during data storage exceptions srr0 written with the ea of the instruction causing the data storage exception srr1 written with the value of the msr at the time of the exception msr ape, apa, we, pr, ee 0 ce, me, de unchanged dr, ir 0 ile unchanged le ile pc evpr[0:15] || 0x0300 dear written with the ea of the failed access esr the dlk, dst, diz, and dsk fields are set to indicate the cause of the exception. see figure 11-7 on page 11-18 for details of the dlk field. section 11 iop 480 exceptions, interrupts, and timers interrupts iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-23 section 11 ? interrupts the exception is precise with respect to the attempted execution of the instruction. program flow vectors to evpr[0:15] || 0x0400.the following registers are modified to the specified values. 11.7.8 external interrupt exception external interrupt exceptions are triggered by active levels on the external interrupt inputs. all external interrupting events are presented to the processor as a single external interrupt. external interrupts are enabled or disabled by the msr[ee] bit. note: the msr[ee] bit also enables the occurrence of pit and fit interrupts. however, after timer interrupts, control passes to different exception vectors than for the interrupts discussed in the preceding paragraph. therefore, these timer exceptions are described in section 11.7.12, ? programmable interval timer (pit) exception, ? on page 11-26 and section 11.7.13, ? fixed interval timer (fit) exception, ? on page 11-26. 11.7.8.1 external interrupt exception handling when msr[ee]=1 (external interrupts are enabled), and a non-critical external interrupt exception occurs, and this exception is the highest priority exception condition, the processor immediately writes the address of the next sequential instruction into srr0. simultaneously, the contents of the msr are saved in srr1. when the processor takes a non-critical external interrupt, msr[ee] is reset to 0. this disables other external interrupts from interrupting the exception handler before srr0 and srr1 are saved. the msr is also written with the other values shown in table 11-11. the high-order 16 bits of the program counter are written with the contents of the evpr and the low-order 16 bits of the program counter are written with 0x0500. exception processing begins at the address in the program counter. executing an rfi instruction restores the program counter from srr0 and the msr from srr1, and execution resumes at the address in the program counter. table 11-10. register settings during instruction storage exceptions srr0 set to the ea of the instruction for which execute access was not permitted srr1 set to the value of the msr at the time of the exception msr ape, apa, we, pr, ee 0 ce, me, de unchanged dr, ir 0 ile unchanged le ile pc evpr[0:15] || 0x0400 esr notes: diz 1if access failure due to a zone protection fault (zpr[z n ]=00 in user mode) if the diz bit is not set, the exception occurred because tbl_entry[ex] was clear in an otherwise accessible zone or instruction fetch from a storage region marked as guarded. see section 11.7.3.5, ? exception syndrome register (esr), ? on page 11-17 for details of esr operation. table 11-11. register settings during external interrupt exceptions srr0 written with the address of the next sequential instruction srr1 written with the contents of the msr msr ape, apa, we, pr, ee 0 ce, me, de unchanged dr, ir 0 ile unchanged le ile pc evpr[0:15] || 0x0500 section 11 interrupts iop 480 exceptions, interrupts, and timers iop 480 data book r2.0 11-24 ? 2000 plx technology, inc. all rights reserved. 11.7.9 alignment exception alignment exceptions are caused by misaligned data accesses by storage reference instructions, a dcbz instruction to non-cacheable or write through storage, or load/store multiple and string instructions when msr[le]=1 (in powerpc little endian mode). table 11-12 summarizes the instructions and conditions causing alignment exceptions. execution of an instruction causing an alignment exception is prohibited from completing. srr0 is written with the address of that instruction and the current contents of the msr are saved into srr1. the dear is written with the address that caused the alignment error. the msr bits are written with the values shown in table 11-13. the high-order 16 bits of the program counter are written with the contents of the evpr and the low-order 16 bits of the program counter are written with 0x0600. exception processing begins at the new address in the program counter. executing an rfi instruction restores the program counter from srr0 and the msr from srr1, and execution resumes at the address in the program counter note: alignment exceptions cannot be disabled. to avoid overwrites of srr0 and srr1 by alignment exceptions that occur within a handler, exception handlers should save these registers as soon as possible. 11.7.10 program exceptions program exceptions are caused by attempting to execute an illegal operation, by executing a trap instruction with conditions satisfied, or by attempting to execute a privileged instruction while in the problem state. the esr bits that differentiate these situations (refer to table 11-14) are mutually exclusive ? when a program exception occurs, the appropriate bit is set and the others are cleared. these exceptions are not maskable. table 11-12. alignment exception summary iop 480 cpu msr instructions causing alignment exceptions conditions msr[le]=0 dcbz ea in non-cacheable or write-through storage dcread, lwarx, stwcx. ea not lword-aligned msr[le]=1 dcbz ea in non-cacheable or write-through storage lha, lhau, lhaux, lhax, lhbrx, lhz, lhzu, lhzux, lhzx, sth, sthbrx, sthu, sthux, sthx ea not word-aligned dcread, lwarx, lwbrx, lwz, lwzu, lwzux, lwzx, stw, stwbrx, stwcx., stwu, stwux, stwx ea not lword-aligned lmw, lswi, lswx, stmw, stswi, stswx always table 11-13. register settings during alignment error exceptions srr0 written with the address of the instruction causing the alignment exception srr1 written with the contents of the msr msr ape, apa, we, pr, ee 0 ce, me, de, px unchanged dr, ir 0 ile unchanged le ile pc evpr[0:15] || 0x0600 dear written with the address that caused the alignment violation section 11 iop 480 exceptions, interrupts, and timers interrupts iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-25 section 11 ? interrupts the program exception interrupt handler does not need to reset the esr. when execution of an illegal instruction is attempted (including memory management instructions when tie_cpummuen=0 or the apu_cpuexception signal is asserted), or when execution of a privileged instruction is attempted in problem state, the iop 480 cpu does not execute the instruction, and it writes the address of the excepting instruction into srr0. trap instructions can be used as a program exception or a debug event, or both (refer to section 26, ? iop 480 cpu debugging and jtag facilities, ? for information about debug events). when a trap instruction is detected as a program exception, the iop 480 cpu writes the address of the trap instruction into srr0. see tw on page 28-163 and twi on page 28-166 for a detailed discussion of the behavior of trap instructions with various exceptions enabled. if msr[apa]=0, an attempt to execute an instruction intended for an auxiliary processor unit (apu) causes a program exception if msr[ape]=0 or the apu_cpuexception signal is asserted. after any program exception, the contents of the msr are written into srr1 and the msr bits are written with the values shown in table 11-15. the high-order 16 bits of the program counter are written with the contents of the evpr; the low-order 16 bits of the program counter are written with 0x0700. exception processing begins at the new address in the program counter. executing an rfi instruction restores the program counter from srr0 and the msr from srr1, and execution resumes at the address in the program counter. 11.7.11 system call exception system call exceptions occur when a sc instruction is executed. the iop 480 cpu writes the address of the instruction following the sc into srr0. the contents of the msr are written into srr1 and the msr bits are written with the values shown in table 11-16. the high-order 16 bits of the program counter are then written with the contents of the evpr and the low-order 16 bits of the program counter are written with 0x0c00. exception processing begins at the new address in the program counter. executing an rfi instruction restores the program counter from srr0 and the msr from srr1, and execution resumes at the address in the program counter. table 11-14. esr usage for program exceptions bit exception cause esr[pil] illegal esr[ppr] privileged esr[ptr] trap esr[pau] auxiliary processor unavailable esr[pae] auxiliary processor exception table 11-15. register settings during program exceptions srr0 written with the address of the excepting instruction srr1 written with the contents of the msr msr we, pr, ee 0 ce, me, de unchanged dr, ir 0 ile unchanged le ile pc evpr[0:15] || 0x0700 esr written with the type of program exception (refer to table 11-5 on page 11-19 and table 11-14 on page 11-25) table 11-16. register settings during system call exceptions srr0 written with the address of the instruction following the sc instruction srr1 written with the contents of the msr msr ape, apa, we, pr, ee 0 ce, me, de unchanged dr, ir 0 ile unchanged le ile pc evpr[0:15] || 0x0c00 section 11 interrupts iop 480 exceptions, interrupts, and timers iop 480 data book r2.0 11-26 ? 2000 plx technology, inc. all rights reserved. 11.7.12 programmable interval timer (pit) exception for a discussion of the iop 480 cpu timer facilities, see section 11.7.18, ? timer facilities, ? on page 11-28. the pit is described in section 11.7.18.2, ? programmable interval timer (pit), ? on page 11-32. if the pit exception is enabled by tcr[pie] and msr[ee], the iop 480 cpu initiates a pit interrupt after detecting a timeout from the pit. timeout is detected when, at the beginning of a clock cycle, tsr[pis]=1. (this occurs on the cycle after the pit decrements on a pit count of 1.) the iop 480 cpu immediately takes the interrupt. the address of the next sequential instruction is saved in srr0; simultaneously, the contents of the msr are written into srr1 and the msr is written with the values shown in table 11-17. the high-order 16 bits of the program counter are then written with the contents of the evpr and the low-order 16 bits of the program counter are written with 0x1000. exception processing begins at the address in the program counter. to clear a pit interrupt, the exception handling routine must clear the pit interrupt bit, tsr[pis]. clearing is performed by writing an lword to tsr, using an mtspr instruction, that has 1 in bit positions to be cleared and 0 in all other bit positions. the data written to the tsr is not direct data, but a mask; a 1 clears the bit and 0 has no effect. executing an rfi instruction restores the program counter from srr0 and the msr from srr1, and execution resumes at the address in the program counter. 11.7.13 fixed interval timer (fit) exception for a discussion of the iop 480 cpu timer facilities, see section 11.7.18, ? timer facilities, ? on page 11-28. the fit is described in section 11.7.18.3, ? fixed interval timer (fit), ? on page 11-33. if the fit exception is enabled by tcr[fie] and msr[ee], the iop 480 cpu initiates a fit interrupt after detecting a timeout from the fit. timeout is detected when, at the beginning of a clock cycle, tsr[fis]=1. (this occurs on the second cycle after the 0 1 transition of the appropriate time-base bit.) the iop 480 cpu immediately takes the interrupt. the address of the next sequential instruction is written into srr0; simultaneously, the contents of the msr are written into srr1 and the msr is written with the values shown in table 11-18. the high-order 16 bits of the program counter are then written with the contents of the evpr and the low-order 16 bits of the program counter are written with 0x1010. exception processing begins at the address in the program counter. to clear a fit interrupt, the exception handling routine must clear the fit interrupt bit, tsr[fis]. clearing is performed by writing an lword to tsr, using an mtspr instruction, that has 1 in any bit positions to be cleared and 0 in all other bit positions. the data written to the tsr is not direct data, but a mask; a 1 clears a bit and 0 has no effect. executing an rfi instruction restores the program counter from srr0 and the msr from srr1, and execution resumes at the address in the program counter. table 11-17. register settings during programmable interval timer exceptions srr0 written with the address of the next instruction to be executed srr1 written with the contents of the msr msr ape, apa, we, pr, ee 0 ce, me, de unchanged dr, ir 0 ile unchanged le ile pc evpr[0:15] || 0x1000 tsr pis 1 table 11-18. register settings during fixed interval timer exceptions srr0 written with the address of the next sequential instruction srr1 written with the contents of the msr msr ape, apa, we, pr, ee 0 ce, me, de unchanged dr, ir 0 ile unchanged le ile pc evpr[0:15] || 0x1010 tsr fis 1 section 11 iop 480 exceptions, interrupts, and timers interrupts iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-27 section 11 ? interrupts 11.7.14 watchdog timer exception for a general description of the iop 480 cpu timer facilities, see section 11.7.18, ? timer facilities, ? on page 11-28. the watchdog timer (wdt) is described in section 11.7.18.4, ? watchdog timer, ? on page 11-33. if the wdt exception is enabled by tcr[wie] and msr[ce], the iop 480 cpu initiates a wdt interrupt after detecting the first wdt timeout. first timeout is detected when, at the beginning of a clock cycle, tsr[wis]=1. (this occurs on the second cycle after the 0 1 transition of the appropriate time-base bit while tsr[enw]=1 and tsr[wis]=0.) the iop 480 cpu immediately takes the interrupt. the address of the next sequential instruction is saved in srr2; simultaneously, the contents of the msr are written into srr3 and the msr is written with the values shown in table 11-19. the high-order 16 bits of the program counter are then written with the contents of the evpr and the low-order 16 bits of the program counter are written with 0x1020. exception processing begins at the address in the program counter. to clear the wdt interrupt, the exception handling routine must clear the wdt interrupt bit tsr[wis]. clearing is done by writing an lword to tsr (using mtspr ), with a 1 in any bit position that is to be cleared and 0 in all other bit positions. the data written to the status register is not direct data, but a mask; a 1 causes the bit to be cleared, and a 0 has no effect. executing the return from critical interrupt instruction ( rfci ) restores the contents of the program counter and the msr from srr2 and srr3, respectively, and the iop 480 cpu resumes execution at the contents of the program counter. 11.7.15 data tlb miss exception the data tlb miss exception is generated if data translation is enabled and a valid tlb entry matching the ea and pid is not present. the address of the instruction generating the untranslatable effective data address is saved in srr0. in addition, the hardware also saves the data address (that missed in the tlb) in the dear. the esr is set to indicate whether the excepting operation was a store (includes dcbz , dcbi , dccci ). the exception is precise. program flow vectors to evpr[0:15] || 0x1100. the following registers are modified to the specified values. note: data tlb miss exceptions can happen whenever data translation is active. therefore, ensure that srr0 and srr1 are saved before enabling translation in an exception handler. 11.7.16 instruction tlb miss exception the instruction tlb miss exception is generated if instruction translation is enabled and execution is attempted for an instruction for which a valid tlb entry matching the ea and pid for the instruction fetch is not present. the instruction whose fetch caused the tlb miss is saved in srr0. the exception is precise with respect to the attempted execution of the instruction. program flow vectors to evpr[0:15 || 0x1200. table 11-19. register settings during watchdog timer exceptions srr2 written with the address of the next sequential instruction srr3 written with the contents of the msr msr ape, apa, we, pr, ce, ee, de 0 me unchanged dr, ir 0 ile unchanged le ile pc evpr[0:15] || 0x1020 tsr wis 1 table 11-20. register settings during data tlb miss exceptions srr0 set to the address of the instruction generating the effective address for which no valid translation exists. srr1 set to the value of the msr at the time of the exception msr ape, apa, we, pr, ee, pe 0 ce, me, de, px unchanged dr, ir 0 ile unchanged le ile pc evpr[0:15] || 0x1100 dear set to the effective address of the failed access esr dst 1 if excepting operation is a store operation (includes dcbi , dcbz , and dccci ). see section 11.7.3.5, ? exception syndrome register (esr), ? on page 11-17 for details of esr operation. section 11 interrupts iop 480 exceptions, interrupts, and timers iop 480 data book r2.0 11-28 ? 2000 plx technology, inc. all rights reserved. the following registers are modified to the specified values. note: instruction tlb miss exceptions can happen any time instruction translation is active. therefore, insure that srr0 and srr1 are saved before enabling translation in an exception handler. 11.7.17 debug exception handling debug exceptions can be either synchronous or asynchronous . the following debug events generate synchronous exceptions: instruction address compare (also referred to as iac), data address compare (also referred to as dac), trap with condition satisfied (tie), branch taken (bt), and instruction completion (ic). the following debug events generate asynchronous exceptions: unconditional debug event (ude) and exceptions (exc). see section 26, ? iop 480 cpu debugging and jtag facilities, ? for more information about debug events. for debug events, srr2 is written with an address, which varies with the type of debug event, as shown in table 11-22. srr3 is written with the contents of the msr and the msr is written with the values shown in table 11-23. the high-order 16 bits of the program counter are then written with the contents of the evpr; the low-order 16 bits of the program counter are written with 0x2000. exception processing begins at the address in the program counter. executing an rfci instruction restores the program counter from srr2 and the msr from srr3, and execution resumes at the address in the program counter. 11.7.18 timer facilities the iop 480 cpu provides four timer facilities: a time base, a programmable interval timer (pit), a fixed interval timer (fit), and a watchdog timer (wdt). these facilities, which share the same base clock frequency, can support: time-of-day functions data logging functions peripherals requiring periodic schedule service general system maintenance additionally, the timer facilities can help a system recover from faulty hardware or software. figure 11-3 on page 11-30 shows the relationship of these facilities and base clock. the time base of the iop 480 cpu is functionally similar to the time base defined in powerpc architecture, but the two are not the same. descriptions of the difference, as an aid to porting code, follow. table 11-21. register settings during instruction tlb miss exceptions srr0 set to the address of the instruction for which no valid translation exists. srr1 set to the value of the msr at the time of the exception msr ape, apa, we, pr, ee, pe 0 ce, me, de, px unchanged dr, ir 0 ile unchanged le ile pc evpr[0:15] || 0x1200 table 11-22. srr2 during debug exceptions debug event address saved in srr2 iac dac tde bt address of the instruction that caused the event ic address of the instruction following the instruction that caused the event ude address of next instruction to be executed at time of ude ede interrupt vector address of the initial exception that caused the exception debug event table 11-23. register settings during debug exceptions srr2 written with an address as described in table 11-22 srr3 written with the contents of the msr msr ape, apa, we, pr, ce, ee, de 0 me unchanged dr, ir 0 ile unchanged le ile pc evpr[0:15] || 0x2000 dbsr set to indicate type of debug event. section 11 iop 480 exceptions, interrupts, and timers interrupts iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-29 section 11 ? interrupts for powerpc architecture: the powerpc architecture defines a 64-bit time base that can be accessed as a pair of 32-bit registers. different register numbers are used for read access (user or privileged mode) and write access (privileged mode). the powerpc architecture provides a mftb (move from time base) instruction for user-mode read access to the time base. the register numbers (0x10c and 0x10d) used to specify the time base registers are not spr numbers. however, the opcode of mftb differs from the opcode of mfspr by only one bit. the powerpc architecture allows an implementation to ignore this bit and handle mftb as mfspr . therefore, the time base register numbers cannot specify other sprs. further, powerpc compilers can use the mftb opcode only with the register numbers specified in the powerpc architecture as read-access time base registers (0x10c and 0x10d). the powerpc architecture does not provide privileged-mode-only read access to the time base (by definition, the user-mode read access mechanism is also available in privileged mode). the powerpc architecture provides privileged- mode write access to the time base using mtspr with spr numbers 0x11c and 0x11d. for the iop 480 cpu: iop 480 cpu defines a 64-bit time base that can be accessed as a pair of 32-bit registers. different register numbers are used for read access (user or privileged mode) and write access (privileged mode). the iop 480 cpu also allows read access (in privileged mode only) using the same register number as a write access. iop 480 cpu provides user-mode and privileged- mode read access to the time base using mfspr with spr numbers 0x3cd and 0x3cc. the iop 480 cpu provides privileged-mode-only read access via mfspr instructions with spr numbers 0x3dd and 0x3dc. the iop 480 cpu does not implement mftb ; an attempt to use it results in a program exception caused by the ? illegal ? opcode. iop 480 cpu provides privileged-mode write access to the time base using mtspr instructions with spr numbers 0x3dd and 0x3dc. table 11-24 on page 11-31 summarizes the differences between the time bases. section 11 interrupts iop 480 exceptions, interrupts, and timers iop 480 data book r2.0 11-30 ? 2000 plx technology, inc. all rights reserved. figure 11-3. relationship of timer facilities to the base clock 11.7.18.1 time base the iop 480 cpu implements a 64-bit time base. the time base, which increments once during each period of the time base clock, provides a time reference. the time base is accessed using the 32-bit registers tblo and tbhi. software access to the time base is through the mfspr and mtspr instructions. access to the time base registers tbhi and tblo is privileged. user-mode read-only access to the time base is provided by reading from different spr numbers. specifically, read-only access to tbhi is accomplished by reading tbhu, and read-only access to tblo is accomplished by reading tblu. both tbhu and tblu are read using mfspr instructions. an mtspr to these registers is boundedly undefined. the period of the 64-bit time base is approximately 7794 years for a 75 mhz time base clock. the time base does not generate interrupts, even when it wraps. for most applications, the time base is set at system reset and only read thereafter. note that the fit and the watchdog timer (discussed below) are driven by 0 1 transitions of selected bits of tblo. transitions caused by software alteration of tblo, using mtspr, have the same effect as transitions caused by normal incrementing of the time base. register 11-9 illustrates tbhi(tbhu); register 11-10 illustrates tblo(tblu). tbhi (32 bits) bit 15 (2 17 clocks) bit 11 (2 21 clocks) bit 7 (2 25 clocks) bit 3 (2 29 clocks) bit 23 (2 9 clocks) bit 19 (2 13 clocks) bit 15 (2 17 clocks) bit 11 (2 21 clocks) wdt events fit events time base (incrementer) 0 tblo (32 bits) 0 31 31 pit (decrementer) (32 bits) 0 31 zero detect pit events external clock source section 11 iop 480 exceptions, interrupts, and timers interrupts iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-31 section 11 ? interrupts register 11-9. time base register (tbhi, tbhu) 0:31 time high current count, high-order. note: tbhu provides read-only access to the time base register tbhi. the contents of tbhu and tbhi never differ). register 11-10. time base register (tblo, tblu) 0:31 time low current count, low-order. note: tblu provides read-only access to the time base register tblo. the contents of tblu and tblo never differ). table 11-24. time base comparison powerpc architecture iop 480 cpu access instructions register number access restrictions access instructions register number access restrictions upper 32 bits mftbu rt extended mnemonic for mftb rt,tbu 0x10d read-only mftbhu rt extended mnemonic fo r mfspr rt tbhu 0x3cc read-only mttbu rs extended mnemonic for mtspr tbu,rs 0x11d privileged; write-only mftbhi rt extended mnemonic for mfspr rt,tbhi mttbhi rs extended mnemonic for mtspr tbhi,rs 0x3dc privileged; read privileged; write lower 32 bits mftb rt extended mnemonic for mftb rt,tbl 0x10c read-only mftblu rt extended mnemonic for mfspr rt,tblu 0x3cd read-only mttbl extended mnemonic for mtspr tbl,rs 0x11c privileged; write-only mftblo rt extended mnemonic for mfspr rt,tblo mttblo rs extended mnemonic for mtspr tblo,rs 0x3dd privileged; read privileged; write section 11 interrupts iop 480 exceptions, interrupts, and timers iop 480 data book r2.0 11-32 ? 2000 plx technology, inc. all rights reserved. 11.7.18.2 programmable interval timer (pit) the pit is a 32-bit register that decrements at the same rate as the time base. the pit is read or written using mfspr or mtspr . writing to the pit, using mtspr, simultaneously writes to a hidden reload register. reading the pit using mfspr returns the current pit contents; the hidden reload register cannot be read. when a non-zero value is written to the pit, it begins to decrement. a pit event occurs when a decrement occurs on a pit count of 1. when a pit event occurs, the following occur: 1. if the pit is in auto-reload mode (tcr[are]=1), the pit is loaded with the last value an mtspr wrote to the pit. a decrement from a pit count of 1 immediately causes a reload; no intermediate pit content of 0 occurs. if the pit is not in auto-reload mode (tcr[are]=0), a decrement from a pit count of simply causes a pit content of 0. 2. tsr[pis] is set to 1. 3. if enabled (tcr[pie]=1 and msr[ee]=1), a pit interrupt is taken. see section 11.7.12, ? programmable interval timer (pit) exception, ? on page 11-26, for details of register behavior during a pit interrupt. the interrupt handler should use software to reset the tsr[pis] bit. this is done by using mtspr to write an lword to the tsr having a 1 in tsr[pis] and any other bits to be cleared, and a 0 in all other bits. the data written to the tsr is not direct data, but a mask. a 1 clears a bit; a 0 has no effect. using mtspr to force the pit to 0 does not cause a pit interrupt. however, decrementing that was ongoing at the instant of the mtspr instruction can cause the appearance of an interrupt. to eliminate the pit as a source of interrupts, write a 0 to tcr[pie], the pit interrupt enable bit. to eliminate all pit activity: 1. write a 0 to tcr[pie]. this prevents pit activity from causing interrupts. 2. write a 0 to tcr[are]. this disables the pit auto-reload feature. 3. write zeroes to the pit to halt pit decrementing. although this action does not cause a pit interrupt to become pending, a near-simultaneous decrement might have done so. 4. write a 1 to tsr[pis] (pit interrupt status bit). this clears tsr[pis] to 0 (refer to section 11.7.18.5, ? timer status register (tsr), ? on page 11-35). this also clears any pending pit interrupt. because the pit freezes, no further pit events are possible. if the auto-reload feature is disabled (tcr[are]=0) after the pit decrements to 0, the pit remains 0 until software uses mtspr to reload it. on all resets, tcr[are]=0, which disables the auto-reload feature. register 11-11 lists the pit bits. register 11-11. programmable interval timer (pit) 0:31 programmed interval remaining the number of clocks remaining until the pit event section 11 iop 480 exceptions, interrupts, and timers interrupts iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-33 section 11 ? interrupts 11.7.18.3 fixed interval timer (fit) the fit provides timer interrupts having a repeatable period, facilitating system maintenance. the fit is functionally similar to an auto-reload pit, except that fewer selections of interrupt periods are available. the fit exception occurs on 0 1 transitions of selected bits from the time base, as shown in table 11-25. the tsr[fis] bit logs a fit exception as a pending interrupt. a fit interrupt occurs if tcr[fie] and msr[ee] are enabled at the time of the fit exception. section 11.7.13, ? fixed interval timer (fit) exception, ? on page 11-26, describes register behavior during a fit interrupt. the interrupt handler must use software to reset the tsr[fis] bit. this is done by using mtspr to write an lword to the tsr having a 1 in tsr[fis] and any other bits to be cleared, and a 0 in all other bits. the data written to the tsr is not direct data, but a mask. a 1 clears a bit and a 0 has no effect. 11.7.18.4 watchdog timer the watchdog timer (wdt) aids system recovery from software or hardware faults. a wdt timeout occurs on 0 1 transitions of selected bits from the time base, as shown in table 11-26. if a wdt timeout occurs while tsr[wis]=0 and tsr[enw]=1, a wdt interrupt occurs if the interrupt is enabled by tcr[wie] and msr[ce]. section 11.7.14, ? watchdog timer exception, ? on page 11-27 describes register behavior during a wdt interrupt. the interrupt handler must use software to reset the tsr[wis] bit. this is done by using mtspr to write an lword to the tsr having a 1 in tsr[wis] and any other bits to be cleared, and a 0 in all other bits. the data written to the tsr is not direct data, but a mask. a 1 clears a bit and a 0 has no effect. if a wdt timeout occurs while tsr[wis]=1 and tsr[enw]=1, a hardware reset occurs if enabled by a non-zero value of tcr[wrc]. the assumption is that tsr[wis] was not cleared because the processor could not execute the watchdog handler, leaving reset as the only way to restart the system. note that after tcr[wrc] is set to a non-zero value, it cannot be reset by software. this prevents errant software from disabling the wdt reset capability. figure 11-4 and table 11-27 describe the watchdog state machine. in the figure, numbers in parentheses refer to descriptions of operating modes that follow the table. table 11-25. fit controls tcr[fp] tblo bit period (time base clocks) period (66 mhz clock) 0, 0 23 2 9 clocks 7.68 s 0, 1 19 2 13 clocks 122.9 s 1, 0 15 2 17 clocks 1.966 ms 1, 1 11 2 21 clocks 31.46 ms table 11-26. watchdog timer controls tcr[wp] tblo bit period (time base clocks) period (66 mhz clock) 0,0 15 2 17 clocks 1.966 ms 0,1 11 2 21 clocks 31.46 ms 1,0 7 2 25 clocks 0.503s 1,1 3 2 29 clocks 8.053s section 11 interrupts iop 480 exceptions, interrupts, and timers iop 480 data book r2.0 11-34 ? 2000 plx technology, inc. all rights reserved. figure 11-4. watchdog timer state machine the controls described in the above table imply three different operating modes that a programmer can select for the wdt. the modes assume that tcr[wrc] was set to allow processor reset by the wdt: 1. always take a pending wdt interrupt, and never attempt to prevent its occurrence. (this mode is described in the preceding text.) clear tsr[wis] in the wdt handler. never use tsr[enw]. 2. always take a pending wdt interrupt, but avoid it whenever possible. this assumes that a recurring code loop of reliable duration exists outside the interrupt handlers, or that a fit interrupt handler is operational. one of these mechanisms clears tsr[enw] more frequently than the watchdog period. clear tsr[enw] to 0 in loop or in fit handler. to clear tsr[enw], use mtspr to write a 1 to tsr[enw] (and to any other bits that are to be cleared), with 0 in all other bit locations. clear tsr[wis] in wdt handler. (this is an unexpected event.) 3. never take a wdt interrupt. this assumes that a recurring code loop of reliable duration exists outside the interrupt handlers, or that a fit interrupt handler is operational. this method guarantees only one wdt period before a reset occurs. clear tsr[wis] in the loop or in fit handler. never use tsr[enw]. enw,wis=0,0 enw,wis=0,1 enw,wis=1,0 enw,wis=1,1 timeout, no interrupt timeout, wdt interrupt timeout, no interrupt timeout (2) sw loop (3) sw loop (1) interrupt handler (2) interrupt handler if wrc 00, then { reset, including wrs wrc wrc 00 } occurs if enabled table 11-27. watchdog timer state machine enable next wdt tsr[enw] wdt status tsr[wis] action when timer interval expires 00 set enable next watchdog (tsr[enw]=1). 01 set tsr[enw]=1. 10 set the watchdog interrupt status (tsr[wis]=1). if tcr[wie]=1 and msr[ce]=1, then interrupt. 11 cause the watchdog reset action specified by tcr[wrc]. on reset, copy pre-reset tcr[wrc] into tsr[wrs] and clear tcr[wrc]. section 11 iop 480 exceptions, interrupts, and timers interrupts iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 11-35 section 11 ? interrupts 11.7.18.5 timer status register (tsr) the tsr can be accessed for read or write-to-clear. status registers are generally set by hardware and read and cleared by software. the mfspr instruction reads the tsr. clearing the tsr is performed by writing an lword to the tsr, using mtspr, having a 1 in all bit positions to be cleared and a 0 in all other bit positions. the data written to the tsr is not direct data, but a mask. a 1 clears the bit and a 0 has no effect. register 11-12 illustrates the tsr bits. register 11-12. timer status register (tsr) 0 enw enable next watchdog 0 action on next watchdog event is to set tsr[0]. 1 action on next watchdog event is governed by tsr[1]. see section 11.7.18.4, ? watchdog timer, ? on page 11-33. 1 wis watchdog interrupt status 0 no watchdog interrupt is pending. 1 watchdog interrupt is pending. 2:3 wrs watchdog reset status 00 no watchdog reset has occurred. 01 core reset was forced by the watchdog. 10 chip reset was forced by the watchdog. 11 system reset was forced by the watchdog. 4 pis pit interrupt status 0 no pit interrupt is pending. 1 pit interrupt is pending. 5 fis fit interrupt status 0 no fit interrupt is pending. 1 fit interrupt is pending. 6:31 reserved 012345 31 enw wrs fis pis wis 6 section 11 interrupts iop 480 exceptions, interrupts, and timers iop 480 data book r2.0 11-36 ? 2000 plx technology, inc. all rights reserved. 11.7.18.6 timer control register (tcr) the tcr controls pit, fit, and wdt operation. the tcr[wrc] field is cleared to 0 by all processor resets. (section , ? this subsection describes the initial state of the iop 480 cpu after a reset, and contains an example of the initialization code required to begin executing application code. initialization of external system components or system-specific chip facilities may also need to be performed in addition to the basic initialization described in this section., ? on page 10-8, describes the types of processor reset.) this field is set only by software. however, hardware does not allow software to clear the field after it is set. after software writes a 1 to a bit in the field, that bit remains a 1 until any reset occurs. this prevents errant code from disabling the wdt reset function. all processor resets clear tcr[are] to 0, disabling the auto-reload feature of the pit. register 11-13 illustrates the tcr bits. register 11-13. timer control register (tcr) 0:1 wp watchdog period 00 2 17 clocks 01 2 21 clocks 10 2 25 clocks 11 2 29 clocks 2:3 wrc watchdog reset control 00 no watchdog reset occurs. 01 core reset is forced by the watchdog. 10 chip reset is forced by the watchdog. 11 system reset is forced by the watchdog. tcr[wrc] resets to 00. this field can be set by software, but cannot be cleared by software, except by a software-induced reset. 4 wie watchdog interrupt enable 0 disable wdt interrupt. 1 enable wdt interrupt. 5 pie pit interrupt enable 0 disable pit interrupt. 1 enable pit interrupt. 6:7 fp fit period 00 2 9 clocks 01 2 13 clocks 10 2 17 clocks 11 2 21 clocks 8 fie fit interrupt enable 0 disable fit interrupt. 1 enable fit interrupt. 9 are auto reload enable 0 disable auto reload. 1 enable auto reload. disables on reset. 10:31 reserved 012345678 9 31 wp wie fp fie pie wrc 10 are iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-1 section 12 ? memory ctrlr 12 memory controller 12.1 overview the iop 480 memory controller supports up to four banks of sram by using lcs[3:0]# signals and up to four banks of either extended data out (edo) dram or synchronous dram (sdram) by using mcs[3:0]# signals. the sram banks (lcs[3:0]# signals) can also be used to access proms, i/o peripheral chips, flash memory, parallel eeproms, and fifo. four different masters can access these banks of memory and peripherals. each of these masters have 32-bit-wide data buses: direct slave controller internal dma channels 0, 1, and 2 internal iop 480 cpu local bus master when an address on the local bus falls into the programmed range of one of the sram or dram banks, the memory controller accesses the appropriate device. either single or burst accesses are supported. if a local address does not match any of the programmed ranges, nor does it fall into the direct master or configuration register ranges, then a default bus descriptor register is used to define the characteristics of the bus. this register is used when the iop 480 is accessing a general-purpose device on the local bus that is not controlled by an sram or dram register. sram banks have individual sets of configuration registers that define base address, size, and bus characteristics. all four dram banks use one additional set of configuration registers. the bus width of the sram banks can be 8, 16, or 32 bits, while the bus width of all four dram banks must be 32 bits. figure 12-1. memory block diagram pci dma iop 480 cpu local bus interface memory controller memory bank (dram) local bus master internal control bus parameters addr/data bus local control bus addr/data bus memory bank (sram) iop 480 external devices section 12 memory controller sram iop 480 data book r2.0 12-2 ? 2000 plx technology, inc. all rights reserved. 12.2 sram sram banks can be used for accesses to sram, prom, external asynchronous fifos, or i/o peripheral devices. 12.2.1 control signals minimum size of each sram bank is 256 bytes. the following address, data, and control signals are used to access an sram device. each unique application does not necessarily use all of the following signals, but only those required by the application. 12.2.2 address the local address bus is de-multiplexed by the memory controller to produce address bits [19:2] to memory. for devices which use more than 20 address bits (1 mb), lad[31:20] must be de-multiplexed in an external latch controlled by ale. the address connections to various widths of memory devices are shown below. a[19:0] represent address pins on the memory device. the local byte enables are used to provide the least significant de-multiplexed address bits. 12.2.3 parity checking even or odd parity is generated for each byte on the local data bus. while data is being read from sram, parity is checked if it is enabled in the corresponding configuration register. when the iop 480 is the local bus master, the bus width determines which bytes are checked for parity. when an external master controls the local bus, the lbe[3:0]# signals determine which bytes are checked for parity. parity errors can be programmed to cause an interrupt. 12.2.4 boot prom after a reset, the registers for lcs0# default to settings which allow the internal iop 480 cpu to boot from an external 8-bit eprom on the local bus. the eprom must use lcs0# as its chip select. table 12-1. sram signals source signal description memory controller ma[12:0] de-multiplexed address bits [14:2] dp[3:0]/ma[16:13] de-multiplexed address bits [18:15] or parity bits lcs3#/ma17 de-multiplexed address bit 19 or lcs3# moe# memory output enable lcs[2:0]# local chip selects mdqm[3:0]# byte write signals rd# read strobe mwe# write strobe local bus lad[31:0] address/data bus (lad0 is least significant) lbe[3:0]# byte enables; also used as address bits [1:0] ale address latch enable lwr# write/read status table 12-2. local burst address device width device address la[19:2] la1 la0 8 bits ma[17:0] lbe1# lbe0# 16 bits ma[17:0] lbe1# not used 32 bits ma[17:0] not used not used section 12 sram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-3 section 12 ? memory ctrlr 12.2.5 sram examples figure 12-2 and figure 12-3 illustrate examples of sram devices (two 64k x 16 and four 256k x 8 devices, respectively). 12.2.6 sram write access an sram write access is started when ads# is asserted, lwr# is high, and the address falls into the appropriate range. if the iop 480 is controlling the access, the multiplexed address/data bus, lad[19:2], is loaded into the ma[17:0] counter at the end of the period in which ads# is asserted. if an external local bus master is controlling the access, the multiplexed address/data bus, lad[19:2], is loaded into the ma[17:0] counter at the end of the period in which ads# is asserted. after each transfer, ma[17:0] is incremented, thus pointing to the next 32-bit word. the moe# signal is connected to the oe# input of the srams, and disables the output drivers during a write access. burst accesses are not permitted to cross a 32 kb page boundary if the internal burst address is being used. if an external address counter is used, the bterm# input can be used to terminate a burst when a page boundary is reached. five types of programmable timing parameters are associated with sram write accesses, as illustrated in table 12-3 on page 12-5. as each word is written to memory, the memory controller generates an internal ready signal, memrdy#, which signals the internal local bus controller that the transfer has occurred. memrdy# is based on the internal wait state generator, and is driven out onto the ready# pin when the ready# input pin is disabled in the configuration registers. if the ready/recover mode bit is set in the bus region descriptor register, then the ready# pin is also driven during the recovery states. this can be used by an external local bus master to delay the start of the next access until the recovery period expires. if dram and page mode are enabled, the memory controller does not assert cas_mdqm[3:0]# during sram accesses. the we# inputs in figure 12-3 would need to be implemented in external logic. if dram is also being used on the local bus, refresh accesses can cause an sram access to be delayed. this is a result of the sharing of memory controller pins between sram and dram. the timing parameter values shown at the top of each timing diagram refer to delay clock periods. this is not necessarily the value written to the corresponding field in the dramtim register. the dramtim register description details the mapping between the value written and resulting number of delay clock periods. section 12 memory controller sram iop 480 data book r2.0 12-4 ? 2000 plx technology, inc. all rights reserved. figure 12-2. sram (two 64k x 16 devices) figure 12-3. sram (four 256k x 8 devices) iop 480 lad ma[17:0] lbe0# lbe1# lbe2# lbe3# lcsn# moe# mwe# addr cs# oe# we# lb# ub# sram (64kx16) data addr cs# oe# we# lb# ub# sram (64kx16) data iop 480 lad ma[17:0] cs# oe# we# sram 256kx8 data addr addr cs# oe# we# sram 256kx8 data addr cs# oe# we# sram 256kx8 data addr cs# oe# we# sram 256kx8 data mdqm0# mdqm1# mdqm2# mdqm3# lcsn# moe# lbe[1:0]# section 12 sram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-5 section 12 ? memory ctrlr figure 12-4. flash (one 8-bit device) table 12-3. sram write access programmable timing parameters field description wad number of write address-to-data wait states (0-15). determines number of wait states for a single transfer, or for the first word of a burst transfer. in cases where the memory being accessed has some start-up latency associated with it, this number is set larger than data-to-data wait states. wdd number of write data-to-data wait states (0-15). determines the number of wait states between burst data transfers. when this value is set to 0, data is transferred on every clock access if wdly and whld are set to 0. wdly number of write enable delay states (0-7). determines the delay from the assertion of the chip select until the write enables are first asserted. it also determines the delay from ready# to the re-assertion of the write enables during a burst access. when this value is set to 0, write strobes are asserted one-half clock period after chip select for external bus masters, and 1.5 clocks after the chip select when the iop 480 is the local bus master. if this field is set to a non- zero value, then wad and wdd values must be set larger to accommodate the write strobe delay. this field does not cause wait states to be automatically added. whld number of write hold states (0-7). determines the number of hold states after the write enables have been de-asserted. during this period, address, data, and read/write signals are held stable. this field causes wait states to be added automatically, as well as those specified in wad and wdd fields. wrcv number of write recovery states (1-8). determines the number of recovery states after a single write transfer or last data transfer of a burst. lad[7:0] ma[16:0] lbe[1:0]# lcs[0]# moe# mwe# addr[18:2] data[7:0] addr[1:0] ce# oe# we# flash (512kx8) iop 480 section 12 memory controller sram iop 480 data book r2.0 12-6 ? 2000 plx technology, inc. all rights reserved. timing diagram 12-1. sram burst write, 32-bit bus; wad=0, wdd=0, wdly=0, whld=0, wrcv=0; master=iop 480 timing diagram 12-2. sram burst write, 32-bit bus, 2-1-1-1 wait states, 2 recovery states; wad=2, wdd=1, wdly=0, whld=1, wrcv=2; lcs x brd [19]=1; master=iop 480 addr d0 d1 d2 d3 a0 a1 a2 a3 0ns 25ns 50ns 75ns 100n s lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[17:0] lcsn# mdqm[3:0]# mwe# blast# memrdy# (internal) addr d0 d1 d2 d3 addr f 0 0 a0 a1 a2 a3 a0 f 0 f 0 f 0 f 0 f 0ns 100ns 200ns 300n s lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[17:0] lcsn# mdqm[3:0]# mwe# blast# memrdy# (internal) section 12 sram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-7 section 12 ? memory ctrlr l timing diagram 12-3. sram burst write, 32-bit bus, 2-1-1-1 wait states, 1 write enable delay; wad=2, wdd=1, wdly=1, whld=1, wrcv=0; master=iop 480 timing diagram 12-4. sram burst write, 32-bit bus, 1 write hold delay; wad=1, wdd=0, wdly=0, whld=1, wrcv=0; master=iop 480 addr d0 d1 d2 d3 f 0 a0 a1 a2 a3 f 0 f 0 f 0 f 0 f 0ns 50ns 100ns 150ns 200ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[17:0] lcsn# mdqm[3:0]# mwe# blast# memrdy (internal) addr d0 d1 d2 d3 a0 a1 a2 a3 0ns 50ns 100ns 150ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[17:0] lcsn# mdqm[3:0]# mwe# blast# memrdy# (internal) section 12 memory controller sram iop 480 data book r2.0 12-8 ? 2000 plx technology, inc. all rights reserved. timing diagram 12-5. sram burst write, 32-bit bus; wad=0, wdd=0, wdly=0, whld=1, wrcv=0; master=external addr d0 d1 d2 d3 f 0 a0 a1 a2 a3 f 0 f 0 f 0 f 0 f 0ns 50ns 100ns 150ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[17:0] lcsn# mdqm[3:0] mwe# blast# memrdy (internal) section 12 sram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-9 section 12 ? memory ctrlr 12.2.7 sram read access an sram read access is started when ads# is asserted, lwr# is low, and address falls into the appropriate range. if the iop 480 is controlling the access, the multiplexed address/data bus, lad[19:2], is loaded into the ma[17:0] counter at the end of the period in which ads# is asserted. if an external local bus master is controlling the access, the multiplexed address/data bus, lad[19:2], is loaded into the ma[17:0] counter at the end of the period in which ads# is asserted. after each transfer, ma[17:0] is incremented, thus pointing to the next 32-bit word. the moe# signal is connected to oe# input of the srams, and enables the output drivers during a read access. to prevent bus contention between the address and first data word, rad and rdlya are typically be programmed to a value of 1. burst accesses are not permitted to cross a 32 kb page boundary if an internal burst address is being used. if an external address counter is used, the bterm# input can be used to terminate a burst when page boundary is reached. there are five types of programmable timing parameters associated with sram read accesses as illustrated in table 12-4. as each word is written to memory, the memory controller generates an internal ready signal, memrdy#, which signals the internal local bus controller that the transfer has occurred. memrdy# is based on the internal wait state generator, and is driven out onto the ready# pin when ready# input pin is disabled in the configuration registers. if the ready/recover mode bit is set in the bus region descriptor register, then the ready# pin is also driven during the recovery states. this can be used by an external local bus master to delay the start of the next access until the recovery period has expired. if dram is also being used on the local bus, refresh accesses can cause an sram access to be delayed. this is a result of the sharing of memory controller pins between sram and dram. the timing parameter values shown at the top of each timing diagram refer to delay clock periods. this is not necessarily the value written to the corresponding field in the dramtim register. the dramtim register description details the mapping between the value written and resulting number of delay clock periods. table 12-4. sram read access programmable timing parameters field description rad number of read address-to-data wait states (0-15). determines number of wait states for a single transfer, or for the first word of a burst transfer. in cases where the memory being accessed has some start-up latency associated with it, this number is set larger than the data-to-data wait states. rdd number of read data-to-data wait states (0-15). determines number of wait states between burst data transfers. when this value is set to 0, data is transferred on every clock access. rdlya number of read enable delay states (0-7) for a single transfer or the first burst transfer. determines delay from assertion of chip select until rd# and moe# are first asserted. when this value is set to 0, rd# is asserted one-half clock access after the end of the address phase and moe# is asserted at the end of the address phase. if this field is set to a non-zero value, then the rad value must be set larger to accommodate read strobe delay. this field does not cause wait states to be added automatically. rdlyd number of read enable delay states (0-7) for successive burst transfers. determines the delay between de-assertion and re-assertion of rd# for successive transfers of a burst read access. when this value is set to 0, rd# is reasserted one-half clock cycle after it is de-asserted from the previous transfer. if this field is set to a non-zero value, then the rdd value must be set larger to accommodate the read strobe delay. this field does not cause wait states to be automatically added. rrcv number of read recovery states (1-8). determines the number of recovery states after a single read transfer or last data transfer of a burst. this field is used to provide the device with time to float its outputs before the next address appears on the bus. section 12 memory controller sram iop 480 data book r2.0 12-10 ? 2000 plx technology, inc. all rights reserved. timing diagram 12-6. sram burst read, 32-bit bus, 0 wait states; rad=0, rdd=0, rdlya=0, rdlyd=0, rrcv=0; master=iop 480 timing diagram 12-7. sram burst read, 32-bit bus, 2-1-1-1 wait states, 2 recovery states; rad=2, rdd=1, rdlya=0, rdlyd=0, rrcv=2; master=iop 480 addr d0 d1 d2 d3 a0 a1 a2 a3 0ns 25ns 50ns 75ns 100n s lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[17:0] lcsn# moe# rd# blast# memrdy# (internal) addr d0 d1 d2 d3 ffff-ffff addr 0 a0 a1 a2 a3 0ns 50ns 100ns 150ns 200ns 25 0 lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[17:0] lcsn# moe# rd# blast# memrdy (internal) section 12 sram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-11 section 12 ? memory ctrlr timing diagram 12-8. sram burst read, 32-bit bus, 3-2-2-2 wait states, 2 recovery states; rad=3, rdd=2, rdlya=1, rdlyd=1, rrcv=2; master=iop 480 timing diagram 12-9. sram burst read, 32-bit bus, 0 wait states; rad=0, rdd=0, rdlya=0, rdlyd=0, rrcv=0; master=external local bus master addr d0 d1 d2 d3 ffffffff addr 0 a0 a1 a2 a3 0ns 100ns 200ns 300ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[17:0] lcsn# moe# rd# blast# memrdy (internal) addr d0 d1 d2 d3 a0 a1 a2 a3 0ns 25ns 50ns 75ns 100n s lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[17:0] lcsn# moe# rd# blast# memrdy# (internal) section 12 memory controller dram iop 480 data book r2.0 12-12 ? 2000 plx technology, inc. all rights reserved. 12.3 dram the memory controller supports up to four banks of sdram or edo dram. all four banks must use the same type of memory device. with 14 address lines, sdram or edo dram banks can be up to 64 mb using 4-bit-wide devices. the following address, data, and control signals are used to access dram. table 12-5. dram control signals source signals edo dram sdram memory controller ras[3:0]# / mcs[3:0]# row address strobe. used to strobe the row address into edo dram, and as part of cas-before-ras refresh sequence. each ras enables one of up to four banks of edo dram. chip select. asserted to initiate read, write, and refresh accesses. each chip select enables one of four banks of sdram. mras# unused. row address strobe. asserted to initiate mode register set, precharge, activate, and refresh accesses. mcas# / moe# output enable. used to enable the dram output buffers during a read access. column address strobe. asserted to initiate mode register set, read, write, and refresh access. cas[3:0]# / mdqm[3:0]# column address strobe. used to strobe the column address into the edo dram. each cas# signal corresponds to one byte in the 32-bit-wide memory. input mask, output enable. used to select bytes during write and read accesses. mwe# write enable. asserted during write accesses. write enable. asserted to initiate mode register set, precharge, and memory write accesses. ma13 / lcs3#, ma[12:0] address. 14-bit multiplexed address allows access to 64 mb of edo dram per bank. eight 16 mb x 4 devices = 64 mb four 8 mb x 8 devices = 32 mb tw o 4 mb x 16 devices = 16 mb eight 4 mb x 4 devices = 16 mb four 2 mb x 8 devices = 8 mb tw o 1 mb x 16 devices = 4 mb address. 14-bit multiplexed address allows access up to 64 mb of sdram per bank. eight 16 mb x 4 devices = 64 mb four 8 mb x 8 devices = 32 mb tw o 4 mb x 16 devices = 16 mb eight 4 mb x 4 devices = 16 mb four 2 mb x 8 devices = 8 mb tw o 1 mb x 16 devices = 4 mb also used to provide mode register data during initialization. local bus controller mcke unused. memory clock enable. used to place memory into a suspend state for low power operation. local bus master lclk unused. clock. use local clock as the sdram clock. all controls, address, and data are synchronous to this clock. section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-13 section 12 ? memory ctrlr 12.3.1 synchronous dram (sdram) 12.3.1.1 sdram signal connections table 12-6 shows the connections between the iop 480 memory signals and signal names found in most sdram specifications. 12.3.1.2 sdram example figure 12-5. sdram (two 4m x 16 devices) table 12-6. sdram signals sdram signal iop 480 signal description a[11:0] ma[11:0] multiplexed address bus ba0 ma12 bank address bit 0 ba1 dp0 / ma13 bank address bit 1 dq[31:0] lad[31:0] data bus clk lclk local bus clock cke mcke clock enable cs# mcs[3:0]# chip select ras# mras# row address strobe cas# mcas# column address strobe we# mwe# write enable dqm[3:0]# mdqm[3:0]# i/o mask (byte enables) iop 480 lad[31:0] ma[13:0] mdqm0# mdqm1# mras# mcas# lclk mcke mcs0# mwe# mdqm2# mdqm3# addr clk cke we# dqm0# dqm1# sdram (4mx16) data cas# ras# cs# addr clk cke we# dqm0# dqm1# sdram (4mx16) data cas# ras# cs# section 12 memory controller dram iop 480 data book r2.0 12-14 ? 2000 plx technology, inc. all rights reserved. 12.3.1.3 sdram addressing the multiplexed memory address bus, ma[13:0], is connected to the following local address bus signals for row, column, and bank address. address bits marked with an asterisk are unused in dram. note: for 64-megabit sdrams, dp0/ma13 is required as a bank select, thus preventing the use of data parity. table 12-7. 16-megabit sdram addressing ma bus 1m x 16 2m x 8 4m x 4 mode register row(11) col(8) row(11) col(9) row(11) col(10) 0102112122 1 1 11 3 12 3 13 3 1 (full page burst) 2124134144 1 3 13 5 14 5 15 5 0 (sequential burst) 4146156166 0 5 15 7 16 7 17 7 1 (cas latency of 2) 6168178188 0 7179189199 0 818 0 19102010 0 91902002111 0 10200210220 0 11 21 = bank address 22 = bank address 23 = bank address 0 12 22* 23* 24* 0 13 23* 24* 25* 0 table 12-8. 64-megabit sdram addressing ma bus 4m x 16 8m x 8 16m x 4 mode register row(12) col(8) row(12) col(9) row(12) col(10) 0102112122 1 1 11 3 12 3 13 3 1 (full page burst) 2124134144 1 3 13 5 14 5 15 5 0 (sequential burst) 4146156166 0 5 15 7 16 7 17 7 1 (cas latency of 2) 6168178188 0 7179189199 0 818 0 19102010 0 91902002111 0 10200210220 0 11210220230 0 12 22 = ba0 23 = ba0 24 = ba0 0 13 23 = ba1 24 = ba1 25 = ba1 0 section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-15 section 12 ? memory ctrlr 12.3.1.4 sdram initialization after the sdrams are powered up and have a stable clock, no commands are issued for at least 200 s. this timeout is based on 13200 clock ticks at local bus clock frequency of 66 mhz. if a slower local bus clock is used, then the power-on delay increases. the delay is calculated as follows: delay = (1/local bus clock frequency) x 13200. all of the command signals (mras#, mcas#, mwe#, mcs[3:0]#, and mdqm[3:0]#) are held in an inactive state during this period. after the 200 s delay, a precharge command is initiated with mcke asserted, precharging both banks. now the sdrams are ready to have their mode registers loaded with the operating mode. the mode register is used to define specific operating modes of sdram, and is programmed with the load mode register command. the mode register is loaded when both banks are idle. the controller must wait the specified time before initiating subsequent operations. the value to be programmed into the mode register is presented to sdram on the multiplexed address bus ma[13:0]. a configuration register in the iop 480 provides the capability to reload the mode register into the sdrams if the default values are not appropriate for the application. the memory controller uses the current value of the sdram initialization word in the draminit register to adjust for different values of cas latency. when the draminit register sdram initialization order bit is low, the mode register is loaded first, followed by eight auto-refresh accesses. when the draminit register sdram initialization order bit is high, the eight auto-refresh accesses are run first, followed by the mode register load. the sdram is now ready to accept an activate command. following is a description of the mode register. 12.3.1.4.1 burst length the burst length determines the maximum number of columns that can be accessed during a read or write burst. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. for the iop 480, the burst length in sdrams should be set to ? full-page. ? in this mode, a burst with an arbitrary length is supported. full-page bursts wrap within the page if the boundary is reached. all burst accesses are sequential for full-page burst mode, and bursts cannot cross a page boundary. page lengths and boundaries are illustrated in table 12-9. 12.3.1.4.2 burst type burst accesses may be sequential or interleaved. for the iop 480, the type should always be set to sequential. 12.3.1.4.3 cas latency cas latency is the delay from the read command to the first valid read data, and can be set to 1, 2, or 3. for local bus speeds between 33 and 66 mhz, set cas latency to 2. 12.3.1.4.4 operating mode the operating mode should always be set to standard operation. other values are for testing purposes only. 12.3.1.4.5 write burst mode the write burst mode determines whether write accesses are burst or single-access only. if this bit is 0, both read and write accesses can be burst accesses. if this bit is 1, then only read accesses can be burst accesses. figure 12-6 is a diagram showing the bit locations of the mode register. table 12-9. sdram page lengths/boundaries number of columns max page length page boundary 8 (x 16 devices) 1024 1024 9 (x 8 devices) 2048 2048 10 (x 4 devices) 4096 4096 section 12 memory controller dram iop 480 data book r2.0 12-16 ? 2000 plx technology, inc. all rights reserved. figure 12-6. sdram mode register address bus mode register (mx) reserved * wb op mode cas latency bt burst length 11 10 9 8 7 6 543 210 ba a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 burst length m3 = 0 m3 = 1 m2 m1 m0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 1 22 4 4 8 8 reserved reserved reserved reserved reserved reserved reserved full page m3 0 1 burst type sequential interleave cas latency m6 m5 m4 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 2 3 reserved reserved reserved reserved reserved m8 m7 m6-m0 operating mode 0 0 defined standard operation all other states reserved ? ?? m9 0 1 write burst mode programmed burst length single location access * should program m11, m10 = 0, 0 to ensure compatibility with future devices section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-17 section 12 ? memory ctrlr 12.3.1.5 sdram commands the following table lists commands that can be issued to sdrams. signal names relate to the sdram device specifications. table notes: 1. cke is high for all commands shown except self- refresh. 2. 16-megabit device: a0 through a10 and ba defines the op-code written to the mode register. 64-megabit device: a0 through a11 defines the op- code written to the mode register. 3. 16-megabit device: a0 through a10 provide the row address, and ba determines which bank is made active. (ba low bank 0, ba high bank 1). 64-megabit device: a0 through a11 provide the row address, and ba0, ba1 determine which bank is made active. 4. 16-megabit device: a0 through a9 provide the column address (a9 is a ? don ? t care ? for x8 devices and a8,9 are ? don ? t cares ? for x16 devices). a10 high enables the auto precharge feature (nonpersistent) while a10 low disables the auto precharge feature. ba determines which bank is being read from or written to (ba low bank 0, ba high bank 1). 64-megabit device: a0 through a9 provide the column address (a9 is a ? don ? t care ? for x8 devices and a8,9 are ? don't cares ? for x16 devices). a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the auto precharge feature. ba0 and ba1 determines which bank is being read from or written to. 5. 16-megabit device: a10 low: ba determines bank being precharged (ba low bank 0, ba high bank 1) a10 high: both banks precharged and ba is a ? don ? t care. ? 64-megabit device: a10 low: ba0, ba1 determine the bank being precharged. a10 high: all banks precharged and ba0 and ba1 are ? don ? t care. ? 6. this command is auto refresh if cke is high, and self-refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ? don ? t care ? except for cke. 8. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay). 12.3.1.5.1 command inhibit command inhibit prevents new commands from being executed and the sdram is effectively deselected. operations in progress continue. table 12-10. sdram commands command cs# ras# cas# we# dqm addr dqs notes command inhibit (nop/continue previous operation) h x x x x x x ? no operation (nop/continue previous operation) l h h h x x x ? active (select bank and activate row) l l h h x bank/row x 3 read (select bank and column and start read burst) l h l h x bank/col x 4 write (select bank and column and start write burst) l h l l x bank/col valid 4 burst terminate l h h l x x active ? precharge (deactivate row in bank or banks) l l h l x code x 5 auto-refresh or self-refresh (enter self-refresh mode) lllhx x x6, 7 load mode register l l l l x op-code x 2 write enable/output enable ???? l ? active 8 write inhibit/output high-z ???? h ? high-z 8 section 12 memory controller dram iop 480 data book r2.0 12-18 ? 2000 plx technology, inc. all rights reserved. 12.3.1.5.2 no operation no operation prevents new commands from being executed, while the sdram is selected (cs# low). this prevents commands from being registered during idle or waits states. operations in progress continue. 12.3.1.5.3 active active activates a row for subsequent accesses. this row remains active until a precharge command is issued ? precharge command must be issued before activating a different row in the same bank. 12.3.1.5.4 read read initiates a burst read access to the active row. the value on ba inputs selects the bank, while the address on a0-9 selects the starting column. the value on a10 determines whether auto precharge is used. if auto precharge is selected, then the row being accessed is precharged at the end of burst. if auto precharge is not selected, the row remains open for access. read data appears on the outputs after the cas latency period, and subject to the value on dqm inputs two clocks earlier (the output enable latency on dqm bits is two clock accesses). 12.3.1.5.5 write write initiates a burst write access to the active row. the value on ba inputs selects the bank, and the address on a[9:0] selects the starting column. the value on a10 determines whether auto precharge is used. if auto precharge is selected, then the row being accessed is precharged at the end of burst. if auto precharge is not selected, the row remains open for access. data is written to memory if the dqm inputs are active coincident with the valid data. the first word to be written can be presented coincident with the write command. 12.3.1.5.6 burst terminate burst terminate terminates only full-page bursts. 12.3.1.5.7 precharge precharge deactivates open rows in one or both banks. if input a10 is low, ba determines which bank is precharged. if input a10 is high, all banks are precharged. once a bank has been precharged, it remains in the idle state and must be activated prior to new read or write commands to that bank. 12.3.1.5.8 auto-precharge auto-precharge performs a precharge without an explicit precharge command, but is not used in full-page burst mode. 12.3.1.5.9 auto-refresh auto-refresh is analogous to cas-before-ras refresh in edo drams. refresh request must be explicitly made. the refresh address is generated internally. a refresh access must be run every 15.6 s in order to refresh 4096 rows every 64 ms. 12.3.1.5.10 self-refresh self-refresh retains data when the rest of the system is powered down. use the following procedure to enter self-refresh mode: issue a burst of 4096 auto-refresh accesses bring cke, cs#, ras#, cas# low and we# high for one clock period keep cke low; other inputs are ? don ? t cares ? during self-refresh, sdram provides its own internal clocking, refresh requests, and address. the following procedure must be used to exit self-refresh mode: wait for clk to stabilize bring cke high issue nop commands for t xsr time (at least 96 ns) issue a burst of 4096 auto refresh accesses 12.3.1.6 operation 12.3.1.6.1 page mode once a row is activated, any column within the current row can be accessed for reads or writes by asserting cas# with the appropriate column address. if the page mode bit in the dram configuration registers is enabled, no precharge command is asserted after the end of an access. during the address phase of the next access, the new row address is compared with previous row address. if they match, a page hit has occurred and the column can be addressed without activating a new row. if a page miss occurs, then the section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-19 section 12 ? memory ctrlr device must precharge and a new row activated. if the application tends towards sequential accesses, then enabling page mode improves performance. random accesses achieve the best performance by having page mode disabled. there is only one page mode row address register that is shared between the four banks of sdrams. therefore, only one row out of all of the banks can be kept active when page mode is enabled. if a page miss occurs, all banks are precharged. if page mode is disabled, all banks are precharged at the end of every single or burst access. if the page mode is enabled, then disabled, the sdram needs to be re-initialized by writing to the draminit register. 12.3.1.6.2 parity checking even or odd parity is generated for each byte on the local data bus. the parity select bit in drambrd register selects polarity of the parity. when data is being read from sdram, parity is checked if it is enabled in the corresponding configuration register. when the iop 480 is the local bus master, all four bytes are checked for parity. when an external master controls the local bus, the lbe[3:0]# signals determine which bytes are checked for parity. parity errors can be programmed to cause an interrupt. 12.3.1.6.3 burst length the length of a burst access depends upon the master accessing sdram, and number of columns in sdram. when the direct slave interface or internal dma controller is accessing sdram, a burst read can be of any length, as long as it fits within a page of sdram. when the internal iop 480 cpu is accessing sdram, burst are limited to a maximum of four, 32-bit sequential words. local bus masters can perform burst accesses of any length, up to the maximum page length of the sdram without crossing a page boundary. 12.3.1.6.4 auto-refresh an auto-refresh access is run at a rate determined by the dramctl refresh interval bit(s) and the local bus clock frequency. a typical refresh rate for most drams is 15.625 s, and is calculated as follows: register value = refresh rate x lclk clock frequency. typically, the register value = 15.625 s x 66.666 mhz = 1041 = 0x411. the value after reset is 0x407. the refresh access has priority over other dram requests. if a refresh request occurs during an sdram burst access, the burst is preempted. the refresh address is generated internally in sdram devices when using auto-refresh. if a refresh request occurs during a dram burst access, then the master of the burst access is preempted. the following table lists the commands to perform auto-refresh. 12.3.1.6.5 self-refresh self-refresh retains system data when the rest of the system is powered down. it is initiated when the power management state matches the state specified in the self-refresh field of the drmctl configuration register. table 12-11. refresh arbitration master action internal iop 480 cpu wait for end of burst (limited to four words) direct slave controller assert blast# and terminate burst dma controllers assert blast# and terminate burst lholdreq0 assert boff# lholdreq1 none table 12-12. auto refresh commands command description precharge all banks if any rows are active nop to satisfy t rp ; precharge command period auto-refresh issues auto-refresh command 7 nops to satisfy t rc ; auto-refresh to active delay section 12 memory controller dram iop 480 data book r2.0 12-20 ? 2000 plx technology, inc. all rights reserved. timing diagram 12-10. sdram initialization . timing diagram 12-11. sdram auto-refresh a10=1 pchg nop ldmode nop nop auto-rf nop opcode note 1: controller waits for 200 us after vcc and clock are stable before issuing the precharge command. note 2: controller issues eight auto-refresh cycles after the load mode command is issued. 0ns 50ns 100ns 150ns 200ns 250ns lclk ma[13:0] cmd (internal) mcs# mras# mcas# mwe# mcke a10=1 pchg nop auto-rf nop 0ns 50ns 100ns 150ns lclk ma[13:0] cmd (internal) mcs# mras# mcas# mwe# mcke section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-21 section 12 ? memory ctrlr timing diagram 12-12. sdram self-refresh start timing diagram 12-13. sdram self-refresh end a10=1 pchg nop auto-rf nop self-rf note: must perform 4096 auto-refresh cycles before issuing the self-refresh command. 0ns 50ns 100ns 150ns 200n s lclk ma[13:0] cmd (internal) mcs# mras# mcas# mwe# mcke a10=1 pchg nop auto-rf nop nop auto-rf nop note: must perform 4096 auto-refresh cycles after mcke is asserted. 0ns 50ns 100ns 150ns 200ns 250ns 300n s lclk ma[13:0] cmd (internal) mcs# mras# mcas# mwe# mcke section 12 memory controller dram iop 480 data book r2.0 12-22 ? 2000 plx technology, inc. all rights reserved. 12.3.1.6.6 sdram initialization the mode register is loaded at initialization, and is used to set the operating parameters of sdram. 12.3.1.6.7 sdram write access an sdram write access starts when ads# is asserted, lwr# high, and address falls into the appropriate range. if the iop 480 is controlling the access, the row address is loaded into the ma[13:0] counter at beginning of the period in which ads# is asserted. if an external local bus master is controlling the access, the row address is loaded into the ma[13:0] counter at the end of the period in which ads# is asserted. during the next clock period, a row is activated by assertion of one of the mcs[3:0]# signals and mras#. the active to write delay is determined by the a2c value in the dram timing configuration register. the ma[13:0] bus is switched to the column address as soon as the active command is registered. the write command is initiated by asserting mcas#, mwe#, and the appropriate mdqm[3:0]# bits. each mdqm[3:0]# signal corresponds to one of the byte lanes (dqm3# ! lad[31:24], ? , dqm0# ! lad[7:0]). the first word of data is written into sdram during this clock cycle. as long as the mdqm[3:0]# bits remain asserted, data is written on each successive cycle. when blast# is detected, the burst write is terminated by issuing a precharge command. the mdqm[3:0]# bits are also de-asserted, thus preventing unwanted writes. burst accesses are not permitted to cross the natural page boundary of sdram devices. three programmable timing parameters are associated with the sdram access, as illustrated in table 12-13. the timing parameter values shown at the top of each timing diagram refer to delay clock periods. this is not necessarily the value written to the corresponding field in the dramtim register. the dramtim register description details the mapping between the value written and resulting number of delay clock periods. section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-23 section 12 ? memory ctrlr timing diagram 12-14. sdram four word non-page mode burst write, 2-0-0-0 wait states; a2c=1, w2w=0, prcg=3; master=iop 480 table 12-13. sdram write access programmable timing parameters field description a2c active command to read/write command delay (1-4). determines number of clock delays between assertion of active and read/write commands. for a 66 mhz bus, this number is typically set to 1. w2w delay between words of a burst write (0-3). determines number of clock delays between successive words of a burst write. mcke is de-asserted during the wait states. for a 66 mhz bus, this number is typically set to 0. prcg precharge delay (1-4). determines the number of clock delays required between precharge and next active command. for a 66 mhz bus, this number is typically set to 2. addr d1 d2 row col0 d0 d3 actv nop wr nop pchg nop nop actv addr data row col ma10=1 0ns 50ns 100ns 150ns 200ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[13:0] cmd (internal) mcsn# mras# mcas# mwe# mdqm[3:0]# blast# memrdy# (internal) section 12 memory controller dram iop 480 data book r2.0 12-24 ? 2000 plx technology, inc. all rights reserved. l timing diagram 12-15. sdram page hit burst write, 1-0-0-0 wait states; w2w=0; master=iop 480 addr d1 d2 col0 d0 d3 wr nop nop 0ns 25ns 50ns 75ns 100ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[13:0] cmd (internal) mcsn# mras# mcas# mwe# mdqm[3:0]# blast# memrdy# (internal) section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-25 section 12 ? memory ctrlr timing diagram 12-16. sdram page hit burst write, 2-1-1-1 wait states; w2w=1; master=iop 480 addr d1 d2 col0 d0 d3 wr nop nop 0ns 50ns 100ns 150ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[13:0] cmd (internal) mcsn# mras# mcas# mwe# mdqm[3:0]# blast# memrdy# (internal) mcke section 12 memory controller dram iop 480 data book r2.0 12-26 ? 2000 plx technology, inc. all rights reserved. timing diagram 12-17. sdram page miss burst write, 6-0-0-0 wait states; a2c=1, w2w=0, prcg=2; master=iop 480 addr d1 d2 row col0 d0 d3 actv nop wr nop nop pchg nop ma10=1 row 0ns 50ns 100ns 150ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[13:0] cmd (internal) mcsn# mras# mcas# mwe# mdqm[3:0]# blast# memrdy# (internal) section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-27 section 12 ? memory ctrlr timing diagram 12-18. sdram four word non-page mode burst write, 2-0-0-0 wait states; a2c=1, w2w=0, prcg=3; master=external local bus master addr d1 d2 row col0 d0 d3 actv nop wr nop pchg nop nop actv addr data row col ma10=1 0ns 50ns 100ns 150ns 200ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[13:0] cmd (internal) mcsn# mras# mcas# mwe# mdqm[3:0]# blast# memrdy# (internal) section 12 memory controller dram iop 480 data book r2.0 12-28 ? 2000 plx technology, inc. all rights reserved. timing diagram 12-19. sdram page hit burst write, 1-0-0-0 wait states; w2w=0; master=external local bus master addr d1 d2 col0 d0 d3 wr nop nop 0ns 25ns 50ns 75ns 100ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[13:0] cmd (internal) mcsn# mras# mcas# mwe# mdqm[3:0]# blast# memrdy# (internal) section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-29 section 12 ? memory ctrlr timing diagram 12-20. sdram page hit burst write, 2-1-1-1 wait states; w2w=1; master=external local bus master addr d1 d2 col0 d0 d3 wr nop nop 0ns 50ns 100ns 150ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[13:0] cmd (internal) mcsn# mras# mcas# mwe# mdqm[3:0]# blast# memrdy# (internal) mcke section 12 memory controller dram iop 480 data book r2.0 12-30 ? 2000 plx technology, inc. all rights reserved. timing diagram 12-21. sdram page miss burst write, 6-0-0-0 wait states; a2c=1, w2w=0, prcg=2; master=external local bus master addr d1 d2 col0 d0 d3 actv nop wr nop nop pchg nop ma10=1 row 0ns 50ns 100ns 150ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[13:0] cmd (internal) mcsn# mras# mcas# mwe# mdqm[3:0]# blast# memrdy# (internal) section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-31 section 12 ? memory ctrlr timing diagram 12-22. long sdram burst write addr 03020100 d0 d1 d2 d3 d4 d5 d6 d7 f 0 0000 row nop active nop write nop f 0 col 0ns 100ns 200ns 300ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[13:0] cmd (internal) mcs0# mras# mcas# mwe# mdqm[3:0] blast# memrdy# (internal) section 12 memory controller dram iop 480 data book r2.0 12-32 ? 2000 plx technology, inc. all rights reserved. 12.3.1.6.8 sdram read access an sdram read access starts when ads# is asserted, lwr# is low, and the address falls into the appropriate range. if the iop 480 is controlling the access, the row address is loaded into the ma[13:0] counter at the beginning of the period in which ads# is asserted. if an external local bus master is controlling the access, the row address is loaded into the ma[13:0] counter at the end of the period in which ads# is asserted. during the next clock period, a row is activated by the assertion of one of the mcs[3:0]# signals and mras#. the active to read delay is determined by the a2c value in the dram timing configuration register. the ma[13:0] bus is switched to the column address as soon as the active command is registered. the read command is initiated by asserting mcas# and the appropriate mdqm[3:0]# bits. each mdqm[3:0]# signal corresponds to one of the byte lanes (dqm3# ! lad[31:24], ? , dqm0# ! lad[7:0]), and for reads, all mdqm bits are asserted. the first word of data is available during the second clock after the read command is registered, resulting from cas latency being set to 2. as long as the mdqm bits remain asserted, data is read on each successive access. when blast# is detected, the burst read is terminated by issuing a precharge command. mdqm bits are also de-asserted. because the mdqm bits have two-clock latency, two additional words are read during the precharge command. for masters capable of providing advance warning of the end of the burst (internal iop 480 cpu and pci interface), the precharge command can be issued during second to last transfer, thereby eliminating the two extra read accesses. burst accesses are not permitted to cross the natural page boundary of sdram devices. there are three programmable timing parameters associated with an sdram access (refer to table 12-14). the timing parameter values shown at the top of each timing diagram refer to delay clock periods. this is not necessarily the value written to the corresponding field in the dramtim register. the dramtim register description details the mapping between the value written and resulting number of delay clock periods. table 12-14. sdram read access programmable timing parameters field description a2c active command to read/write command delay (1-4). determines number of clock delays between assertion of active and read/write commands. for a 66 mhz bus, this number is typically set to 1. prcg precharge delay (1-4). determines the number of clock delays required between precharge command and next active command. for a 66 mhz bus, this number is typically set to 2. rrcv number of read recovery states (1-4). determines the number of extra wait states inserted at the end of dram access, and used to provide the device with adequate time to float its data output buffers. for a 66 mhz bus, this number is typically set to 2 clocks. for an external local bus master, two extra words are always read at end of a burst read. the rrcv value is loaded into a timer, which operates concurrently with the recovery states generated due to the two-word, read overrun. in this case, the minimum number of recovery states is three, and the maximum is four. section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-33 section 12 ? memory ctrlr timing diagram 12-23. sdram non-page mode burst read, 4-0-0-0 wait states; a2c=1, pchg=2; master=iop 480 addr d1 d2 row col0 d0 d3 actv nop rd nop pchg nop addr ma10=1 row col actv 0ns 50ns 100ns 150ns 200ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[13:0] cmd (internal) mcsn# mras# mcas# mwe# mdqm[3:0] early_blast# (internal) blast# memrdy# (internal) section 12 memory controller dram iop 480 data book r2.0 12-34 ? 2000 plx technology, inc. all rights reserved. timing diagram 12-24. sdram page hit burst read, 3-0-0-0 wait states; master=iop 480 addr d1 d2 col0 d0 d3 rd nop nop 0ns 50ns 100ns 1 lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[13:0] cmd (internal) mcsn# mras# mcas# mwe# mdqm[3:0]# early_blast# (internal) blast# memrdy# (internal) section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-35 section 12 ? memory ctrlr ` timing diagram 12-25. sdram page miss burst read, 8-0-0-0 wait states; a2c=1, prcg=2; master=iop 480 addr d1 row col0 d2 actv nop rd nop nop pchg nop ma10=1 row d0 d3 0ns 50ns 100ns 150ns 200ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[13:0] cmd (internal) mcsn# mras# mcas# mwe# mdqm[3:0]# early_blast# (internal) blast# memrdy# (internal) section 12 memory controller dram iop 480 data book r2.0 12-36 ? 2000 plx technology, inc. all rights reserved. timing diagram 12-26. sdram non-page mode burst read, 4-0-0-0 wait states; a2c=1, pchg=2; master=external local bus master addr d1 d2 row col d0 d3 actv nop rd nop pchg nop addr ma10=1 row col actv d4* d5* 0ns 50ns 100ns 150ns 200ns 2 5 lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[13:0] cmd (internal) mcsn# mras# mcas# mwe# mdqm[3:0] blast# memrdy# (internal) section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-37 section 12 ? memory ctrlr timing diagram 12-27. sdram page hit burst read, 3-0-0-0 wait states; master=external local bus master addr d1 d2 col0 d0 d3 rd nop nop d4* d5* 0ns 50ns 100ns 150ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[13:0] cmd (internal) mcsn# mras# mcas# mwe# mdqm[3:0]# blast# memrdy# (internal) section 12 memory controller dram iop 480 data book r2.0 12-38 ? 2000 plx technology, inc. all rights reserved. timing diagram 12-28. sdram page miss burst read, 8-0-0-0 wait states; a2c=1, pchg=2; master=external local bus master addr d1 col0 d2 actv nop rd nop nop pchg nop ma10=1 row d0 d3 d4* d5* 0ns 50ns 100ns 150ns 200ns 2 5 lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[13:0] cmd (internal) mcsn# mras# mcas# mwe# mdqm[3:0]# blast# memrdy# (internal) section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-39 section 12 ? memory ctrlr 12.3.2 edo dram 12.3.2.1 edo signal connections table 12-15 lists the connections between the iop 480 memory signals and signal names found in most edo dram specifications. note: ? n ? is equal to pin number 0, 1, 2, or 3. 12.3.2.2 edo dram examples figure 12-7. edo dram (two 4m x 16 devices) table 12-15. edo signals edo dram signal iop 480 signal description a[12:0] ma[12:0] multiplexed address bus dq[31:0] lad[31:0] data bus ras# ras n # row address strobe cas# cas n # column address strobe we# mwe# write enable oe# moe# output enable iop 480 lad[31:0] ma[13:0] cas0# cas1# cas2# cas3# rasn# moe# mwe# ma[12:0] addr ras# oe# we# casl# cash# edo dram (4mx16) data addr ras# oe# we# casl# cash# edo dram (4mx16) data lad[31:0] section 12 memory controller dram iop 480 data book r2.0 12-40 ? 2000 plx technology, inc. all rights reserved. figure 12-8. edo dram (four 8m x 8 devices) 12.3.2.3 edo addressing the multiplexed memory address bus, ma[12:0], is connected to the following local address bus signals for the row and column. the most significant bits of the multiplexed memory address bus, ma[17:13], are not used for edo drams. dram manufacturers offer several configurations of the numbers of rows and columns in a particular device; therefore, the correct selection must be made in the configuration registers. address bits marked with an asterisk are unused in dram. table 12-17 and table 12-18 illustrate 16- and 64-megabit edo addressing. the maximum burst length is determined by column size. bursts cannot cross page boundaries. iop 480 lad[31:0] ma[13:0] mwe# cas1# cas2# rasn# moe# ma[12:0] cas0# cas3# lad[31:0] addr ras# oe# we# edo dram 8mx8 data cas# addr ras# oe# we# edo dram 8mx8 data cas# addr ras# oe# we# edo dram 8mx8 data cas# addr ras# oe# we# edo dram 8mx8 data cas# table 12-16. edo page lengths/boundaries number of columns max page length page boundary 8 1024 1024 9 2048 2048 10 4096 4096 11 8192 8192 12 16384 16384 section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-41 section 12 ? memory ctrlr table 12-17. 16-megabit edo addressing ma bus 1m x 16 2m x 8 4m x 4 8 column 10 column 9 column 10 column 10 column 11 column row(12) col(8) row(10) col(10) row(12) col(9) row(11) col(10) row(12) col(10) row(11) col(11) 0102122112122122132 1113133123133133143 2124144134144144154 3135155145155155165 4146166156166166176 5157177167177177187 6168188178188188198 7179199189199199209 8 18 0 20101910201020102110 9 19 0 211120 0 211121112211 10 20 0 22* 0 21 0 22 0 22 0 23 12 11 21 0 23* 0 22 0 23* 0 23 0 24* 0 12 22* 0 24* 0 23* 0 24* 0 24* 0 25* 0 13 23* 0 25* 0 24* 0 25* 0 25* 0 26* 0 table 12-18. 64-megabit edo addressing ma bus 4m x 16 8m x 8 16m x 4 9 column 10 column 10 column 11 column 11 column 12 column row(13) col(9) row(12) col(10) row(13) col(10) row(12) col(11) row(13) col(11) row(12) col(12) 0 112122122132132142 1 123133133143143153 2 134144144154154164 3 145155155165165175 4 156166166176176186 5 167177177187187197 6 178188188198198208 7 189199199209209219 8 191020102010211021102210 9 20 0 21 11 21 11 22 11 22 11 23 11 10 21 0 22 0 22 0 231223122412 11 22 0 23 0 23 0 24 0 24 0 25 13 12 23 0 24* 0 24 0 25* 0 25 0 26* 0 13 24* 0 25* 0 25* 0 26* 0 26* 0 27* 0 section 12 memory controller dram iop 480 data book r2.0 12-42 ? 2000 plx technology, inc. all rights reserved. 12.3.2.4 initialization after edo drams are powered up, no dram accesses are started for at least 200 s. this timeout is based on 13200 clock ticks at a local bus clock frequency of 66 mhz. if a slower local bus clock is used, then the power-on delay increases. the delay is calculated as follows: delay = (1/local bus clock freq) x 13200. all control signals (ras#, cas#, we#, and oe#) are held in an inactive state during this period. after the 200 s delay, eight cas-before-ras (cbr) refresh accesses are run. the edo drams are now ready for read and write accesses. 12.3.2.5 refresh a cas-before-ras (cbr) refresh access is run at a rate determined by the refresh interval field of the dram control register and the local bus clock frequency. a typical refresh rate for most drams is 15.625 s, and is calculated as follows: register value = refresh rate x lclk clock frequency. typically, the register value = 15.625 s x 66.666 mhz = 1041 = 0x411. the value after reset is 0x407. refresh access has priority over other dram requests. a refresh access only occurs when both the edo and sram state machines are idle. (refer to figure 12-29.) if a refresh request occurs during a dram burst access, then the master of the burst access is preempted. 12.3.2.6 page mode when ras# is asserted, any column within the current row can be accessed by asserting cas# with the appropriate column address. if the page mode bit in dram configuration registers is enabled, ras# remains asserted after the end of an access. during the next access address cycle, the new row address is compared with previous row address. if they match, a page hit occurs and the column can be addressed without strobing in a new row address. if a page miss occurs, then ras# must be de-asserted, the ras precharge time must be satisfied, and a new row address strobed in before data is accessed. if an application tends towards sequential accesses, then enabling page mode improves performance. with page mode disabled, random accesses achieve the best performance. 12.3.2.7 edo write access an edo write access is started when ads# is asserted, lwr# is high, and the address falls into the appropriate range. the moe# signal is connected to the oe# input of drams, and disables output drivers during a write access. if the iop 480 is controlling the access, the row address is loaded into the ma[12:0] counter at the beginning of the period in which ads# is asserted. if an external local bus master is controlling the access, the row address is loaded into the ma[12:0] counter at the end of the period in which ads# is asserted. the mwe# signal is also asserted at the same time as the row address. because mwe# is asserted before the cas[3:0]# signals, an early write access is utilized. during an early write, the data output remains in the high-impedance state regardless of the oe# input, and data is latched on the leading (falling) edge of cas[3:0]#. each cas signal corresponds to one of the byte lanes (cas3# ! lad[31:24], ? ,cas0# ! lad[7:0]). after the row address to ras delay, one of the ras[3:0]# signals is asserted, strobing the row address into the device. after the ras to column address delay, the ma[12:0] address bus is switched to the column address. after the column address to cas delay, cas[3:0]# is asserted, strobing the column address into the device. the write is complete when cas[3:0]# is de-asserted. if a burst access is requested, then the ma[12:0] address is incremented and cas[3:0]# is re-asserted. burst accesses are not permitted to cross a page boundary (refer to table 12-16). there are five types of programmable timing parameters associated with an edo dram write access, as illustrated in table 12-20. table 12-19. refresh arbitration master action internal iop 480 cpu wait for end of burst (limited to four words) direct slave controller assert blast# and terminate burst dma controllers assert blast# and terminate burst lholdreq0 assert boff# lholdreq1 none section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-43 section 12 ? memory ctrlr the timing parameter values shown at the top of each timing diagram refer to delay clock periods. this is not necessarily the value written to the corresponding field in the dramtim register. the dramtim register description details the mapping between the value written and resulting number of delay clock periods. timing diagram 12-29. edo dram refresh table 12-20. edo dram write access programmable timing parameters field description r2r row address to ras delay (1-4). determines the number of clock delays between assertion of the row address and ras[3:0]#. for a 66 mhz bus, this number is typically set to 1 clock for a 60 ns dram. for a heavily loaded ma[12:0] bus, or when using external buffers, this value may need to be increased. r2c ras to column address delay (1-4). determines the number of clock delays between assertion of ras[3:0]# and the first column address. for a 66 mhz bus, this number is typically set to 2 clocks for a 60 ns dram. for a heavily loaded ma[12:0] bus, or when using external buffers, this value may need to be increased. c2c column address to cas delay (1-4). determines the number of clock delays between assertion of column address and cas[3:0]#. for a 66 mhz bus, this number is typically set to 1 clock for a 60 ns dram. for a heavily loaded ma[12:0] bus, or when using external buffers, this value may need to be increased. note that during a page hit when iop 480 is bus master, there is always additional delay from column address to cas[3:0]# because the address comes out one clock earlier. wcw write cas width (1-4). determines the width of each cas[3:0]# pulse. for a 66 mhz bus, this number is typically set to 1 clock. the internal memrdy# signal is asserted in the last clock period during which cas[3:0]# is asserted. prcg number of ras precharge states (1-4). determines the number of states between de-assertion of one ras[3:0]# and assertion of the next ras[3:0]#, and is used to provide adequate ras precharge time. for a 66 mhz bus, this number is typically set to 3 clocks. 0ns 25ns 50ns 75ns 100ns 125ns lclk casn# rasn# mwe# section 12 memory controller dram iop 480 data book r2.0 12-44 ? 2000 plx technology, inc. all rights reserved. timing diagram 12-30. edo dram non-page mode burst write, 3-1-1-1 wait states; r2r=1, r2c=2, c2c=1, wcw=1, prcg=3; master=iop 480 timing diagram 12-31. edo dram page hit burst write, 1-1-1-1 wait states; c2c=1, wcw=1; master=iop 480 addr d0 d1 d2 d3 row col0 col2 col1 col3 addr data row 0ns 50ns 100ns 150ns 200ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[12:0] rasn# mwe# cas[3:0]# blast# memrdy# (internal) addr d0 d1 d2 d3 col0 col2 col1 col3 0ns 50ns 100ns 150ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[12:0] rasn# mwe# cas[3:0]# blast# memrdy# (internal) section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-45 section 12 ? memory ctrlr timing diagram 12-32. edo dram page hit burst write, 2-2-2-2 wait states; c2c=2, wcw=1; master=iop 480 timing diagram 12-33. edo dram page miss burst write, 6-1-1-1 wait states; r2r=1, r2c=2, c2c=1, wcw=1, prcg=3; master=iop 480 addr d0 d1 d2 d3 col0 col2 col1 col3 0ns 50ns 100ns 150ns 200ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[12:0] rasn# mwe# cas[3:0]# blast# memrdy# (internal) addr d0 d1 d2 d3 row col0 col2 col1 col3 0ns 50ns 100ns 150ns 200ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[12:0] rasn# mwe# cas[3:0]# blast# memrdy# (internal) section 12 memory controller dram iop 480 data book r2.0 12-46 ? 2000 plx technology, inc. all rights reserved. timing diagram 12-34. edo dram non-page mode burst write, 4-1-1-1 wait states; r2r=1, r2c=2, c2c=1, wcw=1, prcg=3; master=external local bus master timing diagram 12-35. edo dram page hit burst write, 2-1-1-1 wait states; c2c=1, wcw=1; master=external local bus master addr d0 d1 d2 d3 row col0 col2 col1 col3 addr data row 0ns 50ns 100ns 150ns 200ns 25 0 lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[12:0] rasn# mwe# cas[3:0]# blast# memrdy# (internal) ready# addr d0 d1 d2 d3 col0 col2 col1 col3 0ns 50ns 100ns 150ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[12:0] rasn# mwe# cas[3:0]# blast# memrdy# (internal) ready# section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-47 section 12 ? memory ctrlr timing diagram 12-36. edo dram page hit burst write, 3-2-2-2 wait states; c2c=1, wcw=2; master=external local bus master timing diagram 12-37. edo dram page miss burst write, 6-1-1-1 wait states; r2r=1, r2c=2, c2c=1, wcw=1, prcg=3; master=external local bus master addr d0 d1 d2 d3 col0 col2 col1 col3 0ns 50ns 100ns 150ns 200ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[12:0] rasn# mwe# cas[3:0]# blast# memrdy# (internal) ready# addr d0 d1 d2 d3 row col0 col2 col1 col3 0ns 50ns 100ns 150ns 200ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[12:0] rasn# mwe# cas[3:0]# blast# memrdy# (internal) ready# section 12 memory controller dram iop 480 data book r2.0 12-48 ? 2000 plx technology, inc. all rights reserved. 12.3.2.8 edo read access an edo read access is started when ads# is asserted, lwr# low, and the address falls into the appropriate range. the moe# signal is connected to oe# input of the drams, and enables the output drivers during a read access. if the iop 480 is controlling the access, the row address is loaded into the ma[12:0] counter at the beginning of the period in which ads# is asserted. if an external local bus master is controlling the access, the row address is loaded into the ma[12:0] counter at the end of the period in which ads# is asserted. the mwe# signal remains de-asserted throughout read the access. after the row address to ras delay, one of the ras[3:0]# signals is asserted, strobing the row address into the device. after ras to column address delay, the ma[12:0] address bus is switched to the column address. after the column address to cas delay, cas[3:0]# is asserted, strobing the column address into the device. for a 60 ns dram, read data is available 60 ns after ras# is asserted, 15 ns after cas[3:0]# is asserted, and 30 ns after the column address is available. if a burst access is requested, then the ma[12:0] address is incremented and cas[3:0]# is reasserted. burst accesses are not permitted to cross a page boundary (refer to table 12-16 on page 12-40). there are six types of programmable timing parameters associated with edo dram read access, as illustrated in table 12-21. the timing parameter values shown at the top of each timing diagram refer to delay clock periods. this is not necessarily the value written to the corresponding field in the dramtim register. the dramtim register description details the mapping between the value written and resulting number of delay clock periods. if the ready/recover mode bit is set in the bus region descriptor register, then the ready# pin is also driven during the recovery states. this can be used by an external local bus master to delay the start of the next access until the recovery period has expired. table 12-21. edo dram read access programmable timing parameters field description r2r row address to ras delay (1-4). determines number of clock delays between the assertion of the row address and ras[3:0]#. for a 66 mhz bus, this number is typically set to 1 clock for a 60 ns dram. for a heavily loaded ma[12:0] bus, or when using external buffers, this value may need to be increased. r2c ras to column address delay (1-4). determines number of clock delays between the assertion of ras[3:0]# and first column address. for a 66 mhz bus, this number is typically set to 2 clocks for a 60 ns dram. for a heavily loaded ma[12:0] bus, or when using external buffers, this value may need to be increased. c2c column address to cas delay (1-4). determines number of clock delays between assertion of the column address and cas[3:0]#. for a 66 mhz bus, this number is typically set to 1 clock for a 60 ns dram. for a heavily loaded ma[12:0] bus, or when using external buffers, this value may need to be increased. note that during a page hit when iop 480 is bus master, there is always one additional delay from column address to cas[3:0]# because bus turnaround time is required between the address and first word of read data. rcw read cas width (1-4). determines the width of each cas[3:0]# pulse. for a 66 mhz bus, this number is typically set to 1 clock. the internal memrdy# signal is asserted in the last clock period during which cas[3:0]# is asserted. prcg number of ras precharge states (1-4). determines the number of states between de-assertion of one ras[3:0]# and assertion of the next ras[3:0]#, and is used to provide adequate ras precharge time. for a 66 mhz bus, this number is typically set to 3 clocks. rrcv number of recovery states (1-4). determines the number of extra wait states inserted at the end of dram access, and is used to provide the device with adequate time to float its data output buffers. for a 66 mhz bus, this number is typically set to 2 clocks. section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-49 section 12 ? memory ctrlr timing diagram 12-38. edo dram non-page mode burst read, 4-1-1-1 wait states; r2r=1, r2c=2, c2c=1, rcw=1, rrcv=2, prcg=3; master=iop 480 timing diagram 12-39. edo dram page hit burst read, 2-1-1-1 wait states; c2c=1, rcw=1; master=iop 480 addr d1 d2 row col0 col2 col1 col3 d0 d3 addr row 0ns 50ns 100ns 150ns 200ns 25 lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[12:0] rasn# cas[3:0]# moe# blast# memrdy# (internal) addr d1 d2 col0 col2 col1 col3 d0 d3 0ns 50ns 100ns 150ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[12:0] rasn# cas[3:0]# moe# blast# memrdy# (internal) section 12 memory controller dram iop 480 data book r2.0 12-50 ? 2000 plx technology, inc. all rights reserved. timing diagram 12-40. edo dram page hit burst read, 3-2-2-2 wait states; c2c=1, rcw=1; master=iop 480 timing diagram 12-41. edo dram page miss burst read, 6-1-1-1 wait states; r2r=1, r2c=2, c2c=1, rcw=1, prcg=3; master=iop 480 addr d1 d2 col0 col2 col1 col3 d0 d3 0ns 50ns 100ns 150ns 200ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[12:0] rasn# cas[3:0]# moe# blast# memrdy# (internal) addr d1 d2 row col0 col2 col1 col3 d0 d3 0ns 50ns 100ns 150ns 200ns 250ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[12:0] rasn# cas[3:0]# moe# blast# memrdy# (internal) section 12 dram memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-51 section 12 ? memory ctrlr timing diagram 12-42. edo dram non-page mode burst read, 5-1-1-1 wait states; r2r=1, r2c=2, c2c=1, rcw=1, rrcv=2, prcg=3; master=external local bus master timing diagram 12-43. edo dram page hit burst read, 3-1-1-1 wait states; c2c=1, rcw=1; master=external local bus master addr d1 d2 row col0 col2 col1 col3 d0 d3 addr row 0ns 50ns 100ns 150ns 200ns 250ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[12:0] rasn# cas[3:0]# moe# blast# memrdy# (internal) addr d1 d2 col0 col2 col1 col3 d0 d3 0ns 50ns 100ns 150ns lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[12:0] rasn# cas[3:0]# moe# blast# memrdy# (internal) section 12 memory controller dram iop 480 data book r2.0 12-52 ? 2000 plx technology, inc. all rights reserved. timing diagram 12-44. edo dram page hit burst read, 3-2-2-2 wait states; c2c=1, rcw=2; master=external local bus master timing diagram 12-45. edo dram page miss burst read, 7-1-1-1 wait states; r2r=1, r2c=2, c2c=1, rcw=1, rrcv=2, prcg=3; master=external local bus master addr d1 d2 col0 col2 col1 col3 d0 d3 0ns 50ns 100ns 150ns 200ns 2 5 lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[12:0] rasn# cas[3:0]# moe# blast# memrdy# (internal) addr d1 d2 row col0 col2 col1 col3 d0 d3 0ns 50ns 100ns 150ns 200ns 2 5 lclk lad[31:0] lbe[3:0]# ale ads# lwr# ma[12:0] rasn# cas[3:0]# moe# blast# memrdy# (internal) section 12 signal loading memory controller iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 12-53 section 12 ? memory ctrlr 12.4 signal loading 12.4.1 sdrams signal loading: ma[13:0] ? 5 pf mras#, mcas#, mwe#, dqm[3:0]#, lclk, mcke, mcs[3:0]# ? 5 pf lad[31:0] ? 6 pf table 12-22 illustrates sdram signal loading. because the iop 480 can drive a maximum load of 50 pf, the maximum number of sdrams that can be attached without external buffering is eight. using 4m x 16 devices yields four 16 mb banks, for a total of 64 mb of memory. since inputs to sdram need to meet specified setup times, adding extra wait states does not compensate for heavily loaded signals. a slower local bus clock frequency would allow for a larger number of sdrams. at 66 mhz, the pins maximum allowable load is reduced to 25 pf; therefore, the number of sdrams that can be attached is reduced. 12.4.2 edo drams signal loading: ma[12:0] ? 5 pf ras[3:0]#, cas[3:0]#, mwe#, moe# ? 7 pf lad[31:0] ? 7 pf table 12-23 illustrates edo signal loading. because the iop 480 can drive a maximum load of 50 pf, the maximum number of edo drams that can be attached without external buffering is six. using six 4m x 16 devices yields three 16 mb banks, for a total of 48 mb of memory. if external buffers are required, then additional states in the memory access can be added, using the timing parameters listed in table 12-24. at 66 mhz, the pins maximum allowable load is reduced to 25 pf; therefore, the number of edo drams that can be attached is reduced. 12.5 overlapping address spaces the iop 480 monitors the local address bus and decodes the following types of accesses ? it is possible to program the configuration registers such that the address spaces overlap. in that case, the spaces decode with the priority listed in table 12-25. table 12-22. sdram signal loading signal min load (one bank of two x 16 devices) max load (four banks of eight x 4 devices) ma[13:0] 10 pf 160 pf mcas# / moe# 10 pf 160 pf mcke 10 pf 160 pf lclk 10 pf 160 pf ras[3:0]# / mcs[3:0]# 10 pf 40 pf cas[3:0]# / mdqm[3:0]# 5 pf 40 pf mras# 10 pf 160 pf mwe# 10 pf 160 pf lad[31:0] 6 pf 24 pf table 12-23. edo signal loading signal min load (one bank of two x 16 devices) max load (four banks of eight x 4 devices) ma[12:0] 10 pf 160 pf mcas# / moe# 14 pf 224 pf mcke 0 pf 0 pf lclk 0 pf 0 pf ras[3:0]# / mcs[3:0]# 14 pf 56 pf cas[3:0]# / mdqm[3:0]# 7 pf 56 pf mras# 0 pf 0 pf mwe# 14 pf 224 pf lad[31:0] 7 pf 28 pf section 12 memory controller overlapping address spaces iop 480 data book r2.0 12-54 ? 2000 plx technology, inc. all rights reserved. table 12-24. edo timing parameters field description r2r row address to ras delay (1-4) r2c ras to column address delay (1-4) c2c column address to cas delay (1-4) rcw read cas width (1-4) wcw write cas width (1-4) table 12-25. overlapping address spaces type of access priority configuration registers 1 direct master access 2 lcs0 memory space 3 lcs1 memory space 4 lcs2 memory space 5 lcs3 memory space 6 dram memory space 7 iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 13-1 section 13 ? i 2 o 13 intelligent i/o (i 2 o) 13.1 overview the i 2 o- ready messaging unit supplies two paths for messages, two inbound fifos to receive messages from the primary pci bus, and two outbound fifos to pass messages to the primary pci bus. refer to i 2 o architecture specification r2.0 for details. figure 13-1 and figure 13-2 illustrate information about i 2 o architecture. figure 13-1. typical i 2 o server/adapter card design figure 13-2. driver architecture compared 13.2 registers used refer to 17.2.3, ? messaging queue registers, ? on page 17-4. 13.3 inbound messages inbound messages reside in a pool of message frames (minimum 64-byte frames) allocated in the shared local bus (iop) memory. the inbound message queue is comprised of a pair of rotating fifos implemented in local memory. the inbound free queue fifo holds the message frame addresses (mfa) of available message frames in local memory. the inbound post queue fifo holds the mfa of all currently posted messages. inbound circular fifos are accessed by external pci agents through the inbound queue port location in the pci address space. the inbound queue port, when read by an external pci agent, returns the inbound free queue fifo mfa. the external pci agent places a message frame into the inbound post queue fifo by writing its mfa to the inbound queue port location. 13.4 outbound messages outbound messages reside in a pool of message frames (minimum 64-byte frames) allocated in the shared pci bus (host system) memory. the outbound message queue is comprised of a pair of rotating fifos implemented in local memory. the outbound free queue fifo holds the message frame addresses (mfa) of available message frames in system memory. the outbound post queue fifo holds the mfa of all currently posted messages. outbound circular fifos are accessed by external pci agents through the outbound queue port location in the pci address space. the outbound queue port, when read by an external pci agent, returns the outbound post queue fifo mfa. the external pci agent places free message frames into the outbound free queue fifo by writing the free mfa into the outbound queue port location. memory for the circular fifos themselves must be allocated in local (iop) memory. the base address of the queue is contained in the queue base address bits (qbar[31:20]). each fifo entry is a 32-bit data value. each read and write of the queue must be a single 32-bit access. host local bus iop local bus no hardware changes required on the host side inbound queue port outbound queue port host pci interface i/o chip i/o chip iop 480 i 2 o messaging unit host cpu pci bus host system memory message frames iop local memory message frames message queues os specific module present architecture hardware device module messaging layer api for i/o commands i 2 o architecture ddm hardware hardware osm i 2 o shell i 2 o shell optional i 2 o shell section 13 intelligent i/o (i 2 o) i 2 o pointer management iop 480 data book r2.0 13-2 ? 2000 plx technology, inc. all rights reserved. circular fifos range in size from 128 to 64k entries. all four fifos must be the same size and contiguous. therefore, the total amount of local memory needed for circular fifos ranges from 2 kb to 1 mb. fifo size is specified in the circular queue size bits (mqcr[3:1]). the starting address of each fifo is based on the queue base address and fifo size. 13.5 i 2 o pointer management fifos always reside in shared local (iop) memory and are allocated and initialized by the iop. before setting the queue enable bit (mqcr[0]=1), the local processor must initialize the following registers, with the initial offset set according to configured fifo size: inbound free head and tail pointer registers (ifhpr, iftpr) inbound post head and tail pointer registers (iphpr, iptpr) outbound free head and tail pointer registers (ofhpr, oftpr) outbound post head and tail pointer registers (ophpr, optpr) the messaging unit (mu) automatically adds the queue base address to offset in each head and tail pointer register. the software can then enable i 2 o. after initialization, the local software should not write to the pointers managed by the mu hardware. empty flags are set if the queues are disabled (mqcr[0]=0) and head and tail pointers are equal. this occurs independent of how the head and tail pointers are set. an empty flag is cleared, signifying not empty, only if the queues are enabled and pointers become not equal. if an empty flag is cleared and the queues are enabled, the empty flag is set only if the tail pointer is incremented and the head and tail pointers become equal. full flags are always cleared when the queues are disabled or the head and tail pointers are not equal. a full flag is set when the queues are enabled, the head pointer is incremented, and the head and tail pointers become equal. each circular fifo has a head pointer and a tail pointer, which are offsets from the queue base address. writes to a fifo occur at the head of the fifo and reads occur from the tail. head and tail pointers are incremented by either the local processor or mu hardware. the unit that writes to the fifo also maintains the pointer. pointers are incremented after a fifo access. both pointers wrap around to the first address of the circular fifo when they reach the fifo size, so that the head and tail pointers continuously ? chase ? each other in the circular fifo. mu wraps the pointers automatically for the pointers that it maintains. iop software must wrap the pointers that it maintains. whenever they are equal, the fifo is empty. to prevent overflow conditions, i 2 o specifies that the number of message frames allocated should be less than or equal to the number of entries in a fifo. (refer to figure 13-3 on page 13-5.) each inbound mfa is specified by i 2 o as the offset from the start of shared local (iop) memory region 0 to the start of the message frame. each outbound mfa is specified as the offset from host memory location 0x00000000h to the start of the message frame in shared host memory. because mfa is an actual address, the message frames need not be contiguous. iop allocates and initializes inbound message frames in shared iop memory using any suitable memory allocation technique. host allocates and initializes outbound message frames in shared host memory using any suitable memory allocation technique. message frames are a minimum of 64 bytes in length. i 2 o uses a ? push ? (write preferred) memory model. that means the iop writes messages and data to the shared host memory, and the host writes messages and data to shared iop memory. software should make use of burst and dma transfers whenever possible to ensure efficient use of the pci bus for message passing. table 13-1. queue starting address fifo starting address inbound free queue qbar inbound post queue qbar + (1 * fifo size) outbound post queue qbar + (2 * fifo size) outbound free queue qbar + (3 * fifo size) section 13 inbound free queue fifo intelligent i/o (i 2 o) iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 13-3 section 13 ? i 2 o additional information on message passing implementation may be found in the i 2 o architecture specification r2.0 . 13.6 inbound free queue fifo the local processor allocates inbound message frames in its shared memory and can place the address of a free (available) message frame into the inbound free queue fifo by writing its mfa into the fifo location pointed to by the queue base register + inbound free head pointer register. the local processor must then increment the inbound free head pointer register. a pci master (host or another iop) can obtain the mfa of a free message frame by reading the inbound queue port address (40h of the first pci memory base address register). if fifo is empty (no free inbound message frames are currently available, head and tail pointers are equal), the mu returns -1 (ffffffffh). if fifo is not empty (head and tail pointers are not equal), the mu reads the mfa pointed to by the queue base register + inbound free tail pointer register, returns its value and increments the inbound free tail pointer register. if the inbound free queue is not empty, and the inbound free queue prefetch enable bit is set (qsr[3]=1), the next entry in the fifo is read from the local bus into a prefetch register. the prefetch register then provides data for the next pci read from this queue, thereby reducing the number of pci wait states. (refer to figure 13-3 on page 13-5.) 13.7 inbound post queue fifo a pci master (host or another iop) can write a message into an available message frame in the shared local (iop) memory. it can then post that message by writing the message frame address (mfa) to the inbound queue port address, iqp (40h of the first pci memory base address register). when the port is written, the mu writes the mfa to the inbound post queue fifo location pointed to by the queue base register + fifo size + inbound post head pointer register. after the mu writes the mfa to the inbound post queue fifo, it increments the inbound post head pointer register. the inbound post tail pointer register points to the inbound post queue fifo location which holds the mfa of the oldest posted message. the local processor maintains the tail pointer. after a local processor reads the oldest mfa, it can remove the mfa from the inbound post queue fifo by incrementing the inbound post tail pointer register. the iop 480 asserts a local interrupt when the inbound post queue fifo is not empty. the inbound post queue fifo interrupt bit in the queue status/ control register (qsr[5]) indicates interrupt status. the interrupt clears when the inbound post queue fifo is empty, and can be masked by the inbound post queue fifo interrupt mask bit (qsr[4]). to prevent racing between the time the pci write transaction is received until the data is written in local memory and the inbound post head pointer register is incremented, any direct slave access to the iop 480 is issued a retry until the write is completed. 13.8 outbound post queue fifo a local master (iop) can write a message into an available message frame in shared host memory. it can then post that message by writing the message frame address (mfa) to the outbound post queue fifo location pointed to by the queue base register + outbound post head pointer register + (2 * fifo size). the local processor should then increment the outbound post head pointer register. a pci master can obtain the mfa of the oldest posted message by reading the outbound queue port address (44h of the first pci memory base address register). if the fifo is empty (no more outbound messages are posted, head and tail pointers are equal), the mu returns -1 (ffffffffh). if the outbound post queue fifo is not empty (head and tail pointers are not equal), the mu reads the mfa pointed to by the queue base register + (2 * fifo size) + outbound post tail pointer register, returns its value, and increments the outbound post tail pointer register. the iop 480 asserts a pci interrupt when the outbound post head pointer register is not equal to the outbound post tail pointer register. the outbound post queue fifo interrupt bit of the outbound post queue interrupt status register (opqis) indicates the interrupt status. when the pointers become equal, both the interrupt and the outbound post queue fifo interrupt bit are automatically cleared. pointers become equal when a section 13 intelligent i/o (i 2 o) outbound free queue fifo iop 480 data book r2.0 13-4 ? 2000 plx technology, inc. all rights reserved. pci master (host or other iop) reads sufficient fifo entries to empty the fifo. the outbound post queue fifo interrupt mask register (opqim) can mask the interrupt. to reduce read latency, prefetching from the tail of the queue occurs whenever the queue is not empty and the tail pointer is incremented (the queue has been read from), or when the queue is empty and the head pointer is incremented (the queue has been written to). prefetching is enabled by setting qsr[2]. when the host cpu reads the outbound post queue, the data is immediately available. 13.9 outbound free queue fifo the pci bus master (host or other iop) allocates outbound message frames in its shared memory. the pci bus master can place the address of a free (available) message frame into the outbound free queue fifo by writing a message frame address (mfa) to the outbound queue port address (44h of the first pci memory base address register). when the port is written, the mu writes mfa to the outbound free queue fifo location pointed to by the queue base register + (3 * fifo size) + outbound free head pointer register. after the mu writes the mfa to the outbound free queue fifo, it increments the outbound free head pointer register. when the iop needs a free outbound message frame, it must first check whether any free frames are available. if the outbound free queue fifo is empty (outbound free head and tail pointers are equal), the iop must wait for the host to place additional outbound free message frames in the outbound free queue fifo. if the outbound free queue fifo is not empty (head and tail pointers are not equal), the iop can obtain the mfa of the oldest free outbound message frame by reading the location pointed to by the queue base register + (3 * fifo size) + outbound free tail pointer register. after the iop reads the mfa, it must increment the outbound free tail pointer register. to prevent overflow conditions, i 2 o specifies the number of message frames allocated should be less than or equal to the number of entries in a fifo. mu also checks for overflows of the outbound free queue fifo. when the queue overflows, the mu asserts a local interrupt. the interrupt is recorded in the queue status/control register (qsr[7]). from the time the pci write transaction is received until the data is written into local memory and the outbound free head pointer register is incremented, any direct slave access to the iop 480 is issued a retry. 13.10 i 2 o enable sequence to enable i 2 o, the local processor should perform the following: initialize space 0 address and range initialize all fifos and message frame memory set the pci base class code bits (pciccr[23:16]) to be an i 2 o device with programming interface 01h set the i 2 o decode enable bit (mqcr[0]) set local init status bit to done (devinit[31]=1) note: the serial eeprom must not set the local init status bit so that the iop 480 issues retries to all pci accesses until the local init status bit is set to done by the local processor. all memory-mapped configuration registers (for example, queue ports 40h and 44h) and space 0 share the pcibar0 register. pci accesses to offset 00h-3ffh of pcibar0 result in accesses to the iop 480 internal configuration registers. accesses above offset 3ffh of pcibar0 result in local space accesses, beginning at offset 400h from the remap pci address to local address space 0 into local address space bit(s) (las0ba[31:10]). therefore, space located at offset 00h-3ffh from las0ba is not addressable from the pci bus using pcibar0. (refer to table 13-2, ? circular fifo summary, ? on page 13-6.) note: because pci accesses to offset 00h-3ffh of pcibar0 result in internal configuration accesses, inbound free mfas must be greater than 3ffh. section 13 i 2 o enable sequence intelligent i/o (i 2 o) iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 13-5 section 13 ? i 2 o figure 13-3. circular fifo operation outbound post queue fifo head pointer tail pointer incremented by local processor (outbound post queue) incremented by iop 480 hardware inbound post queue fifo head pointer tail pointer incremented by iop 480 hardware (inbound post queue) incremented by local processor inbound free queue fifo head pointer tail pointer incremented by local processor (inbound free queue) incremented by iop 480 hardware outbound free queue fifo head pointer tail pointer incremented by iop 480 hardware (outbound free queue) incremented by local processor outbound queue port write read external pci agent inbound queue port write read external pci agent local processor write read local processor write read low address local memor y high address local memory outbound queue inbound queue section 13 intelligent i/o (i 2 o) performance tuning iop 480 data book r2.0 13-6 ? 2000 plx technology, inc. all rights reserved. 13.11 performance tuning 13.11.1 pull option to reduce the number of host cycles on the pci bus, the iop 480 may optionally provide a pull option capability. the host places inbound messages in the host system memory instead of the local shared memory. then the host writes a special extended message frame address (xmfa) into the inbound queue port. xmfa contains the message host system memory address. the iop 480 then transfers the message from host system memory to its own memory. message frames must be aligned on 16-byte boundaries, thus freeing the least significant four bits of the xmfa. the setting of bit 0 differentiates an xmfa from a standard mfa, while bits [3:1] indicate the number of blocks to transfer. the block size is established with the pullblocksize parameter in the executive parameter group 0001h, and defaults to 16 bytes. extended message frames are released by the iop 480 by writing to the hostfreelist fifo structure in host memory. direct master cycles can be used to perform these writes. 13.11.2 outbound option this feature provides an enhanced mechanism for posting messages from the iop 480 to the host. normally, the iop 480 writes the mfa to the outbound post queue, and the host reads the message from local shared memory. using the outbound option feature, the iop 480 copies the message to the host system memory and then posts the message by writing to a single location in the host memory. the iop 480 provides two registers called iopoutboundindex and hostoutboundindex. the iop 480 uses the iopoutboundindex to keep track of where it writes the next mfa into the hostpostlist fifo in host memory. this index register is initialized to zero, and is incremented by four each time the iop 480 writes an mfa to the hostpostlist fifo. the hostoutboundindex register is written by the host, and indicates to the iop 480 how many of the posted messages have been processed by the host. as long as the iopoutboundindex does not equal the hostoutboundindex, the outbound post queue pci interrupt should be generated, indicating that the host needs to process more outbound messages from the iop 480. table 13-2. circular fifo summary fifo name pci port generate pci interrupt generate local interrupt head pointer maintained tail pointer maintained by inbound free queue fifo inbound queue port (host read) no no iop 480 mu hardware inbound post queue fifo inbound queue port (host write) no yes, when fifo is not empty mu hardware local processor outbound post queue fifo outbound queue port (host read) yes, when fifo is not empty no iop 480 mu hardware outbound free queue fifo outbound queue port (host write) no yes, when fifo overflows mu hardware local processor section 13 timing diagrams intelligent i/o (i 2 o) iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 13-7 section 13 ? i 2 o 13.12 timing diagrams timing diagram 13-1. i 2 o inbound write cycle eeeeeeee 7 0 f ffffffff 001005fc eeeeeeee 0000 0401 017f 0180 f 4 0 4 00030040 0ns 50ns 100ns 150ns pclk gnt0#/req# req0#/gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# devsel# lock# lclk ads# ale lad[31:0] ma[12:0] lbe[3:0]# blast# ready# section 13 intelligent i/o (i 2 o) timing diagrams iop 480 data book r2.0 13-8 ? 2000 plx technology, inc. all rights reserved. timing diagram 13-2. i 2 o outbound write cycle 00021000 ffffffff 7 0 f ffffffff 00021000 0000 0100 0401 f 0 00030044 0ns 50ns 100ns 150ns 200ns 2 pclk gnt0#/req# req0#/gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# devsel# stop# lock# lclk ads# ale lad[31:0] ma[12:0] lbe[3:0]# blast# ready# bterm# iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 14-1 section 14 ? hot swap 14 compactpci hot swap the iop 480 is a compactpci hot swap- friendly - compliant device. 14.1 overview hot swap is used for compactpci applications. hot swap functionality allows the orderly insertion and removal of boards without adversely affecting system operation. this is done for repair of faulty boards or system reconfiguration. additionally, hot swap provides access to hot swap services, allowing system reconfiguration and fault recovery to occur with no system downtime and minimum operator interaction. adapter insertion/removal logic control resides on individual adapters. the iop 480 uses two pins, enum# and ledon/ledin, to implement the hardware aspects of hot swap functionality. the iop 480 uses the hot swap capabilities register to implement the software aspects of hot swap. to avoid confusion in the industry, hot swap defines three levels of compatibility: hot swap- capable devices contain the minimum requirements to operate in a hot swap environment hot swap- friendly devices contain additional functions to ease the designer ? s job hot swap- ready devices contain all necessary functions for hot swap hot swap- capable requirements are mandatory for a device to be used in a hot swap environment. these requirements are attributes for which a system user must compensate using external circuitry, as follows: pci local bus specification r2.1 compliance tolerate vcc from early power tolerate asynchronous reset tolerate precharge voltage i/o buffers must meet modified v/i requirements limited i/o pin leakage at precharge voltage hot swap- friendly silicon includes all required capable functions and adds others from the following list. the iop 480 integrated these functions into the pci silicon, thereby reducing the amount and cost of required external circuitry. incorporates hot swap control/status register (hs_csr) ? contained within the configuration space. incorporates an extended capability pointer (ecp) mechanism ? it is required that software retain a standard method of determining if a specific function is designed in accordance with the specification. the capabilities pointer is located within standard csr space, using a bit in the pci status register (offset 04h). incorporates remaining software connection control resources. provides enum#, hot swap switch, and the blue led. the iop 480 is a hot swap- friendly pci silicon device. the iop 480 incorporates all compliant functions defined by the compactpci hot swap specification. the iop 480 incorporates enum#, ledon/ledin, and hot swap capabilities registers ? hscapid, hsnext, and hscsr. 14.2 controlling connection processes the following sections are excerpts from the picmg 2.1, compactpci hot swap specification, r1.0 . refer to the specification for more details. 14.2.1 hardware connection control hardware control provides a means for the platform to control the hardware connection process. the signals listed in the following sections must be supported on all hot swap boards for interoperability. implementations on different platforms may vary. 14.2.1.1 board slot control bd_sel# is one of the shortest pins. it is driven low to enable power-on. for systems not implementing hardware control, it is grounded on the backplane. section 14 compactpci hot swap controlling connection processes iop 480 data book r2.0 14-2 ? 2000 plx technology, inc. all rights reserved. systems implementing hardware control radially connect bd_sel# to a hot swap controller (hsc). the controller terminates the signal with a weak pull-down. the controller can detect board present when the board pull-up overrides the pull-down. hsc can then control the power-on process by driving bd_sel# low. figure 14-1. redirection of bd_sel# 14.2.1.2 board healthy a second radial signal is used to acknowledge board health. it signals that a board is suitable to be released from reset and allowed onto the pci bus. minimally, this signal must be connected to the card ? s power controller ? power good ? status line. use of healthy# can be expanded for applications requiring additional conditions to be met for the board to be considered healthy. on platforms that do not use hardware connection control, this line is not monitored. platforms implementing this signaling route these signals radially to a hot swap controller. figure 14-2. board healthy 14.2.1.3 platform reset reset (pci_rst#), as defined by compactpci specification , is a bused signal on the backplane, driven by the host. platforms may implement this signal as a radial signal from the hot swap controller to further control the electrical connection process. to maintain function of the bused signal, platforms that do this must or the host reset signal with the slot-specific signal. locally, boards must not come out of reset until the h1 state is reached (healthy), but they must also honor the backplane reset. the local board reset (local_pci_rst#) must be the logical or of these two conditions. local_pci_rst# is connected to the iop 480 rst# input pin. during a bios voltage precharge and platform reset, in insertion and extraction procedures, all pci i/o buffers must be in a high impedance state. the iop 480 supports this condition any time the host rst# is asserted ( pci r2.1 or better). to protect the local board components from early power, the iop 480 floats the local bus i/os. the test pin can be used to perform the high impedance condition on the local bus. both the rst# and test signals can be simultaneously asserted. the test signal is de-asserted some time before the host rst# is de-asserted to ensure the iop 480 asserts the lreseto# signal to complete a reset task of the local board. figure 14-3. pci reset 14.2.2 software connection control software connection control provides a means to control the software connection process. resources on the hot swap board facilitate software connection control. access to these resources occurs by way of the bus, using pci protocol transfers (in-band). these resources consist of four elements: enum# driven active indicates the need to change the state of the hot swap board a switch, tied to the ejector, indicates the intent to remove a board led indicates the status of the software connection process control/status register allows the software to interact with these resources on pwr on present vio on bd_sel# vio hsc no hardware control hardware control platform | board platform | board bd_sel# power circuitry power circuitry healthy vio nc hlty hsc no hardware control hardware control platform | board platform | board power circuitry power circuitry host no hardware control host hsc hardware connection control platform | board healthy # platform | board pci_rst# healthy # local_ pci_rst# local_ pci_rst# pci_rst# section 14 controlling connection processes compactpci hot swap iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 14-3 section 14 ? hot swap 14.2.2.1 ejector switch and blue led a microswitch (switch), located in the card-ejector mechanism of the hot swap compactpci board, is used to signal the impending removal of a board. this signal asserts enum#. the operator normally activates the switch, waits for the led illumination to indicate it is okay to remove the board, and then removes the board. the iop 480 implements control logic for both the microswitch and the blue led in one pin (ledon/ledin). when the ejector is opened or closed, the switch bounces for a time. the iop 480 uses internal debounce circuitry to clean the signal before the remainder of hot swap logic acknowledges it. the state of the switch is acknowledged six times, at 1 ms intervals, before it is assumed closed or open. the blue ? status ? led, located on the front of the hot swap compactpci board, is illuminated when it is permissible to remove a board. the hardware connection layer provides protection for the system during all insertions and extractions. this led indicates the system software is in a state that tolerates board extraction. upon insertion, the led is automatically illuminated by the hardware until the hardware connection process completes. the led remains off until the software uses it to indicate extraction is once again permitted. the iop 480 uses a tri-state i/o pin to drive the external led. this pin is time-division multiplexed (tdm) for input and output functionality. when an output, it drives the external led. the led state is driven from the led software on/off switch bit (hscsr[3]). when used as an input, it acknowledges the state of the ejector handle. with the implementation of tdm, this pin is usually driving the led. a small portion of time is dedicated to acknowledging ejector status. 14.2.2.2 enum# enum# is provided to notify the host cpu that a board has been freshly inserted or is about to be removed. this signal informs the cpu that configuration of the system has changed. the cpu then performs any necessary maintenance such as installing a device driver upon board insertion, or quiescing a device driver prior to board extraction. enum# is an open collector bused signal with a pull-up on the host. it may drive an interrupt (preferred) or be polled by the system software at regular intervals. the compactpci hot-plug system driver on the system host manages the enum# sensing. full hot swap boards assert enum# until serviced by the hot-plug system driver. when a board is inserted into the system and reset, the iop 480 acknowledges the state of the ejector switch. if this switch is open (ejector closed) the iop 480 asserts enum# interrupt and sets the enum# status indicator for board insertion bit (hscsr[7]). once the host cpu has installed the proper drivers, it can logically include this board by clearing the interrupt. when a board is about to be removed, the iop 480 acknowledges the ejector switch is closed (ejector open), asserts enum# interrupt and sets the enum# status indicator for board removal bit (hscsr[6]). the host then logically removes the board and turns on the led. the operator can then remove the board completely. 14.2.2.3 hot swap control/status register (hscsr) the iop 480 supports hot swap directly, as a control/status register is provided in configuration space. this register is accessed through the pci extended capabilities pointer (ecp) mechanism. the hot swap control/status register (hscsr) provides status read-back for the hot-plug system driver to determine which board is driving enum#. this register is also used to control the hot swap status led on the front panel of the board, and to de-assert enum#. section 14 compactpci hot swap controlling connection processes iop 480 data book r2.0 14-4 ? 2000 plx technology, inc. all rights reserved. 14.2.2.3.1 hot swap capabilities register hot swap id. bits [7:0] (hscapid[7:0]; pci:54h, loc:354h). these bits are set to a default value of 00h. user must set the bits to 06h for the bits to be valid. next_cap pointer. bits [15:8] (hsnext[7:0]; pci:55h, loc:355h). these bits point to the next new capability structure or are set to 0, if this is the last capability in the structure. hot swap control. bits [23:16] (hscsr[7:0]; pci:56h, loc:356h). this eight-bit control register is defined as follows (refer to table 14-1). register 14-1. hot swap capabilities register 31 24 23 16 15 8 70 reserved hot swap control (06h) next_cap pointer hot swap id (00h) table 14-1. hot swap control bit description 23 enum# status ? insertion (1 = board is inserted). 22 enum# status ? removal (1 = board is being removed). 21 not used. 20 not used. 19 led state (1 = led on, 0 = led off). 18 not used. 17 enum# interrupt enable (1 = de-assert, 0 = enable interrupt). 16 not used. iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 15-1 section 15 ? vpd 15 vital product data 15.1 overview the vital product data (vpd) function in pci specification r2.2 defines a new location and access method. it also defines the read only and read/write bits. currently a device id, vendor id, revision id, class code, subsystem id, and subsystem vendor id are required in the configuration space header and are used for basic identification of the device and device configuration. although this information allows device configuration, it is not sufficient to allow a device to be uniquely identified. with the addition of vpd, optional information is provided allowing devices to be uniquely identified and tracked. these additional bits enable current and/or future support tools and reduce total pc and system cost of ownership. this provides an alternate access method other than expansion rom for vpd. vpd is stored in an external serial eeprom, which is accessed using the capabilities list function. 15.2 vpd registers vpd id. (vpd_cap[7:0]; pci:58h, loc:358h). value of 3h is assigned by the pci sig. the vpd id is hardcoded. next_cap pointer. (vpd_cap[15:8]; pci:58h, loc:358h). either points to next new capability structure, or set to 0 if this is the last one. the iop 480 defaults to 0h. value can be overwritten from the local bus. vpd address. (vpd_cap[30:16]; pci:58h, loc:358h). vpd byte address accessed. all accesses are 32-bit wide; bits [17:16] must be set to 0, with the maximum serial eeprom size being 4k bits. bits [30:28] are ignored. note: address size allows for a 4k bit serial eeprom. f flag. (vpd_cap[31]; pci:58h, loc:358h). flag used to indicate when a serial eeprom data operation is complete. for write cycles, the four bytes of data are first written into the vpd data bits, after which the vpd address is written at the same time the f flag is set to 1. the f flag clears when a serial eeprom data transfer completes. for read cycles, the vpd address is written at the same time the f flag is cleared to 0. the f flag is set when four bytes of data are read from the serial eeprom. vpd data. (vpd_data[31:0]; pci:5ch, loc:35ch). vpd data is written or read through this register. four bytes are always transferred between this register and the serial eeprom. for vpd_data[31:16], these bits go into address n (specified in vpd_cap[30:16]). for vpd_data[15:0], these bits go into address n+1. note: vpd data bits [31:16] correspond to vpd word at the address specified by the vpd address register. 15.2.1 vpd registers 15.3 serial eeprom vpd partitioning to support vpd, the serial eeprom is partitioned into read only and read/write sections. register 15-1. vpd registers 31 30 16 15 8 7 0 f flag vpd address next_cap pointer (0h) vpd id (3h) vpd data section 15 vital product data sequential read area iop 480 data book r2.0 15-2 ? 2000 plx technology, inc. all rights reserved. 15.4 sequential read area at power-up, the first 2048 bits, 256 bytes of the serial eeprom contain read-only information. the read- only portion of the serial eeprom is loaded into the iop 480. this occurs once after power-on, or by writing to the reload configuration registers bit (devinit[29]) using a sequential read command to the serial eeprom. 15.5 random read and write area the iop 480 can read and write the read/write portion of the serial eeprom. serial eeprom locations starting at the address specified by the serial eeprom protected area bits (devinit[14:8]) are read/write. this register is loaded upon power-on and can be written with any value starting at location 0. this provides the capability of writing the entire serial eeprom. writes to the serial eeprom are comprised of the following three commands: write enable write, followed by write data write disable this is done to ensure against accidental writing to the serial eeprom. random cycles allow vpd information to be written and read at any time. section 15 timing diagrams vital product data iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 15-3 section 15 ? vpd 15.6 timing diagrams timing diagram 15-1. register write to start vpd write 5a5a5a5a 5 20000358 8010003 0000 f 0 f 0ns 50ns 100ns 150ns 200ns pclk gnt0#/req# req0#/gnt# frame# ad[31:0] c/be[3:0]# irdy# trdy# devsel# stop# lock# lclk ads# ale lad[31:0] ma[12:0] lbe[3:0]# blast# ready# bterm# lwr# rd# lholdack0/ldreq lholdack1/breq lholdreq0/lholdack lholdreq1 llock# section 15 vital product data timing diagrams iop 480 data book r2.0 15-4 ? 2000 plx technology, inc. all rights reserved. timing diagram 15-2. register read to show completion of vpd read 5a5a5a5a 5 2000358 ffffffff 80100003 ffffffff f 0 f 0ns 100ns 200ns 300ns pclk gnt0#/req# req0#/gnt# frame# ad[31:0] c/be[3:0]# irdy# irdy#1 trdy# devsel# lock# lclk ads# ale lad[31:0] ma[12:0] lbe[3:0]# blast# ready# bterm# lwr# rd# lholdack0/ldreq lholdack1/breq lholdreq0/lholdack lholdreq1 llock# iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 16-1 section 16 ? power mgmt 16 power management 16.1 overview the pci bus power management interface specification, r1.1 defines four power states for pci functions ? d 0 , d 1 , d 2 , and d 3 . states d 0 and d 3 are required, while states d 1 and d 2 are optional. state d 0 represents the highest power consumption and state d 3 the least. while the iop 480 supports the message passing of these power management states, it is the responsibility of software to implement the actual power savings. d 0 (uninitialized) ? enters this state from a power-on reset or from state d 3 . must be initialized to function properly. d 0 (active) ? all functions active. d 1 ? uses less power than state d 0 , and more than state d 2 . no pci bus mastering cycles allowed. d 2 ? uses less power than state d 1 and more power than state d 3 . pci bus mastering cycles are not allowed. clock may be stopped. d 3hot ? uses lower power than any other state. supports pci configuration cycles to function if a clock is running. supports wakeup event from function, but not standard pci interrupts. when programmed for state d 0 , an internal soft reset occurs. all content is lost in this state. d 3cold ? no power. supports bus reset only. all context is lost in this state. 16.2 functional description the pci status register (pcisr) and the capability list pointer register (cap_ptr) indicate whether a new capability (the power management function) is available. the capabilities list status bit (pcisr[4]) enables the pci bios to determine whether the iop 480 supports capabilities list features. this bit is writeable from the local bus, and can be read from the local and pci buses. cap_ptr provides an offset into pci configuration space, indicating the starting location of the first item in a capabilities list. the power management capability id register (pmcapid) specifies the power management capability id, 01h, assigned by the pci sig. the power management next capability pointer register (pmnext) points to the first location of the next item in the capabilities linked list. if power management is the last item in the list, then this register should be set to 0. the default value for the iop 480 is 54h (hot swap). for the iop 480 to change the power state and assert pme#, the local host or pci host should set the pme_en bit (pmcsr[8]=1). the local host then determines to which power state the backplane should change by reading the power_state bits (pmcsr[1:0]). the local host can either be the internal iop 480 cpu or an external mastering device. the local host sets up the following: d 2 _support and d 1 _support bits (pmc[10:9]) are used by the local host to identify power state support pme_support bits (pmc[14:11]) are used by the iop 480 to identify the pme# support corresponding to a given power state (pmcsr[1:0]) the local host then sets the pme_status bit (pmcsr[15]=1) and the iop 480 asserts pme#. to clear the pme# interrupt status bit, the pci host must write a 1 to the pme_status bit (pmcsr[15]=1). to disable the pme# interrupt signal, either host can write a 0 to the pme_en bit (pmcsr[8]=0). into is asserted each time the power state in the pmcsr register changes. it is up to the local host to implement the power savings mode request. a transition from state 11 (d 3hot ) to state 00 (d 0 ) causes a soft reset. this should be initiated only from the pci bus because the local bus interface is reset during a soft reset (pmcsr[1:0]). all context is lost in this state. the data_scale bits (pmcsr[14:13]) indicate the scaling factor to use when interpreting the value of the power management data bits (pmdata[7:0]). the value and meaning of these bits depend upon the data value specified in the data_select bits (pmcsr[12:9]). the data_scale bit value is unique for each data_select bit. for data_select values from 8 to 15, (pmcsr[12:9]=1000 to pmcsr[12:9]=1111), the data_scale bits always return a zero (pmcsr[14:13]=0). this data is optional. section 16 power management system changes power mode example iop 480 data book r2.0 16-2 ? 2000 plx technology, inc. all rights reserved. pmdata provides operating data, such as power consumed or heat dissipation. this data is optional. 16.3 system changes power mode example 1. the host writes to the iop 480 pmcsr register to change the power states. 2. the iop 480 sends a local interrupt (into) to a local cpu (lcpu). 3. the lcpu has 200 ms to read the power management information from the iop 480 pmcsr register to implement the power saving function. 4. after the lcpu implements the power saving function, the iop 480 disables all direct slave accesses and pci interrupt output (inta#). in addition, the bios disables the iop 480 master enable bit (pcicr[2]). notes: in power saving mode, all pci and local configuration cycles are granted. the iop 480 automatically performs a soft reset to a local bus on d 3 -to-d 0 transitions. 16.4 wake-up request example 1. the add-in card (with a iop 480 chip installed) is in a powered-down state. 2. the local cpu performs a write to the iop 480 power management control/status register (pmcsr[1:0]) to request a change in power state. 3. when the request is detected, the iop 480 drives pme# out to the pci bus. 4. the pci host accesses the iop 480 pmcsr register to disable the pme# output signal and restores the iop 480 to the d 0 power state. 5. the iop 480 completes the power management task by issuing the local interrupt (into) to the local cpu, indicating that the power mode has changed. 16.5 power consumption power consumption features include: typical full operational power at 66 mhz local and 33 mhz pci ? 600 mw power with clock, but not with other ongoing operations ? 150 mw power without clock ? 6 mw iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-1 section 17 ? registers 17 register summary 17.1 internal register access the iop 480 provides several internal registers, allowing for maximum flexibility in the bus interface design and performance. these registers are accessible from the pci bus, the internal iop 480 cpu, or the local bus. they include the following: pci configuration registers local configuration registers memory controller registers dma registers mailbox registers pci-to-local and local-to-pci doorbell registers messaging queue registers (i 2 o) power management registers hot swap registers vpd registers runtime registers figure 17-1 illustrates how these registers are accessed. figure 17-1. iop 480 internal register access the iop 480 pci configuration registers can be accessed from the pci bus with a configuration type 0 or type 1 cycle. all other iop 480 internal registers can be accessed from pci by hitting space zero. space zero begins at the address in the pci base address 0 (pcibar0[31:10]) for the iop 480 memory-mapped configuration register. the internal registers take up 1k of space 0. pci read or write accesses to iop 480 registers can be byte, word, or lword accesses. all pci memory accesses to iop 480 registers can be burst or non-burst accesses. all iop 480 internal registers can be accessed from the local bus (or the iop 480 cpu) by hitting the local configuration space. this space starts at the value programmed into cfgba which, by default, is 0x5000-0000. accessing reserved registers returns 0 for reads and has no affect on writes. table 17-1 lists the symbols used for identifying read and write information in the following register listings. note: unused bits should always be written with 0. set clear local bus master pci bus master local configuration registers pci configuration registers dma registers iop 480 mailbox registers pci-to-local doorbell register local-to-pci doorbell register messaging queue registers set clear power management registers hot swap registers vpd registers runtime registers pci interrupt memory controller registers local interrupt table 17-1. read/write symbols used in register listings symbol description ppci bus l local bus e serial eeprom section 17 register summary register address mapping iop 480 data book r2.0 17-2 ? 2000 plx technology, inc. all rights reserved. 17.2 register address mapping 17.2.1 configuration register base addresses the iop 480 contains six groups of configuration registers. table 17-2 lists the base address of each group. table 17-2. configuration register base addresses register set pci configuration offset pci base address 0 (pcibar0) offset local address offset pci configuration registers 00h ? 300h messaging queue registers ? 000h 000h local configuration registers ? 080h 080h memory controller registers ? 100h 100h runtime registers ? 180h 180h dma registers ? 200h 200h section 17 register address mapping register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-3 section 17 ? registers 17.2.2 pci configuration registers table 17-3. pci configuration registers pci offset (cfg) local offset from cfgba mnemonic description write 31 30 24 23 16 15 8 70 00h 300h pci_pciid device id vendor id l, e 04h 304h pci_pcicr status command p, l 08h 308h pci_pcirev class code revision id l, e 0ch 30ch pci_pciclsr bist header type pci latency timer cache line size p, l 10h 310h pci_pcibar0 pci base address 0 for memory-mapped configuration registers and local address space 0 p, l 14h 314h pci_pcibar1 pci base address 1 for local address space 1 p, l 18h 318h pci_pcibar2 pci base address 2 for local address space 2 p, l 1ch 31ch ? unused base address ? 20h 320h ? unused base address ? 24h 324h ? unused base address ? 28h 328h ? cardbus cis pointer ( not supported ) ? 2ch 32ch pci_pcisubid subsystem id subsystem vendor id l, e 30h 330h pci_pcierbar pci base address for local expansion rom p, l 34h 334h pci_pcicapptr reserved cap_pointer l, e 38h 338h ? reserved ? 3ch 33ch pci_pciilr max_lat min_gnt interrupt pin interrupt line p, l, e 40h 340h pmcap power management capabilities next_cap pointer capability id l, e 44h 344h pmcsr data bridge extensions power management csr p, l 48h 348h pmscale reserved power management scale values l, e 4ch 34ch pwrcon power consumed l, e 50h 350h pwrdis power dissipated l, e 54h 354h hs0 reserved hot swap control next_cap pointer hot swap id l, e 58h 358h vpdcap flag vpd address next_cap pointer vpd id l 5ch 35ch vpddata vpd data l 60h- ffh 360h- 3ffh ? reserved ? section 17 register summary register address mapping iop 480 data book r2.0 17-4 ? 2000 plx technology, inc. all rights reserved. 17.2.3 messaging queue registers notes: when i 2 o messaging is enabled (mqc[0]=1), a pci master (host or another iop) uses the inbound queue port to read messaging frame addresses (mfas) from the inbound free queue and to write mfas to the inbound post queue. it uses the outbound queue port to re ad mfas from the outbound post queue and to write mfas to the outbound free queue. each inbound mfa is specified by i 2 o as the offset from the pci base address 0 (programmed in register pcibar0 at offset 10h) to the start of the message frame. this means that all inbound message frames should reside in pci base address 0 memory space. each outbound mfa is specified by i 2 o as the offset from system address 0x00000000h. the outbound mfa is the physical 32-bit address of the frame in shared pci system memory. the inbound and outbound queues reside in the local address space. table 17-4. messaging queue registers pci offset from pcibar0 local offset from cfgba mnemonic register description write 000h 000h mqcr messaging queue configuration p, l 004h 004h qbar queue base address p, l 008h 008h ifhpr inbound free head pointer p, l 00ch 00ch iftpr inbound free tail pointer p, l 010h 010h iphpr inbound post head pointer p, l 014h 014h iptpr inbound post tail pointer p, l 018h 018h ofhpr outbound free head pointer p, l 01ch 01ch oftpr outbound free tail pointer p, l 020h 020h ophpr outbound post head pointer p, l 024h 024h optpr outbound post tail pointer p, l 028h 028h qsr queue status/control p, l 02ch 02ch ? reserved ? 030h 030h opqis outbound post queue interrupt status ? 034h 034h opqim outbound post queue interrupt mask p, l 038h 038h ? reserved ? 03ch 03ch ? reserved ? 040h ? iqpr inbound queue port p 044h ? oqpr outbound queue port p 048h-04ch 048h-04ch ? reserved ? 050h 050h hostoutidx host outbound index p, l 054h 054h iopoutidx iop outbound index p, l 058h-07fh 058h-07fh ? reserved ? section 17 register address mapping register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-5 section 17 ? registers 17.2.4 local configuration registers table 17-5. local configuration registers pci offset from pcibar0 local offset from cfgba mnemonic register description write 080h 080h devinit device initialization p, l, e 084h 084h locctl local bus control p, l, e 088h 088h loctmo local bus timeout p, l, e 08ch 08ch loctmr local timers p, l, e 090h 090h larbr local/dma arbitration p, l, e 094h 094h bigend big/little endian p, l, e 098h 098h pcictl pci bus control p, l, e 09ch-09fh 09ch-09fh ? reserved ? 0a0h 0a0h las0rr range for memory-mapped configuration registers and pci-to-local address space 0 p, l , e 0a4h 0a4h las0ba local base address (remap) for pci to local address space 0 p, l, e 0a8h 0a8h las1rr range for pci-to-local address space 1 p, l, e 0ach 0ach las1ba local base address (remap) for pci to local address space 1 p, l, e 0b0h 0b0h las2rr range for pci-to-local address space 2 p, l, e 0b4h 0b4h las2ba local base address (remap) for pci to local address space 2 p, l, e 0b8h-0bfh 0b8h-0bfh ? reserved ? 0c0h 0c0h eromrr range for pci-to-local expansion rom p, l, e 0c4h 0c4h eromba local base address (remap) for pci-to-local expansion rom p, l, e 0c8h 0c8h dmrr range for direct master-to-pci p, l, e 0cch 0cch dmlbam local base address for direct master-to-pci memory p, l, e 0d0h 0d0h dmpbam pci base address (remap) for direct master-to-pci (lower 32 bits) p, l , e 0d4h 0d4h dmdac pci base address (remap) for direct master-to-pci (upper 32 bits) p, l , e 0d8h 0d8h dmlbai local base address for direct master-to-pci io/cfg p, l, e 0dch 0dch dmcfga pci configuration address register for direct master-to-pci io/cfg p, l , e 0e0h 0e0h cfgba local base address for configuration register access p, l, e 0e4h 0e4h uartba iop 480 cpu base address for uart access p, l, e 0e8h 0e8h plxid plx device and vendor id ? 0ech 0ech plxrev plx silicon revision ? 0f0h-0ffh 0f0h-0ffh ? reserved ? section 17 register summary register address mapping iop 480 data book r2.0 17-6 ? 2000 plx technology, inc. all rights reserved. 17.2.5 memory controller registers table 17-6. memory controller registers pci offset from pcibar0 local offset from cfgba mnemonic register description write 100h 100h lcs0brd lcs0# bus region descriptor p, l, e 104h 104h lcs0wt lcs0# write timing p, l, e 108h 108h lcs0rt lcs0# read timing p, l, e 10ch 10ch lcs0base lcs0# base address p, l, e 110h 110h lcs0range lcs0# range p, l, e 114h 114h lcs1brd lcs1# bus region descriptor p, l, e 118h 118h lcs1wt lcs1# write timing p, l, e 11ch 11ch lcs1rt lcs1# read timing p, l, e 120h 120h lcs1base lcs1# base address p, l, e 124h 124h lcs1range lcs1# range p, l, e 128h 128h lcs2brd lcs2# bus region descriptor p, l, e 12ch 12ch lcs2wt lcs2# write timing p, l, e 130h 130h lcs2rt lcs2# read timing p, l, e 134h 134h lcs2base lcs2# base address p, l, e 138h 138h lcs2range lcs2# range register p, l, e 13ch 13ch lcs3brd lcs3# bus region descriptor p, l, e 140h 140h lcs3wt lcs3# write timing p, l, e 144h 144h lcs3rt lcs3# read timing p, l, e 148h 148h lcs3base lcs3# base address p, l, e 14ch 14ch lcs3range lcs3# range p, l, e 150h 150h drambrd dram bus region descriptor p, l, e 154h 154h dramctl dram control p, l, e 158h 158h draminit dram initialization p, l, e 15ch 15ch dramtim dram timing parameters p, l, e 160h 160h drambase dram base address p, l, e 164h 164h dramrange dram range p, l, e 168h 168h dfltbrd default bus region descriptor p, l, e 16ch-17fh 16ch-17fh ? reserved ? section 17 register address mapping register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-7 section 17 ? registers 17.2.6 runtime registers table 17-7. runtime registers pci offset from pcibar0 local offset from cfgba mnemonic register description write 180h 180h mbox0 mailbox register 0 p, l, e 184h 184h mbox1 mailbox register 1 p, l, e 188h 188h mbox2 mailbox register 2 p, l 18ch 18ch mbox3 mailbox register 3 p, l 190h 190h mbox4 mailbox register 4 p, l 194h 194h mbox5 mailbox register 5 p, l 198h 198h mbox6 mailbox register 6 p, l 19ch 19ch mbox7 mailbox register 7 p, l 1a0h 1a0h p2ldbell pci-to-local doorbell register p, l 1a4h 1a4h l2pdbell local-to-pci doorbell register p, l 1a8h 1a8h ? reserved ? 1ach 1ach ? reserved ? 1b0h 1b0h pintstat pci interrupt status p, l 1b4h 1b4h pintenb pci interrupt enable p, l 1b8h 1b8h lintstat local interrupt status p, l 1bch 1bch lintenb local interrupt enable p, l 1c0h 1c0h pabtadr pci abort address p, l 1c4h-1ffh 1c4h-1ffh ? reserved ? section 17 register summary register address mapping iop 480 data book r2.0 17-8 ? 2000 plx technology, inc. all rights reserved. 17.2.7 dma registers 17.2.8 serial eeprom loading sequence note: lword = 32 bits. table 17-8. dma registers pci offset from pcibar0 local offset from cfgba mnemonic register description write 200h 200h c0mode ch 0 mode p, l 204h 204h c0csr ch 0 control/status p, l 208h 208h c0count ch 0 transfer count, valid bit p, l 20ch 20ch c0pciladr ch 0 pci address (lower 32 bits) p, l 210h 210h c0locadr ch 0 local address p, l 214h 214h c0descptr ch 0 descriptor pointer p, l 218h 218h c0pcihadr ch 0 pci address (upper 32 bits) p, l 21ch 21ch c0thres ch 0 threshold register p, l 220h 220h c1mode ch 1 mode p, l 224h 224h c1csr ch 1 control/status p, l 228h 228h c1count ch 1 transfer count, valid bit p, l 22ch 22ch c1pciladr ch 1 pci address (lower 32 bits) p, l 230h 230h c1locadr ch 1 local address p, l 234h 234h c1descptr ch 1 descriptor pointer p, l 238h 238h c1pcihadr ch 1 pci address (upper 32 bits) p, l 23ch 23ch c1thres ch 1 threshold register p, l 240h 240h c2mode ch 2 mode p, l 244h 244h c2csr ch 2 control/status p, l 248h 248h c2count ch 2 transfer byte count p, l 24ch 24ch c2srcadr ch 2 source address p, l 250h 250h c2destadr ch 2 destination address p, l 254h-27fh 254h-27fh ? reserved ? table 17-9. serial eeprom loading sequence local offset from cfgba registers lword(s) 84h-e4h local configuration 24 100h-168h memory controller 27 180h-184h mailboxes 2 300h, 308h, 32ch, 334h, 33ch, 340h, 348h, 34ch, 350h, 354h pci configuration 10 80h first local configuration 1 total = 64 words = 256 bytes = 2048 bits section 17 pci configuration registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-9 section 17 ? registers 17.3 pci configuration registers registers may be written to or read from in byte (8-bit), word (16-bit) or lword (32-bit) accesses. register 17-1. (pcivid; pci:00h, loc:300h) pci vendor id bit description read write value after reset 15:0 vendor id. identifies the device manufacturer. defaults to the pci sig-issued vendor id of plx (10b5h) if no serial eeprom is present. p, l l, e 10b5h register 17-2. (pcidid; pci:02h, loc:302h) pci device id bit description read write value after reset 15:0 device id. identifies the particular device. defaults to the plx part number for the iop 480 (0480h) if no serial eeprom is present. p, l l, e 0480h register 17-3. (pcicr; pci:04h, loc:304h) pci command bit description read write value after reset 15:10 reserved. p, l n o 0 h 9 fast back-to-back enable. indicates the type of fast back-to-back transfers a master can perform on the bus. value of 0 indicates fast back-to-back transfers can occur only to the same agent as the previous cycle. p, l n o 0 8 serr# enable. value of 0 disables the serr# driver. value of 1 enables the serr# driver. p, l p, l 0 7 step enable. controls whether the device does address/data stepping. value of 0 indicates the device never does stepping. note: hardcoded to 0. p, l n o 0 6 parity error response. value of 0 indicates a parity error is ignored and operation continues. value of 1 indicates a parity checking is enabled. p, l p, l 0 5 vga palette snoop. not supported. p, l n o 0 4 memory write/invalidate. allows the iop 480 to generate memory write and invalidate cycles on the pci bus. (refer to dmpbam[7], c0mode[13], and c1mode[13].) p, l p, l 0 3 special cycle. not supported. p, l n o 0 2 master enable. value of 0 disables the device from generating bus master accesses. value of 1 allows the device to behave as a bus master. p, l p, l 0 1 memory space. value of 0 disables the device from responding to memory space accesses. value of 1 allows the device to respond to memory space accesses. p, l p, l 0 0 i/o space. value of 0 disables the device from responding to i/o space accesses. value of 1 allows the device to respond to i/o space accesses. p, l p, l 0 section 17 register summary pci configuration registers iop 480 data book r2.0 17-10 ? 2000 plx technology, inc. all rights reserved. register 17-4. (pcisr; pci:06h, loc:306h) pci status bit description read write value after reset 15 parity error detected. value of 1 indicates the iop 480 detected a pci bus parity error, although parity error handling was disabled (pcicr[6]=0). one of three conditions can cause this bit to be set. 1) the iop 480 detected a parity error during a pci address phase; 2) the iop 480 detected a data parity error when it was the target of a write; 3) the iop 480 detected a data parity error when performing a master read operation. writing a 1 to this bit clears the bit. p, l p, l / c l r 0 14 signaled system error. value of 1 indicates the iop 480 reported a system error on the serr# signal. writing a 1 to this bit clears the bit. p, l p, l / c l r 0 13 received master abort. value of 1 indicates the iop 480 received a master abort signal. writing a 1 to this bit clears the bit. p, l p, l / c l r 0 12 received target abort. value of 1 indicates the iop 480 received a target abort signal. writing a 1 to this bit clears the bit. p, l p, l / c l r 0 11 target abor t. value of 1 indicates the iop 480 signaled a target abort. writing a 1 to this bit clears the bit. p, l p, l / c l r 0 10:9 devsel timing. indicates the timing for devsel# assertion. value of 01 is medium. p, l n o 0 1 8 master data parity error detected. value of 1 indicates a data parity error occurred while the iop 480 was bus master. this bit is set when three conditions are met: 1) the iop 480 asserted perr# or observed perr# asserted; 2) the iop 480 was the bus master for the operation in which the error occurred; 3) the parity error response bit in the command register is set (pcicr[6]=1). writing a 1 to this bit clears the bit. p, l p, l / c l r 0 7 fast back-to-back capable. value of 1 enables the iop 480 to accept fast back-to-back transactions. p, l n o 1 6 user-definable features. value of 0 indicates the iop 480 does not support user-definable features. value of 1 indicates the iop 480 does support user-definable features. can only be written from the local bus and is read-only from the pci bus. p, l local 0 5 reserved. p, l n o 0 4 capabilities list status. value of 0 indicates the iop 480 does not support capabilities list features. value of 1 indicates the iop 480 does support capabilities list features. p, l local 1 3:0 reserved. p, l n o 0 h register 17-5. (pcirev; pci:08h, loc:308h) pci revision id bit description read write value after reset 7:0 revision id. the iop 480 silicon revision. p, l l, e current revision section 17 pci configuration registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-11 section 17 ? registers register 17-6. (pciccr; pci:09h-0bh, loc:309h-30bh) pci class code bit description read write value after reset 23:16 base class code. values: 06h = bridge device 0eh = intelligent i/o controller p, l l , e 0 e h 15:8 subclass code. values: 00h = i 2 o device 80h = other bridge device p, l l , e 0 0 h 7:0 register level programming interface. value: 00h = messaging queue ports at 40h, 44h. p, l l , e 0 0 h register 17-7. (pciclsr; pci:0ch, loc:30ch) pci cache line size bit description read write value after reset 7:0 cache line size. system cache line size, in units of 32-bit lwords. p, l p, l 0h register 17-8. (pciltr; pci:0dh, loc:30dh) pci latency timer bit description read write value after reset 7:0 pci latency timer. specifies, in units of pci bus clocks, the amount of time the iop 480, as a bus master, can burst data on the pci bus. p, l p, l 0 h register 17-9. (pcihtr; pci:0eh, loc:30eh) pci header type bit description read write value after reset 7 header type. value of 0 indicates a single function. value of 1 indicates multiple functions. p, l l 0 6:0 configuration layout type. specifies the layout of bytes 10h through 3fh in configuration space. only layout 0 is supported. all other encodings are reserved . p, l l 0 h register 17-10. (pcibistr; pci:0fh, loc:30fh) pci built-in self test (bist) bit description read write value after reset 7 bist support. returns 1 if the device supports bist. returns 0 if the device is not bist-compatible. p, l l 0 6 bist start. the pci bus writes a 1 to invoke bist. generates an interrupt to the local bus. local bus resets the bit when bist is complete. software fails the device if bist is not complete after two seconds. refer to the runtime registers for interrupt control/status. p, l p, l 0 5:4 reserved. p, l n o 0 0 3:0 bist code. value of 0 indicates the device passed its test. nonzero values indicate the device failed. device specific failure codes can be encoded in the non-zero value. p, l l 0 h section 17 register summary pci configuration registers iop 480 data book r2.0 17-12 ? 2000 plx technology, inc. all rights reserved. note: pcibar1 can be enabled or disabled by setting or clearing las1ba[0]. register 17-11. (pcibar0; pci:10h, loc:310h) pci base address register for memory accesses to configuration registers and local address space 0 bit description read write value after reset 31:10 memory base address. memory base address for access to messaging queue, local, memory controller, runtime and dma registers, and to local address space 0. the first 1 kb of this base address register accesses the memory-mapped configuration registers. addresses above 1 kb access local address space 0. p, l p, l 0 h 9:4 memory base address. memory base address for access to messaging queue, local, memory controller, runtime and dma registers (default is 1kb). note: hardcoded to 0. p, l n o 0 h 3 prefetchable. value of 1 indicates there are no side effects on reads. this bit has no effect on the iop 480 operation. note: hardcoded to 0. p, l n o 0 2:1 location of register. location values: 00 = locate anywhere in 32-bit memory address space 11 = reserved note: hardcoded to 0. p, l n o 0 0 0 memory space indicator. value of 0 indicates the register maps into memory space. value of 1 indicates the register maps into i/o space. note: hardcoded to 0. p, l n o 0 register 17-12. (pcibar1; pci:14h, loc:314h) pci base address register for memory accesses to local address space 1 bit description read write value after reset 31:4 memory base address. memory base address for access to local address space 1. p, l p, l 0h 3 prefetchable (if memory space) . value of 1 indicates there are no side effects on reads. reflects value of las1rr[3] and provides only status to the system. this bit has no effect on the iop 480 operation. prefetching features of this address space are controlled by the associated bus region descriptor register. (specified in las1rr register.) if i/o space, bit 3 is included in the base address. p, l mem: no i/o: p, l 0 2:1 location of register (if memory space). location values: 00 = locate anywhere in 32-bit memory address space 01 = locate below 1-mb memory address space 10 = locate anywhere in 64-bit memory address space 11 = reserved (specified in las1rr register.) if i/o space, bit 1 is always 0 and bit 2 is included in the base address. p, l mem: no i/o: bit 1, no bit 2, yes p, l 00 0 memory space indicator. value of 0 indicates the register maps into memory space. value of 1 indicates the register maps into i/o space. (specified in las1rr register.) p, l n o 0 section 17 pci configuration registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-13 section 17 ? registers note: pcibar2 can be enabled or disabled by setting or clearing las2ba[0]. register 17-13. (pcibar2; pci:18h, loc:318h) pci base address register for memory accesses to local address space 2 bit description read write value after reset 31:4 memory base address. memory base address for access to local address space 2. p, l p, l 0h 3 prefetchable (if memory space). value of 1 indicates there are no side effects on reads. reflects the value of las2rr[3] and provides only status to the system. this bit has no effect on the iop 480 operation. prefetching features of this address space are controlled by the associated bus region descriptor register. (specified in las2rr register.) if i/o space, bit 3 is included in the base address. p, l mem: no i/o: p, l 0 2:1 location of register. location values: 00 = locate anywhere in 32-bit memory address space 01 = locate below 1-mb memory address space 10 = locate anywhere in 64-bit memory address space 11 = reserved (specified in las2rr register.) if i/o space, bit 1 is always 0 and bit 2 is included in the base address. p, l mem: no i/o: bit 1, no bit 2, yes p, l 00 0 memory space indicator. value of 0 indicates the register maps into memory space. value of 1 indicates the register maps into i/o space. (specified in las2rr register.) p, l n o 0 register 17-14. (pcibar3; pci:1ch, loc:31ch) pci base address register 3 bit description read write value after reset 31:0 reserved. p, l n o 0 h register 17-15. (pcibar4; pci:20h, loc:320h) pci base address register 4 bit description read write value after reset 31:0 reserved. p, l n o 0 h register 17-16. (pcibar5; pci:24h, loc:324h) pci base address register 5 bit description read write value after reset 31:0 reserved. p, l n o 0 h section 17 register summary pci configuration registers iop 480 data book r2.0 17-14 ? 2000 plx technology, inc. all rights reserved. register 17-17. (pcicis; pci:28h, loc:328h) pci cardbus cis pointer bit description read write value after reset 31:0 cardbus. cardbus information structure pointer (cis) for pcmcia. not supported. p, l n o 0 h register 17-18. (pcisvid; pci:2ch, loc:32ch) pci subsystem vendor id bit description read write value after reset 15:0 subsystem vendor id (unique add-in board vendor id). p, l l, e 10b5h register 17-19. (pcisid; pci:2eh, loc:32eh) pci subsystem id bit description read write value after reset 15:0 subsystem id (unique add-in board device id). p, l l, e 0480h register 17-20. (pcierbar; pci:30h, loc:330h) pci expansion rom base bit description read write value after reset 31:11 expansion rom base address (upper 21 bits). p, l p, l 0 h 10:1 reserved. p, l n o 0 h 0 address decode enable. value of 0 indicates the device does not accept accesses to the expansion rom space. value of 1 indicates the device accepts accesses to the expansion rom address. set this bit to 0 if no expansion rom is present. p, l p, l 0 register 17-21. (cap_ptr; pci:34h, loc:334h) capability list pointer bit description read write value after reset 31:8 reserved. p, l n o 0 h 7:0 capability list pointer. provides an offset into the pci configuration space for the location of the first item in the capabilities list, if the capabilities list status bit is set (pcisr[4]=1). bits [1:0] should be written as 00. p, l l, e 40h register 17-22. (pciilr; pci:3ch, loc:33ch) pci interrupt line bit description read write value after reset 7:0 interrupt line routing value. value indicates which system interrupt (controller(s) input is connected to the device interrupt. p, l p, l 0 h section 17 pci configuration registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-15 section 17 ? registers register 17-23. (pciipr; pci:3dh, loc:33dh) pci interrupt pin bit description read write value after reset 7:0 interrupt pin register. indicates which interrupt pin the device uses. the following values are decoded: 0 = no interrupt pin 1 = inta# 2 = intb# 3 = intc# 4 = intd# p, l l, e 01h register 17-24. (pcimgr; pci:3eh, loc:33eh) pci min_gnt bit description read write value after reset 7:0 min_gnt. specifies how long a burst period the device needs, assuming a clock rate of 33 mhz. value is multiple of 1/4 s increments. p, l l , e 0 h register 17-25. (pcimlr; pci:3fh, loc:33fh) pci max_lat bit description read write value after reset 7:0 max_lat. specifies how often the device must gain access to the pci bus. value is multiple of 1/4 s increments. p, l l, e 0h register 17-26. (pmcapid; pci:40h, loc:340h) power management capability id bit description read write value after reset 7:0 pm id. specifies the power management capability id. p, l l, e 01h register 17-27. (pmnext; pci:41h, loc:341h) power management next capability pointer bit description read write value after reset 7:0 next_cap pointer. points to the first location of the next item in the capabilities linked list. if power management is the last item in the list, then this register should be set to 0. p, l l, e 54h section 17 register summary pci configuration registers iop 480 data book r2.0 17-16 ? 2000 plx technology, inc. all rights reserved. register 17-28. ( pmc; pci:42h, loc:342h) power management capabilities bit description read write value after reset 15 reserved. p, l n o 0 14:11 pme_support. indicates the power states in which the iop 480 may assert pme#. value description xxx1 pme# can be asserted from d 0 xx1x pme# can be asserted from d 1 x1xx pme# can be asserted from d 2 1xxx pme# can be asserted from d 3hot p, l l , e 0 h 10 d 2 _support. value of 1 indicates the iop 480 supports the d 2 power state. p, l l, e 0 9 d 1 _support. value of 1 indicates the iop 480 supports the d 1 power state. p, l l, e 0 8:6 reserved. p, l no 000 5 dsi. value of 1 indicates the iop 480 requires special initialization following a transition to the d 0 uninitialized state before the generic class device driver is able to use it. p, l l , e 0 4 auxiliary power source. because the iop 480 does not support pme# while in d 3cold , this bit is always set to 0. p, l n o 0 3 pme clock. value of 1 indicates that a function relies on the presence of the pci clock for pme# operation. the iop 480 does not require the pci clock for pme#; therefore, this bit should set to 0. p, l l , e 0 2:0 version. value of 1 indicates that this function complies with pci power management interface specification, r1.1 . p, l l , e 0 1 section 17 pci configuration registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-17 section 17 ? registers register 17-29. (pmcsr; pci:44h, loc:344h) power management control/status bit description read write value after reset 15 pme_status. value of 1 indicates the pme# pin is being driven if pme_en is set high. writing a 1 from the local bus causes this bit to be set, and writing a 1 from the pci bus clears it. depending on the current power state, this bit is set only if the appropriate pme_support bits are set (pmc[14:11]). p, l l/set, p/clr 0 14:13 data_scale. indicates the scaling factor to use when interpreting the data register value. value and meaning of this bit depends on the data value selected by the data_select bits. the data_scale register bits accessed during a read are selected by the value in the data_select bits. for power consumed and power dissipated data, the following scale factors are used (unit values are in watts; data is read from pmscale): value scale 00 unknown 01 0.1x 10 0.01x 11 0.001x p, l n o 0 0 12:9 data_select. selects which data to access through the pmdata register and data_scale bits. p, l p, l 0h 8 pme_en. value of 1 enables the pme# pin to be asserted. p, l p, l 0 7:2 reserved. p, l n o 0 h 1:0 power state. used to determine or change the current power state. value state 00 d 0 01 d 1 10 d 2 11 d 3hot the transition from state 11 to state 00 causes a soft reset to occur. this should only be initiated from the pci bus because the local bus interface is reset during a soft reset. in state d 3hot , pci memory and i/o accesses are disabled, as well as the pci interrupts, and only configuration is allowed. the same is true for state d 2 if the corresponding d 2 _support pin is set. p, l p, l 00 section 17 register summary pci configuration registers iop 480 data book r2.0 17-18 ? 2000 plx technology, inc. all rights reserved. register 17-30. (pmcsr_bse; pci:46h, loc:346h) pmcsr bridge support extensions bit description read write value after reset 7:0 reserved. p, l n o 0 h register 17-31. (pmdata; pci:47h, loc:347h) power management data bit description read write value after reset 7:0 power management data. provides operating data such as power consumed or heat dissipation. data returned is selected by the data_select bits and is scaled by the data_scale bits. data_select value description 0d 0 power consumed 1d 1 power consumed 2d 2 power consumed 3d 3 power consumed 4d 0 power dissipated 5d 1 power dissipated 6d 2 power dissipated 7d 3 power dissipated p, l n o 0 h register 17-32. (pmscale; pci:48h, loc:348h) power management data_scale values bit description read write value after reset 31:16 reserved. p, l n o 0 h 15:14 data_scale 7. provides the data scale value for power management data 7 (data_select = 7). p, l l , e 0 0 13:12 data_scale 6. provides the data scale value for power management data 6 (data_select = 6). p, l l , e 0 0 11:10 data_scale 5. provides the data scale value for power management data 5 (data_select = 5). p, l l , e 0 0 9:8 data_scale 4. provides the data scale value for power management data 4 (data_select = 4). p, l l , e 0 0 7:6 data_scale 3. provides the data scale value for power management data 3 (data_select = 3). p, l l , e 0 0 5:4 data_scale 2. provides the data scale value for power management data 2 (data_select = 2). p, l l , e 0 0 3:2 data_scale 1. provides the data scale value for power management data 1 (data_select = 1). p, l l , e 0 0 1:0 data_scale 0. provides the data scale value for power management data 0 (data_select = 0). p, l l , e 0 0 section 17 pci configuration registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-19 section 17 ? registers register 17-33. (pwrcon; pci:4ch, loc:34ch) power consumed values bit description read write value after reset 31:24 d 3 power consumed. provides the power consumed in the d 3 state. (value read from pmdata when data_select = 3). p, l l , e 0 h 23:16 d 2 power consumed. provides the power consumed in the d 2 state. (value read from pmdata when data_select = 2). p, l l , e 0 h 15:8 d 1 power consumed. provides the power consumed in the d 1 state. (value read from pmdata when data_select = 1). p, l l , e 0 h 7:0 d 0 power consumed. provides the power consumed in the d 0 state. (value read from pmdata when data_select = 0). p, l l , e 0 h register 17-34. (pwrdis; pci:50h, loc:350h) power dissipated values bit description read write value after reset 31:24 d 3 power dissipated. provides the power dissipated in the d 3 state. (value read from pmdata when data_select = 7.) p, l l, e 0h 23:16 d 2 power dissipated. provides the power dissipated in the d 2 state. (value read from pmdata when data_select = 6.) p, l l, e 0h 15:8 d 1 power dissipated. provides the power dissipated in the d 1 state. (value read from pmdata when data_select = 5.) p, l l, e 0h 7:0 d 0 power dissipated. provides the power dissipated in the d 0 state. (value read from pmdata when data_select = 4.) p, l l, e 0h register 17-35. (hscapid; pci:54h, loc:354h) hot swap capability id bit description read write value after reset 7:0 hot swap id. specifies the hot swap capability id. must be set to 06h to be valid. p, l l, e 0h register 17-36. (hsnext; pci:55h, loc:355h) hot swap next capability pointer bit description read write value after reset 7:0 next_cap pointer. points to the first location of the next item in the capabilities linked list. if hot swap is the last item in the list, then this register should be set to 0. p, l l, e 58h section 17 register summary pci configuration registers iop 480 data book r2.0 17-20 ? 2000 plx technology, inc. all rights reserved. register 17-37. (hscsr; pci:56h, loc:356h) hot swap control/status bit description read write value after reset 15:8 reserved. p, l n o 0 h 7 enum# insertion status. value of 1 indicates that a board was inserted. writing a 1 clears this status bit. p, l p, l/clr 0 6 enum# removed status. value of 1 indicates that a board was removed. writing a 1 clears this status bit. p, l p, l/clr 0 5:4 reserved. p, l n o 0 0 3 led state. value of 1 indicates the external led is turned on. value of 0 indicates the external led is turned off. reading this bit returns the ledon/ledin pin status. p, l p, l 0 2 reserved. p, l n o 0 1 enum# interrupt mask. value of 0 indicates the enum# interrupt output is enabled. value of 1 indicates the enum# interrupt output is disabled. p, l p, l 0 0 reserved. p, l n o 0 register 17-38. (vpd_cap; pci:58h, loc:358h) vpd capabilities bit description read write value after reset 31 f flag. a flag used to indicate when a data operation to the serial eeprom is complete. for write cycles, the four bytes of data are first written into the vpd data bits. then, the vpd address is written at the same time the f flag is set to 1. when the data transfer to the serial eeprom is complete, the f flag is cleared. for read cycles, the vpd address is written at the same time the f flag is cleared to 0. when the four bytes of data are read from the serial eeprom, the f flag is set. p, l p, l/set/clr 0 30:16 vpd address. vpd byte address accessed. all accesses are 32-bit wide; bits [17:16] must be set to 0. with the maximum serial eeprom size being 4k bits, bits [30:28] are ignored. p, l p, l 0 h 15:8 next_cap pointer. points to the first location of the next item in the capabilities linked list. if vpd is the last item in the list, then this register should be set to zero. p, l l 0 h 7:0 vpd id. specifies the vpd capability id. p, l l 3h register 17-39. (vpd_data; pci:5ch, loc:35ch) vpd data bit description read write value after reset 31:16 vpd data. vpd data is written or read through this register. these bits go into address n, as specified in the vpd address bits (vpd_cap[30:16]). p, l p, l 0 h 15:0 vpd data. vpd data is written or read through this register. these bits go into address n + 1. p, l p, l 0h section 17 messaging queue registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-21 section 17 ? registers 17.4 messaging queue registers note: burst cycles are not supported by the messaging queue registers. register 17-40. (mqcr; pci:00h, loc:00h) messaging queue configuration bit description read write value after reset 31:4 reserved. p, l n o 0 h 3:1 queue size. contains the size of one of the circular queues. each of the four queues are the same size. queue size encoding : maximum entries queue total queue 3:1 per queue size memory 000 128 entries 512 kb 2 kb 001 512 entries 2 kb 8 kb 010 2 kilobit entries 8 kb 32 kb 011 4 kilobit entries 16 kb 64 kb 100 8 kilobit entries 32 kb 128 kb 101 16 kilobit entries 64 kb 256 kb 110 32 kilobit entries 128 kb 512 kb 111 64 kilobit entries 256 kb 1 mb p, l p, l 000 0 queue enable. value of 0 indicates writes are accepted, but ignored, and reads return ffffffffh. value of 1 allows accesses to the inbound and outbound queue ports. complete pointer initialization and frame allocation before enabling this bit. p, l p, l 0 register 17-41. (qbar; pci:04h, loc:04h) queue base address bit description read write value after reset 31:20 queue base address. local memory base address of the inbound and outbound circular queues. queue base address must be aligned on a 1 mb boundary. p, l p, l 0 h 19:0 reserved. p, l n o 0 h register 17-42. (ifhpr; pci:08h, loc:08h) inbound free head pointer bit description read write value after reset 31:20 queue base address. local memory base address of the inbound and outbound circular queues. queue base address must be aligned on a 1 mb boundary. p, l n o 0 h 19:2 inbound free head pointer. local memory offset for inbound free queue. must be initialized to (0*queuesize) and maintained by software. p, l p, l 0 h 1:0 reserved. p, l n o 0 0 section 17 register summary messaging queue registers iop 480 data book r2.0 17-22 ? 2000 plx technology, inc. all rights reserved. register 17-43. (iftpr; pci:0ch, loc:0ch) inbound free tail pointer bit description read write value after reset 31:20 queue base address. local memory base address of the inbound and outbound circular queues. queue base address must be aligned on a 1 mb boundary. p, l n o 0 h 19:2 inbound free tail pointer. local memory offset for inbound free queue. must be initialized to (0*queuesize) by software. maintained by the iop 480 and incremented with respect to the queue size. p, l p, l 0 h 1:0 reserved. p, l n o 0 0 register 17-44. (iphpr; pci:10h, loc:10h) inbound post head pointer bit description read write value after reset 31:20 queue base address. local memory base address of the inbound and outbound circular queues. queue base address must be aligned on a 1 mb boundary. p, l n o 0 h 19:2 inbound post head pointer. local memory offset for the inbound post queue. must be initialized to (1*queuesize) by software. maintained by the iop 480 and incremented with respect to the queue size. p, l p, l 0h 1:0 reserved. p, l n o 0 0 register 17-45. (iptpr; pci:14h, loc:14h) inbound post tail pointer bit description read write value after reset 31:20 queue base address. local memory base address of the inbound and outbound circular queues. queue base address must be aligned on a 1 mb boundary. p, l n o 0 h 19:2 inbound post tail pointer. local memory offset for the inbound post queue. must be initialized to (1*queuesize) and maintained by software. p, l p, l 0h 1:0 reserved. p, l n o 0 0 register 17-46. (ofhpr; pci:18h, loc:18h) outbound free head pointer bit description read write value after reset 31:20 queue base address. local memory base address of the inbound and outbound circular queues. queue base address must be aligned on a 1 mb boundary. p, l n o 0 h 19:2 outbound free head pointer. local memory offset for outbound free queue. must be initialized to (3*queuesize) by software. maintained by the iop 480 and incremented with respect to the queue size. p, l p, l 0h 1:0 reserved. p, l n o 0 0 section 17 messaging queue registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-23 section 17 ? registers register 17-47. (oftpr; pci:1ch, loc:1ch) outbound free tail pointer bit description read write value after reset 31:20 queue base address. local memory base address of the inbound and outbound circular queues. queue base address must be aligned on a 1 mb boundary. p, l n o 0 h 19:2 outbound free tail pointer. local memory offset for outbound free queue. must be initialized to (3*queuesize) and maintained by software. p, l p, l 0 h 1:0 reserved. p, l n o 0 0 register 17-48. (ophpr; pci:20h, loc:20h) outbound post head pointer bit description read write value after reset 31:20 queue base address. local memory base address of the inbound and outbound circular queues. queue base address must be aligned on a 1 mb boundary. p, l n o 0 h 19:2 outbound post head pointer. local memory offset for outbound post queue. must be initialized to (2*queuesize) and maintained by software. p, l p, l 0h 1:0 reserved. p, l n o 0 0 register 17-49. (optpr; pci:24h, loc:24h) outbound post tail pointer bit description read write value after reset 31:20 queue base address. local memory base address of the inbound and outbound circular queues. queue base address must be aligned on a 1 mb boundary. p, l n o 0 h 19:2 outbound post tail pointer. local memory offset for outbound post queue. must be initialized to (2*queuesize) by software. maintained by the iop 480 and incremented with respect to the queue size. p, l p, l 0h 1:0 reserved. p, l n o 0 0 section 17 register summary messaging queue registers iop 480 data book r2.0 17-24 ? 2000 plx technology, inc. all rights reserved. register 17-50. (qsr; pci:28h, loc:28h) queue status/control bit description read write value after reset 31:9 reserved. p, l n o 0 h 8 outbound option interrupt mask. value of 0 enables the outbound option to set the outbound post queue interrupt status bit. value of 1 masks the outbound option interrupt. p, l p, l 1 7 outbound free queue overflow interrupt. value of 1 indicates the outbound free queue overflowed. a local interrupt out (into) is generated. writing a message frame address 1 clears the interrupt. p, l p, l/clr 0 6 outbound free queue overflow interrupt mask . value of 0 indicates the outbound free queue overflow interrupt is enabled. value of 1 masks the outbound free queue overflow interrupt. p, l p, l 1 5 inbound post queue interrupt. value of 1 indicates the inbound post queue is not empty. this bit is not effected by the interrupt mask bit. p, l n o 0 4 inbound post queue interrupt mask. value of 0 indicates the inbound post queue interrupt is enabled. value of 1 masks the inbound post queue interrupt. p, l p, l 1 3 inbound free queue prefetch enable. value of 1 indicates prefetching occurs from the inbound free queue if not empty. p, l p, l 0 2 outbound post queue prefetch enable. value of 1 indicates prefetching occurs from the outbound post queue if not empty. p, l p, l 0 1:0 reserved. p, l n o 0 0 register 17-51. (opqis; pci:30h, loc:30h) outbound post queue interrupt status bit description read write value after reset 31:4 reserved. p, l n o 0 h 3 outbound post queue interrupt status. value of 1 indicates the outbound post queue is not empty. also, if the outbound option interrupt is enabled, this interrupt is set if the hostoutidx and iopoutidx registers are not equal. this bit is not effected by the interrupt mask bit, and causes a pci interrupt to be generated. p, l n o 0 2:0 reserved. p, l n o 0 0 0 register 17-52. (opqim; pci:34h, loc:34h) outbound post queue interrupt mask bit description read write value after reset 31:4 reserved. p, l n o 0 h 3 outbound post queue interrupt mask. value of 0 indicates the outbound post queue interrupt is enabled. value of 1 masks the outbound post queue interrupt. p, l p, l 1 2:0 reserved. p, l no 000 section 17 messaging queue registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-25 section 17 ? registers register 17-53. (iqp; pci:40h) inbound queue port bit description read write value after reset 31:0 inbound queue port. value written by the pci master is stored into the inbound post queue, which is located in a local memory at the address pointed to by the queue base address + queue size + inbound post head pointer. from the time of the pci write until the local memory write and update of the inbound post queue head pointer, further accesses to this register result in a retry. a local interrupt is generated when the inbound post queue is not empty. when the port is read by the pci master, the value is read from the inbound free queue, which is located in local memory at the address pointed to by the queue base address + inbound free tail pointer. if the queue is empty, a value of fffffffh is returned. pp 0h register 17-54. (oqp; pci:44h) outbound queue port bit description read write value after reset 31:0 outbound queue port. value written by the pci master is stored into the outbound free queue, which is located in a local memory at the address pointed to by the queue base address + 3*queue size + outbound free head pointer. from the time of the pci write until the local memory write and update of the outbound free queue head pointer, further accesses to this register result in a retry. if the queue fills, a local nmi interrupt is generated. when the port is read by the pci master, the value is read from the outbound post queue, which is located in local memory at the address pointed to by the queue base address + 2*queue size + outbound post tail pointer. if the queue is empty, a value of fffffffh is returned. a pci interrupt is generated if the outbound post queue is not empty. pp 0h register 17-55. (hostoutidx; pci:50h, loc:50h) host outbound index bit description read write value after reset 31:2 host outbound index register. written by the pci host. used for implementing the i 2 o outbound option. indicates to the iop 480 how many of the posted i 2 o messages were processed by the host. p, l p, l 0 h 1:0 reserved . p, l n o 0 0 register 17-56. (iopoutidx; pci:54h, loc:54h) iop outbound index bit description read write value after reset 31:2 iop outbound index register. maintained by the local cpu. used for implementing the i 2 o outbound option. the local cpu (iop) uses this register to keep track of where the next mfa is written into the hostpostlist fifo in host memory. p, l p, l 0 h 1:0 reserved . p, l n o 0 0 section 17 register summary local configuration registers iop 480 data book r2.0 17-26 ? 2000 plx technology, inc. all rights reserved. 17.5 local configuration registers register 17-57. (devinit; pci:80h, loc:80h) device initialization bit description read write value after reset 31 local init status. value of 1 indicates local init done. responses to direct slave accesses are retrys until this bit is set.must be set by either the serial eeprom (at the end of loading) or by the internal iop 480 cpu (in adapter mode). p, l p, l, e 0 30 software reset. value of 1 activates software reset. the iop 480 host/adapter mode pin determines the behavior of the software reset. p, l p, l, e 0 29 reload configuration registers. changing the value from 0 to 1 causes iop 480 to reload the configuration registers from the serial eeprom. p, l p, l, e 0 28 serial eeprom present. value of 1 indicates a non-blank serial eeprom is present and valid. works in conjunction with devinit[5]. p, l n o 0 27 read serial eeprom data. for reads, this input bit is the output of the serial eeprom. clocked out of the serial eeprom by the serial eeprom clock. p, l n o ? 26 write bit to serial eeprom. for writes, this output bit is the input to the serial eeprom. clocked into the serial eeprom by the serial eeprom clock. p, l p, l, e 0 25 serial eeprom chip select. for local or pci bus reads or writes to the serial eeprom, setting this bit to 1 provides the serial eeprom chip select. p, l p, l, e 0 24 serial eeprom clock. toggling this bit generates a serial eeprom clock. (refer to manufacturer ? s data sheet for particular serial eeprom being used.) p, l p, l, e 0 23 serial eeprom data output enable. value of 1 enables software access (read/write) to the serial eeprom. value of 0 disables software access (read/write) to the serial eeprom. p, l p, l 0 22:15 reserved. p, l n o 0 h 14:8 serial eeprom protected area. specifies the top of the protected area in the serial eeprom. locations below this value cannot be written to. these bits are in units of 32-bit lwords. p, l p, l 40h 7:6 reserved . p, l n o 0 0 5 serial eeprom physically present. value of 1 indicates the serial eeprom is blank or programmed. when the serial eeprom present bit is set to 1 (devinit[28]=1), devinit[5] indicates a non-blank serial eeprom is present. value of 0 indicates that there is no serial eeprom physically present. p, l n o 0 4 risctrace enable. value of 1 enables diagnostic risctrace mode. bit 23, the serial eeprom data output enable bit, must also be asserted. the uart (spu) and serial eeprom interface are disabled when risctrace is enabled. the third pci arbiter channel (req2# and gnt2#) are disabled while risctrace is running. in risctrace mode, the iop 480 makes use of the ts[6:1] output pins. p, l p, l, e 0 3 id select. value of 1 places the subsystem and subsystem vendor ids into the pcivid and pcidid registers. p, l p, l, e 0 2:1 mask revision. indicates the silicon mask revision. p, l no current mask revision 0 iop 480 cpu reset. value of 0 causes the iop 480 cpu reset to de-assert, allowing it to begin operation. value of 1 holds the iop 480 cpu in a reset state. if a programmed serial eeprom is not detected at pci reset, this bit is set to 0, allowing the cpu to start. if a programmed serial eeprom is detected, then this bit is programmed by the serial eeprom. p, l p, l, e 1 section 17 local configuration registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-27 section 17 ? registers register 17-58. (locctl; pci:84h, loc:84h) local bus control bit description read write value after reset 31:26 reserved. p, l n o 0 h 25 pci abort control. value of 1 indicates a pci master/target abort asserts bterm# as it normally does, and also continues asserting ready# until blast# is asserted. value of 0 sets up bterm# to indicate the last data transfer for the access. this means that an external local master must know that a cycle can end with either blast# (by master) or bterm# (by slave). p, l p, l 1 24 iop 480 cpu lock. value of 1 indicates the local bus arbiter to grant only the local bus to the internal iop 480 cpu. value of 0 indicates the local bus arbiter operates normally. p, l p, l , e 0 23:22 direct slave write delay. used to delay writes to the local bus, providing time for data to accumulate in the direct slave write fifo before starting a local burst cycle. 00 = no delay; start the cycle immediately 01 = delay 4 local clocks 10 = delay 8 local clocks 11 = delay 16 local clocks p, l p, l , e 0 0 21 direct master fifo almost full. value of 1 indicates the direct master write fifo is almost full. reflects the inverse of the dmpaf# pin. p, l n o 0 20 reserved . p, l n o 0 19 blast# timing. value of 0 asserts blast# during the entire last cycle when the iop 480 is the local bus master. value of 1 causes blast# to not assert until the internal wait state counters have finished counting. p, l p, l , e 0 18 reserved. p, l n o 0 17 user4 data. reading this bit provides the state of the eot1#/eot2#/ user4 pin. when the eot1#/eot2#/user4 pin is not used for dma, it can be used as a general purpose input pin. p, l n o 1 16 user3 data. reading this bit provides the state of the eot0#/user3 pin. when the eot0#/user3 pin is not used for dma, it can be used as a general purpose input pin. p, l n o 1 15:12 reserved. p, l n o 0 h 11 dreq/dack/eot select. selects the function of the dreq1#/dreq2#, dack1#/dack2# and eot1#/eot2#/user4 pins for dma channels 1 and 2. value of 0 indicates use of the dreq1#, dack1#, and eot1# pins. value of 1 indicates use of the dreq2#, dack2#, and eot2# pins. p, l p, l , e 0 10 user2 data. if programmed as an output, writing a 1 causes the corresponding pin to go high. if programmed as an input, reading this bit provides the state of the cint/user2 pin. p, l p, l , e 0 9 user2 direction. value of 0 indicates the bit is programmed as an input. value of 1 indicates the bit is programmed as an output. it is always an input if the cint function is selected. p, l p, l , e 0 8 cint/user2 pin select. selects function of cint/user2 pin. value of 0 identifies this pin as cint. value of 1 identifies this pin as user2. p, l p, l , e 1 7 lcs3#/ma17 pin select. selects function of lcs3#/ma17 pin. value of 0 identifies this pin as lcs3#. value of 1 identifies this pin as ma17. p, l p, l , e 0 6 user1 data. if programmed as an output, writing a 1 causes the corresponding pin to go high. if programmed as an input, reading this bit provides the state of the lcs2#/user1 pin. p, l p, l , e 0 section 17 register summary local configuration registers iop 480 data book r2.0 17-28 ? 2000 plx technology, inc. all rights reserved. 5 user1 direction. value of 0 indicates the bit is programmed as an input. value of 1 indicates the bit is programmed as an output. it is always an output if the lcs2# function is selected. p, l p, l , e 0 4 lcs2#/user1 pin select. selects function of the lcs2#/user1 pin. value of 0 identifies this pin as lcs2#. value of 1 identifies this pin as user1. p, l p, l , e 1 3 user0 data. if programmed as an output, writing a 1 causes the corresponding pin to go high. if programmed as an input, reading this bit provides the state of the lcs1#/user0 pin. p, l p, l , e 0 2 user0 direction. value of 0 indicates the bit is programmed as an input. value of 1 indicates the bit is programmed as an output. it is always an input if the lcs1# function is selected. p, l p, l , e 0 1 lcs1#/user0 pin select. selects function of lcs1#/user0 pin. value of 0 identifies this pin as lcs1#. value of 1 identifies this pin as user0. p, l p, l , e 1 0 lcs0#/dmpaf# pin select. selects function of the lcs0#/dmpaf# pin. value of 0 identifies this pin as lcs0#. value of 1 identifies this pin as dmpaf#. p, l p, l , e 0 register 17-59. (loctmo; pci:88h, loc:88h) local bus timeout bit description read write value after reset 31:16 reserved. p, l n o 0 h 15 local bus timeout enable. value of 1 indicates the local bus timeout timer is enabled. if an external local bus master controls the local bus, then the timeout timer runs only if the timeout timer enable bit in the corresponding memory controller register is also set. p, l p, l, e 0 14:0 local bus timeout value. value loaded into a timer at the beginning of the local bus transfer. timer is decremented once per local bus clock while ready# is de-asserted. if the timer times out, an internal ready and interrupt are generated, signaling a bus timeout. maximum timeout is about 480 s, based on a 66 mhz local bus clock. p, l p, l, e 0h register 17-60. (loctmr; pci:8ch, loc:8ch) local bus timers bit description read write value after reset 31:25 reserved. p, l n o 0 h 24 local bus pause timer enable. value of 1 indicates the pause timer is enabled. p, l p, l, e 0 23:16 local bus pause timer. number of local bus clock cycles to occur before requesting the local bus after releasing the local bus for internal dma channels. p, l p, l, e 0h 15:9 reserved. p, l n o 0 h 8 local bus latency timer enable. value of 1 indicates the latency timer is enabled. p, l p, l, e 0 7:0 local bus latency timer. number of local bus clock cycles the iop 480 holds the local bus before releasing it to another requester. p, l p, l, e 0h register 17-58. (locctl; pci:84h, loc:84h) local bus control (continued) bit description read write value after reset section 17 local configuration registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-29 section 17 ? registers register 17-61. (larbr; pci:90h, loc:90h) local/dma arbitration bit description read write value after reset 31:22 reserved. p, l n o 0 h 21 boff# timer resolution. value of 0 selects the lsb of the backoff timer of 8 clocks. value of 1 selects the lsb of the backoff timer of 64 clocks. p, l p, l, e 0 20:17 direct slave boff# delay clocks. number of local bus clocks in which a direct slave bus request is pending and a local direct master access is in progress and not being granted the bus before asserting boff#. once asserted, boff# remains asserted until the lholdreq[1:0] pins are de-asserted. (lsb = 8 or 64 clocks.) p, l p, l, e 0h 16 local bus boff# enable. value of 1 enables the iop 480 to assert the boff# pin. p, l p, l, e 0 15:11 reserved. p, l n o 0 h 10 latency timer gate. value of 1 indicates the gate of the local bus latency timer with lholdreq[1:0]; therefore, the local bus latency timer is significant only when lholdreq[1:0] input is asserted. p, l p, l, e 0 9 direct slave lock enable. value of 0 disables direct slave locked sequences. value of 1 enables direct slave locked sequences. p, l p, l, e 0 8 local bus direct slave release bus mode. value of 1 indicates the iop 480 de-asserts hold and releases the local bus when the direct slave write fifo becomes empty during a direct slave write or when a direct slave read fifo becomes full during a direct slave read. p, l p, l, e 0 7 external preempt enable. value of 0 indicates the refresh cycle and local latency timer cannot preempt external local masters. value of 1 indicates that lholdack1/breq output is asserted to request an external local master to release the local bus when there is a refresh cycle or the local latency timer is expired (internal local arbiter must be enabled in this case). p, l p, l 1 6 local bus park enable. value of 0 indicates the iop 480 does not drive the lad and lbe buses when the local bus is idle. in this case, external pull-up resistors should be used to drive the lad and lbe buses to a known value. value of 1 indicates the lad and lbe buses are driven by the iop 480 when the internal local bus arbiter is enabled, and the local bus is idle. p, l p, l 1 5:4 dma channel priority. value of 00 indicates a rotational priority scheme. value of 01 indicates channel 0 has priority. value of 10 indicates channel 1 has priority. value of 11 is reserved (local bus arbiter.) p, l p, l, e 00 3:1 local arbitration priority. determines the local bus arbiter operation. if an individual requester is given priority, the other requesters still participate in a round-robin arbitration. the prioritized individual requester alternates with the round-robin arbitration winner. 000 round-robin priority 001 iop 480 cpu has priority 010 dma channels 0 and 1 have priority 011 direct slave has priority 100 lholdreq0/lholdack has priority 101 lholdreq1 has priority 110 dma channel 2 has priority 111 reserved p, l p, l, e 000 0 local arbiter enable. value of 0 indicates the local bus arbiter is disabled, and lholdreq0/lholdack and lholdack0/ldreq are used by the iop 480 to acquire local bus use. value of 1 indicates this bit enables the local bus arbiter. p, l p, l, e 1 section 17 register summary local configuration registers iop 480 data book r2.0 17-30 ? 2000 plx technology, inc. all rights reserved. register 17-62. (bigend; pci:94h, loc:94h) big/little endian bit description read write value after reset 31:4 reserved . p, l n o 0 h 3 direct master big endian mode (for internal iop 480 cpu). value of 0 specifies little endian ordering. value of 1 specifies use of big endian data ordering for direct master accesses. p, l p, l , e 0 2 configuration register big endian mode (for internal iop 480 cpu). value of 0 specifies little endian ordering. value of 1 specifies use of big endian data ordering for local accesses to the configuration registers. p, l p, l , e 0 1 direct master big endian mode (for external local bus master). value of 0 specifies little endian ordering. value of 1 specifies use of big endian data ordering for direct master accesses. p, l p, l , e 0 0 configuration register big endian mode (for external local bus master). value of 0 specifies little endian ordering. value of 1 specifies use of big endian data ordering for local accesses to the configuration registers. p, l p, l , e 0 register 17-63. (pcictl; pci:98h, loc:98h) pci bus control bit description read write value after reset 31:28 direct slave retry delay clocks. contains the value (multiplied by 8) of the number of pci bus clocks after receiving a pci local read or write access and not successfully completing a transfer. pertains only to direct slave writes when bit 27 is set to 1 (pcictl[27]=1). p, l p, l, e 4 (32 clocks) 27 insert direct slave wait states on direct slave write fifo full. value of 0 indicates the iop 480 should disconnect when the direct slave write fifo is full. value of 1 indicates the iop 480 should de-assert trdy# when the write fifo is full. p, l p, l, e 0 26 de-assert pci request at frame#. value of 0 causes the iop 480 to leave req0# asserted for the entire bus master cycle. value of 1 causes the iop 480 to de-assert req0# when it asserts frame# during a master cycle. valid only when the iop 480 pci arbiter is disabled. p, l p, l, e 1 25 pci delayed read mode. value of 0 indicates the iop 480 does not return trdy# to the pci host until read data is available. value of 1 indicates the iop 480 operates in delayed transaction mode for direct slave reads. the iop 480 issues a retry and prefetches the read data. considered a pending read until the pci host returns for the read data. p, l p, l, e 1 24 retry pci writes during pending reads. value of 0 allows writes to occur while a read is pending. value of 1 forces a retry on writes if read is pending. p, l p, l, e 0 23 flush pending reads on pci writes. value of 1 flushes pending read cycles when a write cycle is detected. p, l p, l, e 0 22 pci read ahead mode. value of 0 submits request to flush the read fifo when a pci read cycle completes. value of 1 submits a request to not flush the read fifo when the pci read cycle completes. p, l p, l, e 0 21 treat 256 pci retries as abort. value of 0 enables the iop 480 to attempt master retries indefinitely. value of 1 enables the iop 480 to treat 256 master consecutive retries from a direct slave as a target abort. p, l p, l 0 section 17 local configuration registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-31 section 17 ? registers 20 flush pending pci reads on disconnect (by the iop 480). value of 1 forces the iop 480 to flush any pending reads after the iop 480 issues a disconnect (versus a retry). value of 0 makes no distinction between a disconnect or a retry; therefore, it does not flush pending reads, waiting for the reading master to return for the read data. p, l p, l 0 19 pci arbiter parking on iop 480. value of 1 indicates the pci arbiter parks the grant on the iop 480. value of 0 indicates the pci arbiter parks the grant on the current pci master (when using the internal pci arbiter). p, l p, l 0 18 early grant release. value of 0 indicates the iop 480 keeps gnt# asserted until another master requests use of the pci bus. value of 1 indicates the iop 480 always de-asserts the current gnt# when frame# is asserted (when using the internal pci arbiter). p, l p, l, e 0 17 iop 480 high priority. value of 0 indicates the iop 480 participates in round-robin arbitration with the other pci masters. value of 1 indicates a two-level, round-robin arbitration scheme is enabled. the other pci bus masters participate in their own round-robin arbitration. the winner of this arbitration then arbitrates for the pci bus with the iop 480 (when using the internal pci arbiter). p, l p, l, e 0 16 pci arbiter enable. value of 0 indicates the pci arbiter is disabled and req0# and gnt0# are used by the iop 480 to acquire pci bus use. value of 1 indicates the pci arbiter is enabled. p, l p, l, e 0 15:12 pci memory write command code for direct master. p, l p, l, e 0111 11:8 pci memory read command code for direct master. p, l p, l, e 0110 7:4 pci write command code for dma. p, l p, l, e 0111 3:0 pci read command code for dma. p, l p, l, e 1110 register 17-64. (las0rr; pci:a0h, loc:a0h) memory-mapped configuration register and local address space 0 range register for pci-to-local bus bit description read write value after reset 31:10 local space 0 range. specifies which pci address bits to use for decoding a pci access to the memory-mapped configuration registers and local address space 0. each bit corresponds to a pci address bit. bit 31 corresponds to address bit 31. write 1 to all bits included in the decoding. write 0 to all other bits (used in conjunction with pcibar0). the default is 1 kb, which corresponds to the configuration register space. p, l p, l, e ffffc0h 9:0 reserved. p, l n o 0 h register 17-65. (las0ba; pci:a4h, loc:a4h) local address space 0 base address (remap) for pci-to-local bus bit description read write value after reset 31:10 local space 0 remap. remap of pci address space to local address space 0 into a local address space. bits in this register remap (replace) the pci address bits used for decoding as the local address bits. p, l p, l, e 0h 9:0 reserved. p, l n o 0 h register 17-63. (pcictl; pci:98h, loc:98h) pci bus control (continued) bit description read write value after reset section 17 register summary local configuration registers iop 480 data book r2.0 17-32 ? 2000 plx technology, inc. all rights reserved. register 17-66. (las1rr; pci:a8h, loc:a8h) local address space 1 range register for pci-to-local bus bit description read write value after reset 31:4 local space 1 range. specifies which pci address bits to use for decoding a pci access to local address space 1. each bit corresponds to a pci address bit. bit 31 corresponds to address bit 31. write 1 to all bits included in the decoding. write 0 to all other bits (used in conjunction with pcibar1). default is 1 mb. p, l p, l, e fff0000h 3 prefetchable. if mapped into memory space, a value of 1 indicates reads are prefetchable (bit has no effect on the operation of iop 480, but is for system status). if mapped into i/o space, the bit is included with bits [31:2] to indicate the decoding range. p, l p, l, e 0 2:1 address location. if mapped into memory space, encoding is as follows: 2/1 meaning 0 0 locate anywhere in 32-bit pci address space 0 1 locate below 1 mb in pci address space 1 0 locate anywhere in 64-bit pci address space 1 1 reserved if mapped into i/o space, bit 1 must be set to 0. bit 2 is included with bits [31:3] to indicate decoding range. p, l p, l, e 00 0 memory space indicator. value of 0 indicates the local address space 1 maps into pci memory space. value of 1 indicates the local address space 1 maps into pci i/o space. p, l p, l, e 0 register 17-67. (las1ba; pci:ach, loc:ach) local address space 1 base address (remap) for pci-to-local bus bit description read write value after reset 31:4 local space 1 remap. remap of pci address space to local address space 1 into a local address space. bits in this register remap (replace) the pci address bits used for decoding as the local address bits. p, l p, l , e 0 h 3:2 local space 1 remap. if local address space 1 is mapped into memory space, bits are not used. if mapped into i/o space, bits are included with bits [31:4] for remapping. p, l p, l , e 0 0 1 reserved. p, l n o 0 0 space 1 enable. value of 0 disables decoding of this address space. value of 1 enables decoding of pci addresses for direct slave access to local address space 1. p, l p, l , e 0 section 17 local configuration registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-33 section 17 ? registers register 17-68. (las2rr; pci:b0h, loc:b0h) local address space 2 range register for pci-to-local bus bit description read write value after reset 31:4 local space 2 range. specifies which pci address bits to use for decoding a pci access to local address space 2. each bit corresponds to a pci address bit. bit 31 corresponds to address bit 31. write 1 to all bits included in the decoding. write 0 to all other bits (used in conjunction with pcibar2). default is 1 mb. p, l p, l, e fff0000h 3 prefetchable. if mapped into memory space, a value of 1 indicates reads are prefetchable (bit has no effect on the operation of iop 480, but is for system status). if mapped into i/o space, bit is included with bits [31:2] to indicate decoding range. p, l p, l , e 0 2:1 address location. if mapped into memory space, encoding is as follows: 2/1 meaning 0 0 locate anywhere in 32-bit pci address space 0 1 locate below 1 mb in pci address space 1 0 locate anywhere in 64-bit pci address space 1 1 reserved if mapped into i/o space, bit 1 must be set to 0. bit 2 is included with bits [31:3] to indicate decoding range. p, l p, l , e 0 0 0 memory space indicator. value of 0 indicates the local address space 2 maps into pci memory space. value of 1 indicates the local address space 2 maps into the pci i/o space. p, l p, l , e 0 register 17-69. (las2ba; pci:b4h, loc:b4h) local address space 2 base address (remap) for pci-to-local bus bit description read write value after reset 31:4 local space 2 remap. remap of pci address space to local address space 2 into a local address space. bits in this register remap (replace) the pci address bits used for decoding as the local address bits. p, l p, l, e 0h 3:2 local space 2 remap . if local address space 2 is mapped into memory space, bits are not used. if mapped into i/o space, bits are included with bits [31:4] for remapping. p, l p, l, e 00 1 reserved. p, l n o 0 0 space 2 enable. value of 0 disables decoding of this address space. value of 1 enables decoding of pci addresses for direct slave access to local address space 2. p, l p, l, e 0 section 17 register summary local configuration registers iop 480 data book r2.0 17-34 ? 2000 plx technology, inc. all rights reserved. register 17-70. (eromrr; pci:c0h, loc:c0h) expansion rom range bit description read write value after reset 31:11 erom range. specifies which pci address bits to use for decoding a pci-to-local bus expansion rom. each bit corresponds to a pci address bit. bit 31 corresponds to address bit 31. write 1 to all bits included in decode. write 0 to all other bits (used in conjunction with pcierbar). default is 64 kb. p, l p, l, e ffff00h 10:0 reserved. p, l n o 0 h register 17-71. (eromba; pci:c4h, loc:c4h) expansion rom local base address (remap) bit description read write value after reset 31:11 erom remap. remap of pci expansion rom space into a local address space. bits in this register remap (replace) the pci address bits for decoding as the local address bits. p, l p, l , e 0 h 10:0 reserved. p, l n o 0 h register 17-72. (dmrr; pci:c8h, loc:c8h) local range register for direct master-to-pci bit description read write value after reset 31:16 direct master range. specifies which local address bits to use for decoding a local-to-pci bus access. each bit corresponds to a pci address bit. bit 31 corresponds to address bit 31. write 1 to all bits included in decoding. write 0 to all other bits. changes the range, in increments of 64 kb. p, l p, l, e 0h 15:0 reserved. p, l n o 0 h register 17-73. (dmlbam; pci:cch, loc:cch) local bus base address register for direct master-to-pci memory bit description read write value after reset 31:16 local direct master base address. assigns a value to the bits to use for decoding local-to-pci memory access. p, l p, l, e 0h 15:0 reserved. p, l n o 0 h section 17 local configuration registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-35 section 17 ? registers register 17-74. (dmpbam; pci:d0h, loc:d0h) pci base address (remap) register for direct master-to-pci memory (lower 32 bits) bit description read write value after reset 31:16 direct master remap. remap of local-to-pci space into pci address space. bits in this register remap (replace) the local address bits used in decode as the pci address bits. p, l p, l, e 0h 15 i/o remap select. value of 0 uses bits [31:16] as pci address bits [31:16]. value of 1 forces pci address bits [31:16] to all zeros on direct master i/o cycles. p, l p, l, e 0 14:13 direct master write delay. delays the pci bus request after a direct master burst write cycle started. values: 00 = no delay; start the cycle immediately 01 = delay 4 pci clocks 10 = delay 8 pci clocks 11 = delay 16 pci clocks p, l p, l, e 00 12:8 programmable almost full flag. when the number of entries in the 32-lword direct master write fifo exceed this value, the output pin dmpaf# is asserted low. p, l p, l, e 0h 7 write and invalidate mode. value of 1 indicates the iop 480 waits for 8 or 16 lwords that must be written from the local bus before starting a pci access. value of 1 indicates that all local direct master-to-pci write accesses must be 8- or 16-lword bursts. p, l p, l, e 0 6 direct master pci read mode. value of 0 indicates the iop 480 should release the pci bus when the read fifo becomes full. value of 1 indicates the iop 480 should keep the pci bus and de-assert irdy# when read fifo becomes full. p, l p, l, e 0 5 direct master prefetch limit. value of 1 indicates that prefetching is terminated at 4 kb boundaries. p, l p, l, e 0 4:3 direct master read prefetch size control. values: 00 = iop 480 continues to prefetch the read data from the pci bus until the direct master access is finished. may result in an additional four unneeded words being prefetched from the pci bus. 01 = prefetch up to 4 words from the pci bus 10 = prefetch up to 8 words from the pci bus 11 = prefetch up to 16 words from the pci bus direct master burst reads should not exceed the programmed limit. p, l p, l, e 00 2 llock# input enable. value of 0 disables llock# input. value of 1 enables llock# input, enabling pci-locked sequences. p, l p, l, e 0 1 direct master i/o access enable. value of 0 disables decode of direct master i/o accesses. value of 1 enables decode of direct master i/o accesses. p, l p, l, e 0 0 direct master memory access enable. value of 0 disables decode of direct master memory accesses. value of 1 enables decode of direct master memory accesses. p, l p, l, e 0 section 17 register summary local configuration registers iop 480 data book r2.0 17-36 ? 2000 plx technology, inc. all rights reserved. register 17-75. (dmdac; pci:d4h, loc:d4h) direct master dual address cycle upper address bit description read write value after reset 31:0 direct master pci dual address cycle upper address. during pci dual address cycles provides the upper 32 bits of the pci address for memory cycles. used for 64-bit pci addressing on devices that do not support the 64-bit addressing bus (pci single address cycle), but support 64-bit addressing with an additional address phase (pci dual address cycle). direct master pci dual address cycles are enabled only when this register is a value other than 0. p, l p, l, e 0h register 17-76. (dmlbai; pci:d8h, loc:d8h) local base address register for direct master-to-pci io/cfg bit description read write value after reset 31:16 direct master io/cfg local base address. assigns a value to the bits to use for decoding a local-to-pci i/o or configuration access. p, l p, l, e 0h 15:0 reserved. p, l n o 0 h register 17-77. (dmcfga; pci:dch, loc:dch) pci configuration address register for direct master-to-pci io/cfg bit description read write value after reset 31 configuration enable. value of 1 allows local-to-pci i/o accesses converted to a pci configuration cycle. parameters in this table are used to generate the pci configuration address. p, l p, l , e 0 30:24 reserved. p, l n o 0 h 23:16 bus number. p, l p, l , e 0 h 15:11 device number. p, l p, l , e 0 h 10:8 function number. p, l p, l, e 000 7:2 register number. p, l p, l , e 0 h 1:0 configuration type. values: 00 = type 0 01 = type 1 p, l p, l , e 0 0 section 17 local configuration registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-37 section 17 ? registers register 17-78. (cfgba; pci:e0h, loc:e0h) configuration base address bit description read write value after reset 31:10 configuration base address. defines the base address of the 1 kb address space used to access the configuration registers from the iop 480 cpu or the local bus master. p, l p, l, e 0101_0000_ 0000_0000_ 0000_00 9:0 reserved. p, l n o 0 h register 17-79. (uartba; pci:e4h, loc:e4h) uart base address bit description read write value after reset 31:24 uart base address. defines the base address of the 32-byte address space used to access the uart from the iop 480 cpu or the local bus master. p, l p, l, e 0100_0000 23:0 reserved. p, l n o 0 h register 17-80. (plxid; pci:e8h, loc:e8h) plx hardcoded configuration id bit description read write value after reset 31:16 plx device id. identifies the particular device. hardcoded to the plx part number for the iop 480 (0480h). p, l no 0480h 15:0 plx vendor id. identifies the device manufacturer. hardcoded to the pci sig-issued vendor id of plx (10b5h). p, l n o 1 0 b 5 h register 17-81. (plxrev; pci:ech, loc:ech) plx hardcoded revision id bit description read write value after reset 31:8 reserved. p, l n o 0 h 7:0 plx revision id. hardcoded silicon revision of the iop 480. p, l no current revision section 17 register summary memory controller registers iop 480 data book r2.0 17-38 ? 2000 plx technology, inc. all rights reserved. 17.6 memory controller registers note: this bus region is used for the boot rom if no programmed serial eeprom is detected. register 17-82. (lcs0brd; pci:100h, loc:100h) lcs0 bus region descriptor bit description read write value after reset 31:20 reserved. p, l n o 0 h 19 ready/recover enable. value of 0 indicates the ready# pin is driven only with the iop 480 internal ready status. value of 1 indicates the ready# pin is also driven active during recovery states. can be used to prevent external local bus masters from starting a new cycle until the recovery period expires. p, l p, l, e 0 18:17 read prefetch count. number of words to prefetch when the the direct slave controller or the dma controller is reading this memory. used only when the prefetch count is enabled (lcs0brd[16]=1). values: 00 = don ? t prefetch. only read bytes specified by c/be lines. 01 = prefetch 4 words if bit 16 is set. 10 = prefetch 8 words if bit 16 is set. 11 = prefetch 16 words if bit 16 is set. p, l p, l, e 00 16 read prefetch count enable. value of 0 indicates the count is ignored and prefetching continues until it is terminated by the pci bus or a page boundary is reached. value of 1 indicates the iop 480 prefetches up to the number of words specified by the read prefetch count bits [18:17]. p, l p, l, e 0 15 reserved. p, l p, l, e 0 14 timeout enable. value of 0 indicates the local bus timeout timer is disabled if an external master controls the local bus. value of 1 indicates the local bus timeout timer is enabled if an external master controls the local bus. p, l p, l, e 0 13 parity select. value of 0 indicates even parity is selected. value of 1 indicates odd parity is selected. p, l p, l, e 0 12 parity checking. value of 0 indicates parity checking is disabled. value of 1 indicates parity checking is enabled. when parity is disabled, ma[16:13] are driven out onto the dp[3:0]/ma[16:13] pins if this region is accessed, and a 0 is written to this bit by the serial eeprom or a cpu. p, l p, l, e 0 11 memory write protect. value of 0 indicates the mdqm[3:0]# and mwe# signals are asserted during write cycles. value of 1 indicates the mdqm[3:0]# and mwe# signals are not asserted during write cycles (write protected). p, l p, l, e 0 10 bterm# input enable. value of 0 indicates bterm# input is disabled and the burst length is limited to four words. value of 1 indicates bterm# input is enabled, and bursts continue until bterm# is asserted or the corresponding fifo becomes empty or full. used only when the iop 480 direct slave interface or one of the three internal dma controllers are performing the transfer. p, l p, l, e 0 9 ready# input enable. value of 0 indicates ready# input is disabled, and the number of wait states is determined by the internal wait state generator. value of 1 indicates ready# input is enabled, and determines when a read or write transfer occurs. set to 1 when the enable target device is a peripheral that requires an unknown number of wait states for access. p, l p, l, e 0 section 17 memory controller registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-39 section 17 ? registers 8 burst enable. value of 0 indicates bursting is disabled. value of 1 indicates bursting is enabled and the target device must be able to accept burst transfers. clear bit if the target device can accept only single-cycle transfers. used only when the iop 480 direct slave interface or one of the three internal dma controllers are performing the transfer. burst cycles from the pci direct slave or dma controllers are terminated when a page boundary is reached. the internal iop 480 cpu and external local bus masters should burst only to devices that can accept burst cycles, and must prevent bursting across page boundaries. p, l p, l, e 0 7:5 reserved. p, l no 000 4 iop 480 cpu byte ordering. determines byte ordering when iop 480 cpu is the local bus master. value of 0 indicates that little endian byte ordering is selected. value of 1 indicates that big endian byte ordering is selected. p, l p, l, e 0 3 big endian byte lane mode. value of 0 specifies that in big endian mode byte lanes [15:0] are used for a 16-bit bus, and byte lanes [7:0] for an 8-bit bus. value of 1 specifies that in big endian mode byte lanes [31:16] be used for a 16-bit bus, and byte lanes [31:24] for an 8-bit bus. p, l p, l, e 0 2 direct slave byte ordering. value of 0 indicates that little endian byte ordering is selected. value of 1 indicates that big endian byte ordering is selected. p, l p, l, e 0 1:0 local bus width. specifies data bus width to the devices using this chip select. values: 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved p, l p, l, e 00 register 17-83. (lcs0wt; pci:104h, loc:104h) lcs0 write timing bit description read write value after reset 31:19 reserved. p, l n o 0 h 18:16 wrcv. number of write recovery states (1 ? 8). recovery states = wrcv+1 ( for example , wrcv=001, recovery states = 2). p, l p, l, e 000 15:14 reserved. p, l n o 0 0 13:11 whld. number of write hold (mdqm#, mwe#) states (0 ? 7). p, l p, l, e 000 10:8 wdly. number of write enable (mdqm# and mwe#) delay states (0 ? 7). p, l p, l, e 000 7:4 wdd. number of write data-to-data wait states (0 ? 15). p, l p, l, e 0000 3:0 wad. number of write address-to-data wait states (0 ? 15). p, l p, l, e 0000 register 17-82. (lcs0brd; pci:100h, loc:100h) lcs0 bus region descriptor (continued) bit description read write value after reset section 17 register summary memory controller registers iop 480 data book r2.0 17-40 ? 2000 plx technology, inc. all rights reserved. register 17-84. (lcs0rt; pci:108h, loc:108h) lcs0 read timing bit description read write value after reset 31:19 reserved. p, l n o 0 h 18:16 rrcv. number of read recovery states (1 ? 8: value + 1). p, l p, l, e 111 15:14 reserved. p, l n o 0 0 13:11 rdlyd. number of read enable (rd# and moe#) delay states (0 ? 7). p, l p, l, e 000 10:8 rdlya. number of read enable (rd# and moe#) delay states (0 ? 7). p, l p, l, e 001 7:4 rdd. number of read data-to-data wait states (0 ? 15). p, l p, l, e 0111 3:0 rad. number of read address-to-data wait states (0 ? 15). p, l p, l, e 0111 register 17-85. (lcs0base; pci:10ch, loc:10ch) lcs0 base address bit description read write value after reset 31:8 lcs0# local base address. defines the lcs0 memory region base address. the resolution is 256 bytes. the default base address is 0xfff00000, which allows the internal iop 480 cpu to boot from a serial eeprom at location 0xfffffffc. p, l p, l, e 1111_1111_ 1111_0000_ 0000_0000 7:1 reserved. p, l n o 0 h 0 lcs0# enable. value of 0 indicates that lcs0# is disabled. value of 1 indicates that lcs0# is enabled. because lcs0# is output on a multiplexed pin, the lcs0# function must be selected in the locctl configuration register before using this bus region (locctl[0]). p, l p, l, e 1 register 17-86. (lcs0range; pci:110h, loc:110h) lcs0 range bit description read write value after reset 31:8 lcs0 range. specifies which local address bits to use for decoding accesses to the lcs0 memory region. each bit corresponds to a local address bit. bit 31 corresponds to address bit 31. write 1 to all bits included in decoding. write 0 to all other bits. default is 1 mb. p, l p, l, e 1111_1111_ 1111_0000_ 0000_0000 7:0 reserved. p, l n o 0 h section 17 memory controller registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-41 section 17 ? registers register 17-87. (lcs1brd; pci:114h, loc:114h) lcs1 bus region descriptor bit description read write value after reset 31:20 reserved. p, l n o 0 h 19 ready/recover enable. value of 0 indicates the ready# pin is driven only with the iop 480 internal ready status. value of 1 indicates the ready# pin is also driven active during recovery states. can be used to prevent external local bus masters from starting a new cycle until the recovery period expires. p, l p, l , e 0 18:17 read prefetch count. number of words to prefetch when the direct slave controller or dma controller is reading this memory. only used if prefetch count is enabled (lcs1brd[1]=1). values: 00 = don ? t prefetch. only read bytes specified by c/be lines. 01 = prefetch 4 words if bit 16 is set. 10 = prefetch 8 words if bit 16 is set. 11 = prefetch 16 words if bit 16 is set. p, l p, l , e 0 0 16 read prefetch count enable. value of 0 indicates the count is ignored and prefetching continues until it is terminated by the pci bus or a page boundary is reached. value of 1 indicates the iop 480 prefetches up to the number of words specified by the read prefetch count bits [18:17]. p, l p, l , e 0 15 reserved. p, l n o 0 14 timeout enable. value of 0 indicates that the local bus timeout timer is disabled if an external master controls the local bus. value of 1 indicates the local bus timeout timer is enabled if an external master controls the local bus. p, l p, l , e 0 13 parity select. value of 0 indicates even parity is selected. value of 1 indicates odd parity is selected. p, l p, l , e 0 12 parity checking. value of 0 indicates that parity checking is disabled. value of 1 indicates that parity checking is enabled. when parity is disabled, ma[16:13] are driven out onto the dp[3:0]/ma[16:13] pins if this region is accessed, and a 0 is written to this bit by the serial eeprom or a cpu. p, l p, l , e 0 11 memory write protect. value of 0 indicates the mdqm[3:0]# and mwe# signals are asserted during write cycles. value of 1 indicates the mdqm[3:0]# and mwe# signals are not asserted during write cycles (write-protected). p, l p, l , e 0 10 bterm# input enable. value of 0 indicates that bterm# input is disabled and the burst length is limited to 4 words. value of 1 indicates that bterm# input is enabled, and bursts continue until bterm# is asserted or the corresponding fifo becomes empty or full. used only when the iop 480 direct slave interface or one of the three internal dma controllers are performing the transfer. p, l p, l , e 0 9 ready# input enable. value of 0 indicates that ready# input is disabled, and the number of wait states is determined by the internal wait state generator. value of 1 indicates that ready# input is enabled, and determines when a read or write transfer occurs. enable when the target device is a peripheral that requires an unknown number of wait states for access. p, l p, l , e 0 8 burst enable. value of 0 indicates bursting is disabled. value of 1 indicates bursting is enabled and the target device must be able to accept burst transfers. this bit should be cleared if the target device can accept only single-cycle transfers. used only when the iop 480 direct slave interface or one of the three internal dma controllers are performing the transfer. burst cycles from pci direct slave or dma controllers are terminated when a page boundary is reached. the internal iop 480 cpu and external local bus masters should burst only to devices that can accept burst cycles, and must prevent bursting across page boundaries. p, l p, l , e 0 7:5 reserved. p, l no 000 section 17 register summary memory controller registers iop 480 data book r2.0 17-42 ? 2000 plx technology, inc. all rights reserved. 4 iop 480 cpu byte ordering. determines byte ordering when iop 480 cpu is the local bus master. value of 0 indicates little endian byte ordering is selected. value of 1 indicates big endian byte ordering is selected. p, l p, l , e 0 3 big endian byte lane mode. value of 0 specifies that in big endian mode byte lanes [15:0] are used for a 16-bit bus, and byte lanes [7:0] for an 8-bit bus. value of 1 specifies that in big endian mode byte lanes [31:16] be used for a 16-bit bus, and byte lanes [31:24] for an 8-bit bus. p, l p, l , e 0 2 direct slave byte ordering. value of 0 indicates little endian byte ordering is selected. value of 1 indicates big endian byte ordering is selected. p, l p, l , e 0 1:0 local bus width. specifies data bus width to the devices using this chip select. values: 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved p, l p, l , e 0 0 register 17-88. (lcs1wt; pci:118h, loc:118h) lcs1 write timing bit description read write value after reset 31:19 reserved. p, l n o 0 h 18:16 wrcv. number of write recovery states (1 ? 8: value + 1). p, l p, l, e 000 15:14 reserved. p, l n o 0 0 13:11 whld. number of write hold (mdqm#, mwe#) states (0 ? 7). p, l p, l, e 000 10:8 wdly. number of write enable (mdqm#, mwe#) delay states (0 ? 7). p, l p, l, e 000 7:4 wdd. number of write data-to-data wait states (0 ? 15). p, l p, l, e 0000 3:0 wad. number of write address-to-data wait states (0 ? 15). p, l p, l, e 0000 register 17-89. (lcs1rt; pci:11ch, loc:11ch) lcs1 read timing bit description read write value after reset 31:19 reserved. p, l n o 0 h 18:16 rrcv. number of read recovery states (1 ? 8: value + 1). p, l p, l, e 000 15:14 reserved. p, l n o 0 0 13:11 rdlyd. number of read enable (rd# and moe#) delay states (0 ? 7). p, l p, l, e 000 10:8 rdlya. number of read enable (rd# and moe#) delay states (0 ? 7). p, l p, l, e 001 7:4 rdd. number of read data-to-data wait states (0 ? 15). p, l p, l, e 0000 3:0 rad. number of read address-to-data wait states (0 ? 15). p, l p, l, e 0001 register 17-87. (lcs1brd; pci:114h, loc:114h) lcs1 bus region descriptor (continued) bit description read write value after reset section 17 memory controller registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-43 section 17 ? registers register 17-90. (lcs1base; pci:120ch, loc:120ch) lcs1 base address bit description read write value after reset 31:8 lcs1# local base address. defines the lcs1 memory region base address. the resolution is 256 bytes. p, l p, l , e 0 h 7:1 reserved. p, l n o 0 h 0 lcs1# enable. value of 0 indicates lcs1# is disabled. value of 1 indicates lcs1# is enabled. because lcs1# is output on a multiplexed pin, the lcs1# function must be selected in the locctl configuration register (locctl[1]=0) before using this bus region. p, l p, l , e 0 register 17-91. (lcs1range; pci:124h, loc:124h) lcs1 range bit description read write value after reset 31:8 lcs1 range. specifies which local address bits to use for decoding accesses to the lcs1 memory region. each bit corresponds to a local address bit. bit 31 corresponds to address bit 31. write 1 to all bits included in decoding. write 0 to all other bits. default is 1 mb. p, l p, l , e 1111_1111_ 1111_0000_ 0000_0000 7:0 reserved. p, l n o 0 h register 17-92. (lcs2brd; pci:128h, loc:128h) lcs2 bus region descriptor bit description read write value after reset 31:20 reserved. p, l n o 0 h 19 ready/recover enable. value of 0 indicates the ready# pin is driven only with the iop 480 internal ready status. value of 1 indicates the ready# pin is also driven active during recovery states.can be used to prevent external local bus masters from starting a new cycle until the recovery period expires. p, l p, l , e 0 18:17 read prefetch count. number of words to prefetch when the direct slave controller or dma controller is reading this memory. used only when prefetch count is enabled (lcs2brd[16]=1). values: 00 = don ? t prefetch. only read bytes specified by c/be lines. 01 = prefetch 4 words if bit 16 is set. 10 = prefetch 8 words if bit 16 is set. 11 = prefetch 16 words if bit 16 is set. p, l p, l , e 0 0 16 read prefetch count enable. value of 0 indicates the count is ignored and prefetching continues until it is terminated by the pci bus or a page boundary is reached. value of 1 indicates the iop 480 prefetches up to the number of words specified by the read prefetch count bits [18:17]. p, l p, l , e 0 15 reserved. p, l n o 0 14 timeout enable. value of 0 indicates that the local bus timeout timer is disabled if an external master controls the local bus. value of 1 indicates the local bus timeout timer is enabled if an external master controls the local bus. p, l p, l , e 0 13 parity select. value of 0 indicates even parity is selected. value of 1 indicates odd parity is selected. p, l p, l , e 0 12 parity checking. value of 0 indicates parity checking is disabled. value of 1 indicates parity checking is enabled. when parity is disabled, ma[16:13] is driven out on the dp[3:0]/ma[16:13] pins if this region is accessed, and a 0 is written to this bit by the serial eeprom or a cpu. p, l p, l , e 0 section 17 register summary memory controller registers iop 480 data book r2.0 17-44 ? 2000 plx technology, inc. all rights reserved. 11 memory write protect. value of 0 indicates the mdqm[3:0]# and mwe# signals are asserted during write cycles. value of 1 indicates the mdqm[3:0]# and mwe# signals are not asserted during write cycles (write-protected). p, l p, l , e 0 10 bterm# input enable. value of 0 indicates bterm# input is disabled and the burst length is limited to 4 words. value of 1 indicates bterm# input is enabled, and bursts continue until bterm# is asserted or the corresponding fifo becomes empty or full. used only when the iop 480 pci direct slave interface or one of the three internal dma controllers are performing the transfer. p, l p, l , e 0 9 ready# input enable. value of 0 indicates ready# input is disabled, and the number of wait states is determined by the internal wait state generator. value of 1 indicates ready# input is enabled, and determines when a read or write transfer occurs. enable when the target device is a peripheral that requires an unknown number of wait states for access. p, l p, l , e 0 8 burst enable. value of 0 indicates that bursting is disabled. value of 1 indicates that bursting is enabled and the target device must be able to accept burst transfers. this bit should be cleared if the target device can accept only single-cycle transfers. used only when the iop 480 direct slave interface or one of the three internal dma controllers are performing the transfer. burst cycles from the pci direct slave or dma controllers are terminated when a page boundary is reached. the internal iop 480 cpu and external local bus masters should burst only to devices that can accept burst cycles, and must prevent bursting across page boundaries. p, l p, l , e 0 7:5 reserved. p, l no 000 4 iop 480 cpu byte ordering. determines byte ordering when iop 480 cpu is the local bus master. value of 0 indicates that little endian byte ordering is selected. value of 1 indicates that big endian byte ordering is selected. p, l p, l , e 0 3 big endian byte lane mode. value of 0 specifies that in big endian mode byte lanes [15:0] are used for a 16-bit bus, and byte lanes [7:0] for an 8-bit bus. value of 1 specifies that in big endian mode byte lanes [31:16] be used for a 16-bit bus, and byte lanes [31:24] for an 8-bit bus. p, l p, l , e 0 2 direct slave byte ordering. value of 0 indicates that little endian byte ordering is selected. value of 1 indicates that big endian byte ordering is selected. p, l p, l , e 0 1:0 local bus width. specifies data bus width to the devices using this chip select. values: 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved p, l p, l , e 0 0 register 17-92. (lcs2brd; pci:128h, loc:128h) lcs2 bus region descriptor (continued) bit description read write value after reset section 17 memory controller registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-45 section 17 ? registers register 17-93. (lcs2wt; pci:12ch, loc:12ch) lcs2 write timing bit description read write value after reset 31:19 reserved. p, l n o 0 h 18:16 wrcv. number of write recovery states (1 ? 8: value + 1). p, l p, l, e 000 15:14 reserved. p, l n o 0 0 13:11 whld. number of write hold (mdqm#, mwe#) states (0 ? 7). p, l p, l, e 000 10:8 wdly. number of write enable (mdqm#, mwe#) delay states (0 ? 7). p, l p, l, e 000 7:4 wdd. number of write data-to-data wait states (0 ? 15). p, l p, l, e 0000 3:0 wad. number of write address-to-data wait states (0 ? 15). p, l p, l, e 0000 register 17-94. (lcs2rt; pci:130h, loc:130h) lcs2 read timing bit description read write value after reset 31:19 reserved. p, l n o 0 h 18:16 rrcv. number of read recovery states (1 ? 8: value + 1). p, l p, l, e 000 15:14 reserved. p, l n o 0 0 13:11 rdlyd. number of read enable (rd# and moe#) delay states (0 ? 7). p, l p, l, e 000 10:8 rdlya. number of read enable (rd# and moe#) delay states (0 ? 7). p, l p, l, e 001 7:4 rdd. number of read data-to-data wait states (0 ? 15). p, l p, l, e 0000 3:0 rad. number of read address-to-data wait states (0 ? 15). p, l p, l, e 0001 register 17-95. (lcs2base; pci:134h, loc:134h) lcs2 base address bit description read write value after reset 31:8 lcs2# local base address. defines the lcs2 memory region base address. the resolution is 256 bytes. p, l p, l, e 0h 7:1 reserved. p, l n o 0 h 0 lcs2# enable. value of 0 indicates lcs2# is disabled. value of 1 indicates lcs2# is enabled. because lcs2# is output on a multiplexed pin, the lcs2# function must be selected in the locctl configuration register (locctl[4]=0) before using this bus region. p, l p, l, e 0 register 17-96. (lcs2range; pci:138h, loc:138h) lcs2 range bit description read write value after reset 31:8 lcs2 range. specifies which local address bits to use for decoding accesses to the lcs2 memory region. each bit corresponds to a local address bit. bit 31 corresponds to address bit 31. write 1 to all bits included in decoding. write 0 to all other bits. default is 1 mb. p, l p, l , e 1111_1111_ 1111_0000_ 0000_0000 7:0 reserved. p, l n o 0 h section 17 register summary memory controller registers iop 480 data book r2.0 17-46 ? 2000 plx technology, inc. all rights reserved. register 17-97. (lcs3brd; pci:13ch, loc:13ch) lcs3 bus region descriptor bit description read write value after reset 31:20 reserved. p, l n o 0 h 19 ready/recover enable. value of 0 indicates the ready# pin is driven only with the iop 480 internal ready status. value of 1 indicates the ready# pin is also driven active during recovery states. can be used to prevent external local bus masters from starting a new cycle until the recovery period expires. p, l p, l, e 0 18:17 read prefetch count. number of words to prefetch when the direct slave controller or dma controller is reading this memory. used only when prefetch count is enabled (lcs3brd[16]=1). values: 00 = don ? t prefetch. only read bytes specified by c/be lines. 01 = prefetch 4 words if bit 16 is set. 10 = prefetch 8 words if bit 16 is set. 11 = prefetch 16 words if bit 16 is set. p, l p, l, e 0 16 read prefetch count enable. value of 0 indicates the count is ignored and prefetching continues until it is terminated by the pci bus or a page boundary is reached. value of 1 indicates the iop 480 prefetches up to the number of words specified by the read prefetch count bits [18:17]. p, l p, l, e 0 15 reserved. p, l n o 0 14 timeout enable. value of 0 indicates the local bus timeout timer is disabled if an external master controls the local bus. value of 1 indicates the local bus timeout timer is enabled if an external master controls the local bus. p, l p, l, e 0 13 parity select. value of 0 indicates even parity is selected. value of 1 indicates odd parity is selected. p, l p, l, e 0 12 parity checking. value of 0 indicates parity checking is disabled. value of 1 indicates parity checking is enabled. when parity is disabled, ma[16:13] is driven out on the dp[3:0]/ma[16:13] pins if this region is accessed, and a 0 is written to this bit by the serial eeprom or a cpu. p, l p, l, e 0 11 memory write protect. value of 0 indicates the mdqm[3:0]# and mwe# signals are asserted during write cycles. value of 1 indicates the mdqm[3:0]# and mwe# signals are not asserted during write cycles (write-protected). p, l p, l, e 0 10 bterm# input enable. value of 0 indicates that bterm# input is disabled and the burst length is limited to 4 words. value of 1 indicates that bterm# input is enabled, and bursts continue until bterm# is asserted or the corresponding fifo becomes empty or full. used only when the iop 480 direct slave interface or one of the three internal dma controllers are performing the transfer. p, l p, l, e 0 9 ready# input enable. value of 0 indicates the ready# input is disabled, and the number of wait states is determined by the internal wait state generator. value of 1 indicates the ready# input is enabled, and determines when a read or write transfer occurs. enable this bit when the target device is a peripheral that requires an unknown number of wait states for accesses. p, l p, l, e 0 8 burst enable. value of 0 indicates that bursting is disabled. value of 1 indicates that bursting is enabled and the target device must be able to accept burst transfers. clear this bit if the target device can only accept single-cycle transfers. used only when the iop 480 direct slave interface or one of the three internal dma controllers are performing the transfer. burst cycles from the pci direct slave or dma controllers are terminated when a page boundary is reached. the internal iop 480 cpu and external local bus masters should burst only to devices that can accept burst cycles, and must prevent bursting across page boundaries. p, l p, l, e 0 7:5 reserved. p, l no 000 section 17 memory controller registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-47 section 17 ? registers 4 iop 480 cpu byte ordering. determines byte ordering when iop 480 cpu is the local bus master. value of 0 indicates that little endian byte ordering is selected. value of 1 indicates that big endian byte ordering is selected. p, l p, l, e 0 3 big endian byte lane mode. value of 0 specifies that in big endian mode byte lanes [15:0] are used for a 16-bit bus, and byte lanes [7:0] for an 8-bit bus. value of 1 specifies that in big endian mode byte lanes [31:16] be used for a 16-bit bus, and byte lanes [31:24] for an 8-bit bus. p, l p, l, e 0 2 direct slave byte ordering. value of 0 indicates that little endian byte ordering is selected. value of 1 indicates that big endian byte ordering is selected. p, l p, l, e 0 1:0 local bus width. specifies data bus width to the devices using this chip select. values: 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved p, l p, l, e 00 register 17-98. (lcs3wt; pci:140h, loc:140h) lcs3 write timing bit description read write value after reset 31:19 reserved. p, l n o 0 h 18:16 wrcv. number of write recovery states (1 ? 8: value + 1). p, l p, l, e 000 15:14 reserved. p, l n o 0 0 13:11 whld. number of write hold (mdqm#, mwe#) states (0 ? 7). p, l p, l, e 000 10:8 wdly. number of write enable (mdqm#, mwe#) delay states (0 ? 7). p, l p, l, e 000 7:4 wdd. number of write data-to-data wait states (0 ? 15). p, l p, l, e 0000 3:0 wad. number of write address-to-data wait states (0 ? 15). p, l p, l, e 0000 register 17-99. (lcs3rt; pci:144h, loc:144h) lcs3 read timing bit description read write value after reset 31:19 reserved. p, l n o 0 h 18:16 rrcv. number of read recovery states (1 ? 8: value + 1). p, l p, l, e 000 15:14 reserved. p, l n o 0 0 13:11 rdlyd. number of read enable (rd# and moe#) delay states (0 ? 7). p, l p, l, e 000 10:8 rdlya. number of read enable (rd# and moe#) delay states (0 ? 7). p, l p, l, e 001 7:4 rdd. number of read data-to-data wait states (0 ? 15). p, l p, l, e 0000 3:0 rad. number of read address-to-data wait states (0 ? 15). p, l p, l, e 0001 register 17-97. (lcs3brd; pci:13ch, loc:13ch) lcs3 bus region descriptor (continued) bit description read write value after reset section 17 register summary memory controller registers iop 480 data book r2.0 17-48 ? 2000 plx technology, inc. all rights reserved. register 17-100. (lcs3base; pci:148h, loc:148h) lcs3 base address bit description read write value after reset 31:8 lcs3# local base address. defines the lcs3 memory region base address. the resolution is 256 bytes. p, l p, l, e 0h 7:1 reserved. p, l n o 0 h 0 lcs3# enable. value of 0 indicates that lcs3# is disabled. value of 1 indicates that lcs3# is enabled. because lcs3# is output on a multiplexed pin, the lcs3# function must be selected in the locctl configuration register (locctl[7]=0) before using this bus region. p, l p, l, e 0 register 17-101. (lcs3range; pci:14ch, loc:14ch) lcs3 range bit description read write value after reset 31:8 lcs3 range. specifies which local address bits to use for decoding accesses to the lcs3 memory region. each bit corresponds to a local address bit. bit 31 corresponds to address bit 31. write 1 to all bits included in decoding. write 0 to all other bits. default is 1 mb. p, l p, l , e 1111_1111_ 1111_0000_ 0000_0000 7:0 reserved. p, l n o 0 h register 17-102. (drambrd; pci:150h, loc:150h) dram bus region descriptor bit description read write value after reset 31:20 reserved. p, l n o 0 h 19 ready/recover enable. value of 0 indicates the ready# pin is driven only with the iop 480 internal ready status. value of 1 indicates the ready# pin is also driven active during recovery states. can be used to prevent external local bus masters from starting a new cycle until the recovery period expires. p, l p, l , e 0 18:17 read prefetch count. number of words to prefetch when the direct slave controller or dma controller is reading this memory. used only when prefetch count is enabled (drambrd[16]=1). values: 00 = don ? t prefetch. only read bytes specified by c/be lines. 01 = prefetch 4 words if bit 16 is set. 10 = prefetch 8 words if bit 16 is set. 11 = prefetch 16 words if bit 16 is set. p, l p, l , e 0 0 16 read prefetch count enable. value of 0 indicates the count is ignored and prefetching continues until it is terminated by the pci bus or a page boundary is reached. value of 1 indicates the iop 480 prefetches up to the number of words specified by the read prefetch count bits [18:17]. p, l p, l , e 0 15:14 reserved. p, l n o 0 0 13 parity select. value of 0 indicates even parity is selected. value of 1 indicates odd parity is selected. p, l p, l , e 0 12 parity checking. value of 0 indicates that parity checking is disabled. value of 1 indicates that parity checking is enabled. when parity is disabled, zeros are driven out on the dp[3:0]/ma[16:13] pins if this region is accessed, and a 0 is written to this bit by the serial eeprom or a cpu. p, l p, l , e 0 11 memory write protect. value of 0 indicates the mdqm[3:0]# (for sdram) and mwe# (for edo) signals are asserted during write cycles. value of 1 indicates the mdqm[3:0]# (for sdram) and mwe# (for edo) signals are not asserted during write cycles (write-protected). p, l p, l , e 0 section 17 memory controller registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-49 section 17 ? registers 10 bterm# input enable. value of 0 indicates that bterm# input is disabled and the burst length is limited to 4 words. value of 1 indicates that bterm# input is enabled, and bursts continue until bterm# is asserted or the corresponding fifo becomes empty or full. used only when the iop 480 direct slave interface or one of the three internal dma controllers are performing the transfer. p, l p, l , e 0 9 reserved. p, l n o 0 8 burst enable. value of 0 indicates that bursting is disabled. value of 1 indicates that bursting is enabled and the target device must be able to accept burst transfers. this bit should be cleared if the target device can accept only single-cycle transfers. used only when the iop 480 direct slave interface or one of the three internal dma controllers are performing the transfer. burst cycles from pci direct slave or dma controllers are terminated when a page boundary is reached. the internal iop 480 cpu and external local bus masters should burst only to devices that can accept burst cycles, and must prevent bursting across page boundaries. p, l p, l , e 0 7:5 reserved. p, l n o 0 0 0 4 iop 480 cpu byte ordering. determines byte ordering when iop 480 cpu is the local bus master. value of 0 indicates that little endian byte ordering is selected. value of 1 indicates that big endian byte ordering is selected. p, l p, l , e 0 3 big endian byte lane mode. value of 0 specifies that in big endian mode byte lanes [15:0] are used for a 16-bit bus, and byte lanes [7:0] for an 8-bit bus. value of 1 specifies that in big endian mode byte lanes [31:16] be used for a 16-bit bus, and byte lanes [31:24] for an 8-bit bus. p, l p, l , e 0 2 direct slave byte ordering. value of 0 indicates that little endian byte ordering is selected. value of 1 indicates that big endian byte ordering is selected. p, l p, l , e 0 1:0 local bus width. specifies data bus width to the devices using this chip select. values: 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved p, l p, l , e 0 0 register 17-102. (drambrd; pci:150h, loc:150h) dram bus region descriptor (continued) bit description read write value after reset section 17 register summary memory controller registers iop 480 data book r2.0 17-50 ? 2000 plx technology, inc. all rights reserved. note: this register cannot be written to until all other dram registers have been set up, including enabling the sdram reload initialization bit (dram initialization [14]) and enabling the dram enable bit (dram base address [0]). writing to this register prior to this crashes the memory controller. register 17-103. (dramctl; pci:154h, loc:154h) dram control bit description read write value after reset 31:24 reserved. p, l n o 0 h 23 refresh enable. value of 0 indicates that refresh cycles are disabled. value of 1 indicates that refresh cycles are enabled. p, l p, l, e 1 22:12 refresh interval. determines the interval between refresh cycles in terms of lclk clock cycles. the value can be calculated as follows: reg value = refresh rate x lclk clock frequency. typically: reg value = 15.625 s x 66.666 mhz = 1041 = 0x411. p, l p, l, e 100_0000_0111 11:10 self-refresh level. determines the power management level at which an sdram initiates low-power auto-refresh mode. values: 00 = no self-refresh (fully operational) 01 = self-refresh when in power management state d 1 or higher 10 = self-refresh when in power management state d 2 or higher 11 = self-refresh when in power management state d 3 p, l p, l, e 10 9 page mode enable. value of 0 indicates page mode is disabled. value of 1 indicates page mode is enabled. if page mode is enabled, the cas_mdqm[3:0]# pins are not asserted during sram cycles. p, l p, l, e 0 8:6 number of columns. values: 000 8 columns 001 9 columns 010 10 columns 011 11 columns 100 12 columns 101-111 reserved p, l p, l, e 000 5:4 reserved. p, l n o 0 0 3:1 bank size. these bits set the maximum addressable memory size for each of the four banks of the iop 480. total addressable memory is four times the chosen bank size. values: 000 4 mb 001 8 mb 010 16 mb 011 32 mb 100 64 mb 101-111 reserved p, l p, l, e 000 0 dram type. value of 0 indicates that edo drams are selected. value of 1 indicates that sdrams are selected. p, l p, l, e 0 section 17 memory controller registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-51 section 17 ? registers register 17-104. (draminit; pci:158h, loc:158h) dram initialization bit description read write value after reset 31:17 reserved. p, l n o 0 h 16 sdram initialization status. initialized to 1 at reset, and automatically cleared when an sdram initialization is complete p, l n o 1 15 sdram initialization order. value of 0 indicates that ? load mode ? command is followed by eight refresh cycles during initialization. value of 1 indicates that eight refresh cycles are followed by ? load mode ? command during initialization. cleared when sdram initialization completes. p, l p, l, e 0 14 reload sdram initialization word. write this bit to reload the sdram initialization word with bits [13:0]. automatically cleared when initialization completes. p, l s e t 0 13:0 sdram initialization word. described in the iop 480 memory controller specification. determines the sdram operating modes. the value in these bits is automatically loaded into the sdram at power-on. also used by the sram memory controller for determining the cas latency value programmed into the sdrams. this bit must not be changed to a value other than that present when the sdram initialization occurs. p, l p, l, e 00_0000_0010_ 0111 section 17 register summary memory controller registers iop 480 data book r2.0 17-52 ? 2000 plx technology, inc. all rights reserved. register 17-105. (dramtim; pci:15ch, loc:15ch) dram timing bit description read write value after reset 31:22 reserved. p, l n o 0 h 21:20 twr. delay between the last word written during a single or burst write cycle and a precharge command. values clock period(s) 00 0 01 1 10 2 11 3 p, l p, l , e 0 0 19:18 w2w. delay between words of a burst write for an sdram write cycle. values clock period(s) 00 0 01 1 10 2 11 3 p, l p, l , e 0 0 17:16 a2c. active to read/write command delay for an sdram read or write cycle. values clock period(s) 00 1 01 2 10 3 11 4 p, l p, l , e 0 1 15:14 reserved. p, l n o 0 13:12 rrcv. number of recovery states after the end of a single or burst edo or an sdram read cycle. used to provide the device with time to float its outputs. values clock period(s) 00 1 01 2 10 3 11 4 p, l p, l , e 0 1 11:10 prcg. ras precharge delay for edo or sdrams. values clock period(s) 00 1 01 2 10 3 11 4 p, l p, l , e 1 0 9:8 wcw. cas pulse width for an edo write cycle. values clock period(s) 00 1 01 2 10 3 11 4 p, l p, l , e 0 0 section 17 memory controller registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-53 section 17 ? registers 7:6 rcw. cas pulse width for edo read cycle. values clock period(s) 00 1 01 2 10 3 11 4 p, l p, l , e 0 0 5:4 c2c. delay from column address to cas for edo cycle. values clock period(s) 00 1 01 2 10 3 11 4 p, l p, l , e 0 0 3:2 r2c. delay from ras to column address for edo cycle. values clock period(s) 00 1 01 2 10 3 11 4 p, l p, l , e 01 1:0 r2r. delay from row address to ras for edo cycle. values clock period(s) 00 1 01 2 10 3 11 4 p, l p, l , e 0 0 register 17-106. (drambase; pci:160h, loc:160h) dram base address bit description read write value after reset 31:22 dram local base address. defines the dram memory region base address. the resolution is 4 mb. p, l p, l, e 0h 21:1 reserved. p, l n o 0 h 0 dram enable. value of 0 indicates the dram controller is disabled. value of 1 indicates the dram controller is enabled. p, l p, l, e 0 register 17-107. (dramrange; pci:164h, loc:164h) dram range bit description read write value after reset 31:22 dram range. specifies which local address bits to use for decoding accesses to the dram memory region. each bit corresponds to a local address bit. bit 31 corresponds to address bit 31. write 1 to all bits included in decoding. write 0 to all other bits. default is 4 mb. p, l p, l, e 1111_1111_11 21:0 reserved. p, l n o 0 h register 17-105. (dramtim; pci:15ch, loc:15ch) dram timing (continued) section 17 register summary memory controller registers iop 480 data book r2.0 17-54 ? 2000 plx technology, inc. all rights reserved. note: the following bus parameters are used when accesses to the local bus by the iop 480 (pci, dma, or internal iop 480 cpu) do not fall into one of the five memory spaces. there are no programmable timing parameters for this space, and all cycles are termina ted with bterm# or ready#. register 17-108. (dfltbrd; pci:168h, loc:168h) default bus region descriptor bit description read write value after reset 31:19 reserved. p, l n o 0 h 18:17 read prefetch count. number of words to prefetch when the direct slave controller or dma controller is reading this memory. used only when the prefetch count is enabled (dfltbrd[16]=1). values: 00 = don ? t prefetch. only read bytes specified by c/be lines. 01 = prefetch 4 words if bit 16 is set. 10 = prefetch 8 words if bit 16 is set. 11 = prefetch 16 words if bit 16 is set. p, l p, l, e 00 16 read prefetch count enable. value of 0 indicates the count is ignored and prefetching continues until it is terminated by the pci bus or a page boundary is reached. value of 1 indicates the iop 480 prefetches up to the number of words specified by the read prefetch count bits [18:17]. p, l p, l, e 0 15 timeout ready out enable. value of 0 indicates the ready# pin is not driven when a timeout during accesses to a device in the default region is detected. value of 1 indicates the ready# pin is driven when a timeout is detected during accesses to a device in the default region. p, l p, l 0 14 timeout enable. value of 0 indicates the local bus timeout timer is disabled if an external master controls the local bus. value of 1 indicates the local bus timeout timer is enabled if an external master controls the local bus. p, l p, l, e 0 13 parity select. value of 0 indicates even parity is selected. value of 1 indicates odd parity is selected. p, l p, l, e 0 12 parity checking. value of 0 indicates parity checking is disabled. value of 1 indicates parity checking is enabled. when parity is disabled, ma[16:13] is driven out on the dp[3:0]/ma[16:13] pins if this region is accessed, and a 0 is written to this bit by the serial eeprom or a cpu. p, l p, l, e 0 11 memory write protect. value of 0 indicates the mdqm[3:0]# and mwe# signals are asserted during write cycles. value of 1 indicates the mdqm[3:0]# and mwe# signals are not asserted during write cycles (write-protected). p, l p, l, e 0 10 bterm# input enable. value of 0 indicates bterm# input is disabled and the burst length is limited to four words. value of 1 indicates bterm# input is enabled, and bursts continue until bterm# is asserted or the corresponding fifo becomes empty or full. used only when the iop 480 direct slave interface or one of the three internal dma controllers are performing the transfer. p, l p, l, e 0 9 reserved. p, l n o 0 8 burst enable. value of 0 indicates that bursting is disabled. value of 1 indicates bursting is enabled and that the target device must be able to accept burst transfers. clear this bit if the target device can only accept single-cycle transfers. used only when the iop 480 direct slave interface or one of the three internal dma controllers are performing the transfer. burst cycles from the pci direct slave or dma controllers are terminated when a page boundary is reached. the internal iop 480 cpu and external local bus masters should burst only to devices that can accept burst cycles, and must prevent bursting across page boundaries. p, l p, l, e 0 7:5 reserved. p, l no 000 section 17 memory controller registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-55 section 17 ? registers 4 iop 480 cpu byte ordering. determines byte ordering when iop 480 cpu is the local bus master. value of 0 indicates that little endian byte ordering is selected. value of 1 indicates that big endian byte ordering is selected. p, l p, l, e 0 3 big endian byte lane mode. value of 0 specifies that in big endian mode byte lanes [15:0] are used for a 16-bit bus, and byte lanes [7:0] for an 8-bit bus. value of 1 specifies that in big endian mode byte lanes [31:16] be used for a 16-bit bus, and byte lanes [31:24] for an 8-bit bus. p, l p, l, e 0 2 direct slave byte ordering. value of 0 indicates that little endian byte ordering is selected. value of 1 indicates that big endian byte ordering is selected. p, l p, l, e 0 1:0 local bus width. specifies the data bus width to the default devices. values: 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = reserved p, l p, l, e 10 register 17-108. (dfltbrd; pci:168h, loc:168h) default bus region descriptor (continued) bit description read write value after reset section 17 register summary runtime registers iop 480 data book r2.0 17-56 ? 2000 plx technology, inc. all rights reserved. 17.7 runtime registers register 17-109. (mbox0; pci:180h, loc:180h) mailbox 0 bit description read write value after reset 31:0 32-bit mailbox register. p, l p, l, e 0h register 17-110. (mbox1; pci:184h, loc:184h) mailbox 1 bit description read write value after reset 31:0 32-bit mailbox register. p, l p, l , e 0 h register 17-111. (mbox2; pci:188h, loc:188h) mailbox 2 bit description read write value after reset 31:0 32-bit mailbox register. p, l p, l 0 h register 17-112. (mbox3; pci:18ch, loc:18ch) mailbox 3 bit description read write value after reset 31:0 32-bit mailbox register. p, l p, l 0 h register 17-113. (mbox4; pci:190h, loc:190h) mailbox 4 bit description read write value after reset 31:0 32-bit mailbox register. p, l p, l 0h register 17-114. (mbox5; pci:194h, loc:194h) mailbox 5 bit description read write value after reset 31:0 32-bit mailbox register. p, l p, l 0 h register 17-115. (mbox6; pci:198h, loc:198h) mailbox 6 bit description read write value after reset 31:0 32-bit mailbox register. p, l p, l 0h section 17 runtime registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-57 section 17 ? registers register 17-116. (mbox7; pci:19ch, loc:19ch) mailbox 7 bit description read write value after reset 31:0 32-bit mailbox register. p, l p, l 0 h register 17-117. (p2ldbell; pci:1a0h, loc:1a0h) pci-to-local doorbell bit description read write value after reset 31:0 doorbell register. a pci master can write to this register and generate a local interrupt to the local processor. the local processor can then read this register to determine which doorbell bit was asserted. the pci master sets a doorbell by writing 1 to a particular bit. the local processor can clear a doorbell bit by writing 1 to that bit position. p, l p, l/clr 0h register 17-118. (l2pdbell; pci:1a4h, loc:1a4h) local-to-pci doorbell bit description read write value after reset 31:0 doorbell register. the local processor can write to this register and generate a pci interrupt. the pci master can then read this register to determine which doorbell bit was asserted. the local processor sets a doorbell by writing 1 to a particular bit. the pci master can clear a doorbell bit by writing 1 to that bit position. p, l p, l/clr 0h section 17 register summary runtime registers iop 480 data book r2.0 17-58 ? 2000 plx technology, inc. all rights reserved. note: the following bits determine when inta# is asserted when enabled by pintenb[0]. register 17-119. (pintstat; pci:1b0h, loc:1b0h) pci interrupt status bit description read write value after reset 31:20 reserved. p, l n o 0 h 19 target abort generated. value of 1 indicates a target abort was generated by the iop 480 after 256 consecutive master retries to a target. p, l n o 0 18 dma channel 1 ? master or target abort detected. value of 1 indicates dma channel 1 was the bus master during a master or target abort. p, l n o 0 17 dma channel 0 ? master or target abort detected. value of 1 indicates dma channel 0 was the bus master during a master or target abort. p, l n o 0 16 direct master ? master or target abort detected. value of 1 indicates a direct master was the bus master during a master or target abort. p, l n o 0 15:14 reserved. p, l n o 0 0 13 pci abort interrupt. value of 1 indicates the pci abort interrupt is active. p, l no 0 12 local interrupt. value of 1 indicates the local interrupt is active. p, l no 0 11 pci doorbell interrupt. value of 1 indicates the pci doorbell interrupt is active. p, l n o 0 10 dma channel 2 interrupt. value of 1 indicates the dma ch 2 interrupt is active. p, l n o 0 9 dma channel 1 interrupt. value of 1 indicates the dma ch 1 interrupt is active. p, l n o 0 8 dma channel 0 interrupt. value of 1 indicates the dma ch 0 interrupt is active. p, l n o 0 7:1 reserved. p, l n o 0 h 0 generate pci bus serr#. changing the value from 0 to 1 generates a pci bus serr#. p, l p, l 0 section 17 runtime registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-59 section 17 ? registers register 17-120. (pintenb; pci:1b4h, loc:1b4h) pci interrupt enable bit description read write value after reset 31:14 reserved. p, l n o 0 h 13 pci abort interrupt enable. value of 1 enables a master abort or master detect of a target abort to generate a pci interrupt. used in conjunction with pci interrupt enable. clearing the abort status bit pcisr[13] also clears the pci interrupt. p, l p, l 0 12 pci local interrupt enable. value of 1 enables a local interrupt to generate a pci interrupt. use in conjunction with the pci interrupt enable bit pintenb[13]. clearing the local bus cause of the interrupt also clears the interrupt. p, l p, l 0 11 pci doorbell interrupt enable. value of 1 enables doorbell interrupts. used in conjunction with pci interrupt enable. clearing the doorbell interrupt bits that caused the interrupt also clears the interrupt. p, l p, l 0 10 dma ch 2 interrupt enable. value of 1 enables a pci interrupt to generate when the dma controller channel 2 is done or has reached a terminal count. p, l p, l 0 9 dma ch 1 interrupt enable. value of 1 enables a pci interrupt to generate when the dma controller channel 1 is done or has reached a terminal count. p, l p, l 0 8 dma ch 0 interrupt enable. value of 1 enables a pci interrupt to generate when the dma controller channel 0 is done or has reached a terminal count. p, l p, l 0 7:1 reserved. p, l n o 0 h 0 pci interrupt output enable. value of 1 enables pci interrupts. p, l p, l 1 section 17 register summary runtime registers iop 480 data book r2.0 17-60 ? 2000 plx technology, inc. all rights reserved. note: the following bits determine when into is asserted, assuming they are enabled in the lintenb register. into also drives the iop 480 cpu external interrupt input. register 17-121. (lintstat; pci:1b8h, loc:1b8h) local interrupt status bit description read write value after reset 31 mailbox 7 interrupt. value of 1 indicates the pci wrote data to mailbox 7. to clear the local interrupt, the local master must read the mailbox. p, l n o 0 30 mailbox 6 interrupt. value of 1 indicates the pci wrote data to mailbox 6. to clear the local interrupt, the local master must read the mailbox. p, l n o 0 29 mailbox 5 interrupt. value of 1 indicates the pci wrote data to mailbox 5. to clear the local interrupt, the local master must read the mailbox. p, l n o 0 28 mailbox 4 interrupt. value of 1 indicates the pci wrote data to mailbox 4. to clear the local interrupt, the local master must read the mailbox. p, l n o 0 27 mailbox 3 interrupt. value of 1 indicates the pci wrote data to mailbox 3. to clear the local interrupt, the local master must read the mailbox. p, l n o 0 26 mailbox 2 interrupt. value of 1 indicates the pci wrote data to mailbox 2. to clear the local interrupt, the local master must read the mailbox. p, l n o 0 25 mailbox 1 interrupt. value of 1 indicates the pci wrote data to mailbox 1. to clear the local interrupt, the local master must read the mailbox. p, l n o 0 24 mailbox 0 interrupt. value of 1 indicates the pci wrote data to mailbox 0. to clear the local interrupt, the local master must read the mailbox. p, l n o 0 23:22 reserved . p, l n o 0 0 21 refresh local interrupt status. value of 1 indicates a refresh local interrupt occurs. writing a 1 clears the interrupt. the refresh int is set when two refresh requests occur without a grant occurring between the two requests. value of 0 indicates that no refresh local interrupt occurs. p, l p/clr, l/clr 0 20 pci serr interrupt. value of 1 indicates that an interrupt was received on the serr# pin. writing a 1 clears the interrupt. p, l p, l/clr 0 19:17 reserved . p, l no 000 16 pci enum# interrupt. value of 1 indicates the enum# pin received an interrupt. writing a 1 clears the interrupt. p, l p, l/clr 0 15 pci pme# interrupt. value of 1 indicates the pme# pin received an interrupt. writing a 1 clears the interrupt. p, l p, l/clr 0 14 pci inta# interrupt. value of 1 indicates the inta# pin received an interrupt. writing a 1 clears the interrupt. p, l p, l/clr 0 13 power management interrupt. value of 1 indicates a power management interrupt is pending. a power management interrupt is caused by a change in the power state bits (pmcsr[1:0]). writing a 1 clears the interrupt. p, l p, l/clr 0 12 bist interrupt. value of 1 indicates bist interrupt is active. a bist (built-in self test) interrupt is generated by writing 1 to the bist interrupt bit (pcibist[6]=1). clearing (pcibist[6]), clears the interrupt. refer to the pcibistr register for a description of self test. p, l n o 0 11 local doorbell interrupt. value of 1 indicates local doorbell interrupt is active. clearing the local doorbell interrupt clears the interrupt and, as a result, the local doorbell interrupt is de-activated. p, l n o 0 10 channel 2 dma interrupt. value of 1 indicates the dma ch 2 interrupt is active. clearing the dma status bits also clears the interrupt. p, l n o 0 9 channel 1 dma interrupt. value of 1 indicates the dma ch 1 interrupt is active. clearing the dma status bits also clears the interrupt. p, l n o 0 8 channel 0 dma interrupt. value of 1 indicates the dma ch 0 interrupt is active. clearing the dma status bits also clears the interrupt. p, l n o 0 section 17 runtime registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-61 section 17 ? registers 7 inti interrupt. value of 1 indicates an interrupt is pending on the inti pin. writing a 1 clears the interrupt. p, l p, l/clr 0 6 local bus parity error. value of 1 indicates that a local bus parity error has occurred. writing a 1 clears the interrupt. p, l p, l/clr 0 5 serial port interrupt 2. value of 1 indicates the serial port interrupt 2 is active. p, l n o 0 4 serial port interrupt 1. value of 1 indicates the serial port interrupt 1 is active. p, l n o 0 3 local bus timeout interrupt. value of 1 indicates a local bus timeout has occurred. writing a 1 clears the interrupt. p, l p, l/clr 0 2 pci error interrupt. value of 1 indicates a pci parity error or messaging queue outbound free queue overflow interrupt is active. p, l n o 0 1 pci abort interrupt. value of 1 indicates a pci master or target abort status is active. p, l n o 0 0 reserved. p, l n o 0 register 17-122. (lintenb; pci:1bch, loc:1bch) local interrupt enable bit description read write value after reset 31 mailbox 7 interrupt enable. value of 1 enables a local interrupt generated when the pci bus writes to mailbox 7. p, l p, l 0 30 mailbox 6 interrupt enable. value of 1 enables a local interrupt generated when the pci bus writes to mailbox 6. p, l p, l 0 29 mailbox 5 interrupt enable. value of 1 enables a local interrupt generated when the pci bus writes to mailbox 5. p, l p, l 0 28 mailbox 4 interrupt enable. value of 1 enables a local interrupt generated when the pci bus writes to mailbox 4. p, l p, l 0 27 mailbox 3 interrupt enable. value of 1 enables a local interrupt generated when the pci bus writes to mailbox 3. p, l p, l 0 26 mailbox 2 interrupt enable. value of 1 enables a local interrupt generated when the pci bus writes to mailbox 2. p, l p, l 0 25 mailbox 1 interrupt enable. value of 1 enables a local interrupt generated when the pci bus writes to mailbox 1. p, l p, l 0 24 mailbox 0 interrupt enable. value of 1 enables a local interrupt generated when the pci bus writes to mailbox 0. p, l p, l 0 23:22 reserved. p, l n o 0 0 21 refresh local interrupt enable. value of 1 indicates the refresh local interrupt is enabled. the refresh int is set when two refresh requests occur without a grant occurring between the two requests. value of 0 indicates the refresh local interrupt is disabled. p, l p, l 0 20 pci serr interrupt enable reserved. value of 1 enables a local interrupt to generate when the pci serr# pin is asserted. p, l p, l 0 19 cint polarity. value of 1 indicates active high polarity for the cint interrupt input. value of 0 indicates active low polarity for the cint interrupt input. p, l p, l 0 18 inti polarity. value of 1 indicates active high polarity for the inti interrupt input. value of 0 indicates active low polarity for the inti interrupt input. p, l p, l 0 register 17-121. (lintstat; pci:1b8h, loc:1b8h) local interrupt status (continued) bit description read write value after reset section 17 register summary runtime registers iop 480 data book r2.0 17-62 ? 2000 plx technology, inc. all rights reserved. 17 into polarity. value of 1 indicates active high polarity for the into interrupt output. value of 0 indicates active low polarity for the into interrupt output. p, l p, l 0 16 pci enum# interrupt enable. value of 1 enables a local interrupt to generate when the pci enum# pin is asserted. p, l p, l 0 15 pci pme interrupt enable. value of 1 enables a local interrupt to generate when the pci pme# pin is asserted. p, l p, l 0 14 pci inta interrupt enable. value of 1 enables a local interrupt to generate when the pci inta# pin is asserted. p, l p, l 0 13 power management interrupt enable. value of 1 enables a local interrupt to generate when the power management power state changes (pmcsr[1:0]). p, l p, l 0 12 bist interrupt enable. value of 1 enables a local interrupt to generate when the built-in self test interrupt bit is set (pcibist[6]=1) by the pci host. p, l p, l 0 11 local doorbell interrupt enable. value of 1 enables doorbell interrupts. used in conjunction with local interrupt enable. p, l p, l 0 10 local dma channel 2 interrupt enable. value of 1 enables dma channel 2 interrupts. used in conjunction with local interrupt enable. p, l p, l 0 9 local dma channel 1 interrupt enable. value of 1 enables dma channel 1 interrupts. used in conjunction with local interrupt enable. p, l p, l 0 8 local dma channel 0 interrupt enable. value of 1 enables dma channel 0 interrupts. used in conjunction with local interrupt enable. clearing the dma status bits also clears the interrupt. p, l p, l 0 7 inti interrupt enable. value of 1 enables an interrupt to generate if the inti pin is asserted. p, l p, l 0 6 local parity error interrupt enable. value of 1 enables a local interrupt to generate if a local parity error is detected. p, l p, l 0 5 serial port interrupt 2 enable. value of 1 enables a local interrupt when serial port interrupt 2 is active. p, l p, l 0 4 serial port interrupt 1 enable. value of 1 enables a local interrupt when serial port interrupt 1 is active. p, l p, l 0 3 local timeout interrupt enable. value of 1 enables a local interrupt when a local bus timeout occurs. p, l p, l 0 2 pci bus parity error interrupt enable. value of 1 enables a local interrupt when a pci parity error is detected or the outbound free messaging queue overflows. p, l p, l 0 1 pci abort interrupt enable. value of 1 enables a local interrupt output when a direct slave bit (pcisr[12]) or master abort status bit (pcisr[13]) is set in the pci status configuration register. p, l p, l 0 0 local interrupt output enable. value of 1 enables local interrupt output. p, l p, l 1 register 17-123. (pabtadr; pci:1c0h, loc:1c0h) pci abort address bit description read write value after reset 31:2 pci abort address. when a pci master/target abort occurs, the starting address of the current access is returned to this register. p, l no 32'h0000_0000 1:0 reserved. no no 0 register 17-122. (lintenb; pci:1bch, loc:1bch) local interrupt enable (continued) bit description read write value after reset section 17 dma registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-63 section 17 ? registers 17.8 dma registers register 17-124. (c0mode; pci:200h, loc:200h) channel 0 mode bit description read write value after reset 31:21 reserved. p, l n o 0 h 20 eot0# end link. used only for dma scatter/gather transfers. when eot0# is asserted, value of 1 indicates the dma transfer ends the current scatter/ gather link and continues with the remaining scatter/gather transfers. when eot0# is asserted, value of 0 indicates the dma transfer ends the current scatter/gather transfer and does not continue with the remaining scatter/ gather transfers. p, l p, l 0 19 valid stop control. value of 0 indicates the dma chaining controller continuously polls a descriptor with the valid bit set to 0 (invalid descriptor) if the valid mode enable bit (c0mode[18]=1) is set. value of 1 indicates the chaining controller stops polling when the valid bit with a value of 0 is detected (c0count[31]=0). in this case, the cpu must restart the dma controller by setting the start bit (c0csr[1]=1). a pause sets the dma done register. p, l p, l 0 18 valid mode enable. value of 0 indicates the valid bit (c0count[31]) is ignored. value of 1 indicates the dma descriptors are processed only when the valid bit is set (c0count[31]). if the valid bit is set, the transfer count is 0, and the descriptor is not the last descriptor in the chain. the dma controller then moves to the next descriptor in the chain. p, l p, l 0 17 pci dual address scatter/gather. value of 0 indicates that normal address cycles are used during descriptor scatter/gather operations. value of 1 indicates that pci dual address cycles are used during descriptor scatter/gather operations (load c0pcihadr[31:0]). p, l p, l 0 16 dma clear count mode. value of 1 indicates the byte count in each scatter/gather descriptor is cleared when the corresponding dma transfer is complete. if this bit is enabled and scatter/gather dma has been stopped by eot, the writeback cycle writes back to the current descriptor the number of bytes remaining to be transferred. p, l p, l 0 15 dma fast/slow terminate mode select. value of 0 asserts blast# to terminate a dma transfer. value of 1 indicates eot0# asserted or dreq0# de-asserted during demand mode dma immediately terminates a dma transfer (with or without blast#). p, l p, l 0 14 dma eot enable. value of 0 disables eot0# input pin. value of 1 enables the eot0# input pin. p, l p, l 0 13 write and invalidate mode for dma transfers. value of 1 indicates the iop 480 performs write and invalidate cycles to the pci bus. the iop 480 supports write and invalidate sizes of 8 or 16 words. size is specified in the pci cache line size register. if a size other than 8 or 16 is specified, the iop 480 performs write transfers rather than write and invalidate transfers. transfers must start and end at the cache-line boundaries. p, l p, l 0 12 demand mode. value of 1 causes the dma controller to operate in demand mode. in demand mode, the dma controller transfers data when its dreq0# input is asserted. it asserts dack0# to indicate the current local bus transfer is in response to the dreq0# input. dma controller transfers words (32 bits) of data. may result in multiple transfers for an 8- or 16-bit bus. p, l p, l 0 section 17 register summary dma registers iop 480 data book r2.0 17-64 ? 2000 plx technology, inc. all rights reserved. 11 local addressing mode. value of 0 indicates the local address is incremented. value of 1 indicates the local address ma[17:0] must be held constant. p, l p, l 0 10 done interrupt enable. value of 1 enables the dma done interrupt. when dma clear count mode (c0mode[16]=1)is enabled, the interrupt does not occur until byte count is cleared. p, l p, l 0 9 scatter/gather. value of 0 indicates block mode is enabled. value of 1 indicates scatter/gather mode is enabled. for scatter/gather mode, the dma source address, destination address, and byte count are loaded from memory into pci or local address spaces. p, l p, l 0 8:0 reserved. p, l n o 0 h register 17-125. (c0csr; pci:204h, loc:204h) channel 0 control/status bit description read write value after reset 31:5 reserved. p, l n o 0 h 4 dma done. value of 0 indicates the channel transfer is not complete. value of 1 indicates the channel transfer is complete, which occurs at the end of a single dma transfer if scatter/gather is disabled (c0mode[9]=0), or at the completion of a group of scatter/gather dma transfers if scatter/gather is enabled (c0mode[9]=1). p, l n o 1 3 clear interrupts. writing a value of 1 to this bit clears channel 0 interrupts. no p, l/clr 0 2 abort. writing a value of 1 to this bit causes the channel to abort the current transfer. the channel enable bit must be cleared (c0csr[0]=0). the dma done bit is set when the abort is complete (c0csr[4]=1). no p, l/set 0 1 start. writing a value of 1 to this bit causes the channel to start transferring data if the channel is enabled (c0csr[0]=1). no p, l/set 0 0 enable. value of 0 disables the channel from starting a dma transfer and if in the process of transferring data, to suspend the transfer (pause). value of 1 enables the channel to transfer data. p, l p, l 0 register 17-126. (c0count; pci:208h, loc:208h) channel 0 transfer count bit description read write value after reset 31 valid. when the valid mode bit is enabled (c0mode[18]=1), indicates the validity of this dma descriptor. p, l p, l 0 30:23 reserved. p, l n o 0 h 22:0 dma transfer size (bytes). indicates the number of bytes to transfer during a dma operation. however, if dma clear count mode is enabled and the dma channel had not been stopped by eot, the writeback cycle clears this register ? s bits to zero. however, if dma clear count mode is enabled and the dma channel had been stopped by eot, the writeback cycle writes back the number of bytes remaining to transfer. p, l p, l 0 h register 17-124. (c0mode; pci:200h, loc:200h) channel 0 mode (continued) bit description read write value after reset section 17 dma registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-65 section 17 ? registers register 17-127. (c0pciladr; pci:20ch, loc:20ch) channel 0 pci lower address bit description read write value after reset 31:0 pci address register. indicates pci memory space location in which the dma transfers (reads or writes) start. p, l p, l 0 h register 17-128. (c0locadr; pci:210h, loc:210h) channel 0 local address bit description read write value after reset 31:0 local address register. indicates the local memory space location in which the dma transfers (reads or writes) start. p, l p, l 0 h register 17-129. (c0descptr; pci:214h, loc:214h) channel 0 descriptor pointer bit description read write value after reset 31:4 next descriptor address. quad-word aligned (bits [3:0] = 0000). p, l p, l 0h 3 direction of transfer. value of 1 indicates transfers from the local bus to the pci bus. value of 0 indicates transfers from the pci bus to the local bus. p, l p, l 0 2 interrupt after terminal count. value of 1 generates an interrupt after reaching the terminal count for this descriptor. value of 0 disables interrupts from being generated. p, l p, l 0 1 end of chain. value of 1 indicates end of chain. value of 0 indicates not end of chain descriptor. (same as block mode.) p, l p, l 0 0 descriptor location. value of 1 indicates pci address space. value of 0 indicates local address space. p, l p, l 0 section 17 register summary dma registers iop 480 data book r2.0 17-66 ? 2000 plx technology, inc. all rights reserved. register 17-130. (c0pcihadr; pci:218h, loc:218h) channel 0 dual address cycle upper address bit description read write value after reset 31:0 dual address cycle upper address. upper 32-bits of the dual address cycle pci address during dma channel 0 cycles. used for 64-bit pci addressing on devices that don ? t support the 64-bit addressing bus (single address cycle), but support 64-bit addressing with an additional address phase (dual address cycle). dma channel 0 dual address cycles are enabled when this register is non-zero. p, l p, l 0h register 17-131. (c0thres; pci:21ch, loc:21ch) channel 0 threshold bit description read write value after reset 31:16 reserved. p, l n o 0 h 15:12 pci-to-local almost empty (c0plae). number of empty entries (minus 1) in the fifo before requesting the pci bus for reads. p, l p, l 0 h 11:8 local-to-pci almost full (c0lpaf). number of pairs of full entries (minus 1) in the fifo before requesting the pci bus for writes. p, l p, l 0 h 7:4 local-to-pci almost empty (c0lpae). number of empty entries (minus 1) in the fifo before requesting the local bus for reads. (c0lpaf+1) + (c0lpae+1) should be fifo depth of 32. p, l p, l 0 h 3:0 pci-to-local almost full (c0plaf). number of pairs of full entries (minus 1) in the fifo before requesting the local bus for writes. (c0plaf+1) + (c0plae+1) should be fifo depth of 32. p, l p, l 0 h section 17 dma registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-67 section 17 ? registers register 17-132. (c1mode; pci:220h, loc:220h) channel 1 mode bit description read write value after reset 31:21 reserved. p, l n o 0 h 20 eot1# end link. used only for dma scatter/gather transfers. when eot1# is asserted, value of 1 indicates the dma transfer ends the current scatter/ gather link and continues with the remaining scatter/gather transfers. when eot1# is asserted, value of 0 indicates the dma transfer ends the current scatter/gather transfer and does not continue with the remaining scatter/ gather transfers. p, l p, l 0 19 valid stop control. value of 0 indicates the dma chaining controller continuously polls a descriptor with the valid bit set to 0 (invalid descriptor) if the valid mode enable bit (c1mode[18]=1) is set. value of 1 indicates the chaining controller stops polling when the valid bit with a value of 0 is detected (c1count[31]). in this case, the cpu must restart the dma controller by setting the start bit (c1csr[1]=1). a pause sets the dma done register. p, l p, l 0 18 valid mode enable. value of 0 indicates the valid bit (c1count[31]) is ignored. value of 1 indicates that dma descriptors are processed only when the valid bit is set (c1count[31]). if the valid bit is set, the transfer count is 0, and the descriptor is not the last descriptor in the chain. the dma controller then moves to the next descriptor in the chain. p, l p, l 0 17 pci dual address scatter/gather. value of 0 indicates that normal address cycles are used during descriptor scatter/gather operations. value of 1 indicates that pci dual address cycles are used during descriptor scatter/gather operations (load c1pcihadr[31:0]). p, l p, l 0 16 dma clear count mode. value of 1 indicates that byte count in each scatter/gather descriptor is cleared when the corresponding dma transfer is complete. if this bit is enabled and scatter/gather dma had been stopped by eot, the writeback cycle writes back to the current descriptor the number of bytes remaining to be transferred. p, l p, l 0 15 dma fast/slow terminate mode select. value of 0 asserts blast# to terminate a dma transfer. value of 1 indicates eot1# asserted or dreq1# de-asserted during demand mode dma immediately terminates a dma transfer (with or without blast#). p, l p, l 0 14 dma eot enable. value of 0 disables eot1# input pin. value of 1 enables eot1# input pin. p, l p, l 0 13 write and invalidate mode for dma transfers. value of 1 indicates the iop 480 performs write and invalidate cycles to the pci bus. the iop 480 supports write and invalidate sizes of 8 or 16 words. size is specified in the pci cache line size register. if a size other than 8 or 16 is specified, the iop 480 performs write transfers rather than write and invalidate transfers. transfers must start and end at the cache-line boundaries. p, l p, l 0 12 demand mode. value of 1 causes dma controller to operate in demand mode. in demand mode, the dma controller transfers data when its dreq1# input is asserted. it asserts dack1# to indicate the current local bus transfer is in response to the dreq1# input. dma controller transfers words (32 bits) of data. may result in multiple transfers for an 8- or 16-bit bus. p, l p, l 0 section 17 register summary dma registers iop 480 data book r2.0 17-68 ? 2000 plx technology, inc. all rights reserved. 11 local addressing mode. value of 0 indicates local address is incremented. value of 1 indicates local address ma[17:0] must be held constant. p, l p, l 0 10 done interrupt enable. value of 1 enables dma done interrupt. when dma clear count mode (c1mode[16]=1) is enabled, the interrupt does not occur until byte count is cleared. p, l p, l 0 9 scatter/gather. value of 0 indicates block mode is enabled. value of 1 indicates scatter/gather mode is enabled. for scatter/gather mode, the dma source address, destination address and byte count are loaded from memory in pci or local address spaces. p, l p, l 0 8:0 reserved. p, l n o 0 h register 17-133. (c1csr; pci:224h, loc:224h) channel 1 control/status bit description read write value after reset 31:5 reserved. p, l n o 0 h 4 dma done. value of 1 indicates the channel transfer is complete, which occurs at the end of a single dma transfer if scatter/gather is disabled (c1mode[9]=1), or at the completion of a group of scatter/gather dma transfers if scatter/gather is enabled. value of 0 indicates channel transfer is not complete (c1mode[9]=0). p, l n o 1 3 clear interrupts. writing a 1 to this bit clears channel 1 interrupts. no p, l/clr 0 2 abort. writing a 1 to this bit causes the channel to abort the current transfer. the channel enable bit must be cleared (c1csr[0]=0). the dma done bit is set when the abort is complete (c1csr[4]=1). no p, l/set 0 1 start. value of 1 to this bit causes the channel to start transferring data if the channel is enabled (c1csr[0]=1). no p, l/set 0 0 enable. value of 0 disables the channel from starting a dma transfer and if in the process of transferring data, to suspend the transfer (pause). value of 1 enables the channel to transfer data. p, l p, l 0 register 17-134. (c1count; pci:228h, loc:228h) channel 1 transfer count bit description read write value after reset 31 valid. when the valid mode is enabled (c1mode[18]=1), indicates the validity of this dma descriptor. p, l p, l 0 30:23 reserved. p, l n o 0 h 22:0 dma transfer size (bytes). indicates number of bytes to transfer during a dma operation. however, if dma clear count mode is enabled and the dma channel had not been stopped by eot, the writeback cycle clears this register ? s bits to zero. however, if dma clear count mode is enabled and the dma channel had been stopped by eot, the writeback cycle writes back the number of bytes remaining to transfer. p, l p, l 0h register 17-132. (c1mode; pci:220h, loc:220h) channel 1 mode (continued) bit description read write value after reset section 17 dma registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-69 section 17 ? registers register 17-135. (c1pciladr; pci:22ch, loc:22ch) channel 1 pci lower address bit description read write value after reset 31:0 pci address register. indicates the pci memory space location in which the dma transfers (reads or writes) start. p, l p, l 0h register 17-136. (c1locadr; pci:230h, loc:230h) channel 1 local address bit description read write value after reset 31:0 local address register. indicates the local memory space location in which the dma transfers (reads or writes) start. p, l p, l 0h register 17-137. (c1descptr; pci:234h, loc:234h) channel 1 descriptor pointer bit description read write value after reset 31:4 next descriptor address. quad-word aligned (bits [3:0] = 0000). p, l p, l 0h 3 direction of transfer. value of 1 indicates transfers from the local bus to the pci bus. value of 0 indicates transfers from the pci bus to the local bus. p, l p, l 0 2 interrupt after terminal count. value of 1 generates an interrupt after reaching the terminal count for this descriptor. value of 0 disables interrupts from being generated. p, l p, l 0 1 end of chain. value of 1 indicates end of chain. value of 0 indicates not end of chain descriptor. (same as block mode.) p, l p, l 0 0 descriptor location. value of 1 indicates pci address space. value of 0 indicates local address space. p, l p, l 0 register 17-138. (c1pcihadr; pci:238h, loc:238h) channel 1 dual address cycle upper address bit description read write value after reset 31:0 dual address cycle upper address. upper 32-bits of the dual address cycle pci address during dma channel 1 cycles. used for 64-bit pci addressing on devices that don ? t support the 64-bit addressing bus (single address cycle), but support 64-bit addressing with an additional address phase (dual address cycle). dma channel 1 dual address cycles are enabled when this register is non-zero. p, l p, l 0h section 17 register summary dma registers iop 480 data book r2.0 17-70 ? 2000 plx technology, inc. all rights reserved. register 17-139. (c1thres; pci:23ch, loc:23ch) channel 1 threshold bit description read write value after reset 31:16 reserved. p, l n o 0 h 15:12 pci-to-local almost empty (c1plae). number of empty entries (minus 1) in the fifo before requesting the pci bus for reads. p, l p, l 0h 11:8 local-to-pci almost full (c1lpaf). number of pairs of full entries (minus 1) in the fifo before requesting the pci bus for writes. p, l p, l 0h 7:4 local-to-pci almost empty (c1lpae). number of empty entries (minus 1) in the fifo before requesting local bus for reads. (c1lpaf+1) + (c1lpae+1) should be fifo depth of 16. p, l p, l 0h 3:0 pci-to-local almost full (c1plaf). number of pairs of full entries (minus 1) in the fifo before requesting local bus for writes. (c1plaf+1) + (c1plae+1) should be fifo depth of 16. p, l p, l 0h section 17 dma registers register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 17-71 section 17 ? registers register 17-140. (c2mode; pci:240h, loc:240h) channel 2 mode bit description read write value after reset 31:16 reserved. p, l n o 0 h 15 dma fast/slow terminate mode select. value of 0 indicates when eot# is asserted or dreq2# is de-asserted, the dma controller completes the current word ? s transfer and completes the next word ? s transfer with blast# asserted. when set to 1, the dma controller stops transferring data after the current word is transferred, although blast# output is not asserted. p, l p, l 0 14 dma eot enable. value of 0 disables the eot2# input pin. value of 1 enables the eot2# input pin. p, l p, l 0 13 done interrupt enable. value of 1 enables the dma done interrupt. p, l p, l 0 12 source demand mode. value of 1 causes the dma controller to operate in demand mode while reading source data. in demand mode, the dma controller transfers data when its dreq2# input is asserted. it asserts dack2# to indicate the current local bus transfer is in response to the dreq2# input. the dma controller transfers words (32 bits) of data. may result in multiple transfers for an 8- or 16-bit bus. for flyby mode, this bit is ignored. p, l p, l 0 11 destination demand mode. value of 1 causes the dma controller to operate in demand mode while writing destination data. in demand mode, the dma controller transfers data when its dreq2# input is asserted. it asserts dack2# to indicate the current local bus transfer is in response to the dreq2# input. the dma controller transfers words (32 bits) of data. this may result in multiple transfers for an 8- or 16-bit bus. for flyby mode, this bit is used for reads or writes. p, l p, l 0 10 flyby mode. value of 0 indicates normal dma addressing, with the local source address used for reads and the destination address used for writes. value of 1 indicates that a flyby dma is performed, where the destination information is used for reads or writes. p, l p, l 0 9 flyby direction. when flyby mode is enabled (c2mode[10]=1), a value of 0 indicates the destination address is written (c2mode[10]=1). value of 1 indicates the destination address is read. note: destination address is used for both modes. p, l p, l 0 8 reserved. p, l n o 0 7 local destination addressing mode. value of 0 indicates the local destination address is incremented. value of 1 indicates the local address ma[17:0] must be held constant. used during all flyby mode dma operations. p, l p, l 0 6 local source addressing mode. value of 0 indicates local source address is incremented. value of 1 indicates local address ma[17:0] must be held constant. this bit is ignored during all flyby mode dma operations. p, l p, l 0 5:0 reserved. p, l n o 0 h section 17 register summary dma registers iop 480 data book r2.0 17-72 ? 2000 plx technology, inc. all rights reserved. register 17-141. (c2csr; pci:244h, loc:244h) channel 2 control/status bit description read write value after reset 31:5 reserved. p, l n o 0 h 4 dma done. a value of 1 indicates the channel transfer is complete, which occurs at the end of a single dma transfer. a value of 0 indicates channel transfer is not complete. p, l n o 1 3 clear interrupts. writing a 1 to this bit clears channel 2 interrupts. no p, l/clr 0 2 abort. value of 1 to this bit causes the channel to abort the current transfer. the channel enable bit must be cleared (c2csr[0]=0). the dma done bit is set when the abort is complete (c2csr[4]=1). no p, l/set 0 1 start. value of 1 causes the channel to start transferring data if the channel is enabled (c2csr[0]=1). no p, l/set 0 0 enable. value of 1 enables the channel to transfer data. value of 0 disables the channel from starting a dma transfer and if in the process of transferring data suspend the transfer (pause). p, l p, l 0 register 17-142. (c2count; pci:248h, loc:248h) channel 2 transfer count bit description read write value after reset 31:0 dma transfers size (bytes). indicates number of bytes to transfer during a dma operation. p, l p, l 0 h register 17-143. (c2srcadr; pci:24ch, loc:24ch) channel 2 source address bit description read write value after reset 31:0 source address register. indicates the local memory space location in which the dma transfers (reads or writes) start. p, l p, l 0 h register 17-144. (c2destadr; pci:250h, loc:250h) channel 2 destination address bit description read write value after reset 31:0 destination address register. indicates the local memory space location in which the dma transfers (reads or writes) start. p, l p, l 0h iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 18-1 section 18 ? pin description 18 iop 480 pin description 18.1 pin descriptions table 18-2 lists the abbreviations used in the tables that follow. table 18-3 describes the i/o buffer types. note: pu or pd indicates that the pin buffer has either an internal pull-up or pull-down resistor. this guarantees only that the internal chip pin signal is being pulled up or pulled down. it does not guarantee that the pin signal external to the chip will be pulled up or down. therefore, external pull-up or pull-down resistors are recommended, even when internal pull-up or pull-down resistors are provided. for a visual view of the chip pinout, refer to section 20, ? package. ? table 18-1. i/o pin summary functional block number of external i/o comments pqfp pbga pci bus controller with i 2 o interface 50 50 plx pci 9054 core pci arbiter 6 6 up to three external pci masters serial eeprom interface 3 3 for controller configuration hot swap 2 2 compactpci hot swap support 16450 compatible serial port (uart) 2 2 serial port memory controller 25 25 supports edo dram/sdram devices iop 480 cpu clock and test/debug 11 11 iop 480 cpu reset, clock, test, and debug power, ground, and unused 43 59 power and ground pins (pbga package includes one extra common ground, six additional ground pins, and nine unused pins) local bus interface (iop 480 cpu type) 59 60 local bus 32-bit multiplexed interface (pbga package includes one extra pad for llock# signal) local bus arbiter 4 4 up to two external local bus masters local bus interrupts 3 3 general-purpose local bus interrupts to ta l 208 225 table 18-2. pin type abbreviations abbreviation pin type i/o input and output pin i input-only pin o output-only pin ts three-state pin od open drain pin tp totem pole pin sts sustained three-state pin, driven high for one clk before float pu pull-up resistor on pin pd pull-down resistor on pin table 18-3. i/o buffer types buffer buffer type bt520 bt535 bt550 bt565 local bus buffers bpci5 bpci5t bpci5pu bpci5put pci bus buffers section 18 iop 480 pin description pin descriptions iop 480 data book r2.0 18-2 ? 2000 plx technology, inc. all rights reserved. table 18-4. pin configuration control pins pin name pin configuration configuration register and bit default after reset enum# pci hot swap ? selectable as input or output hmode pin ? inta# pci interrupt a ? output enable (always input) pciipr[7:0] disabled pme# pci power management event ? output enable (always input) pmcsr[8] disabled rst# pci reset ? input or output hmode pin ? gnt0#/req# pci grant 0 ? input or output (determined by pcictl[16]) input pci arbiter enable pcictl[16] disabled req0#/gnt# pci request 0 ? input or output (determined by pcictl[16]) output pci arbiter enable pcictl[16] disabled gnt2#/ts1 pci grant 2 or risctrace 1 output devinit[4] gnt2 req2#/ts2 pci request 2 or risctrace 2 output devinit[4] req2# eedata/ts3 serial eeprom data or risctrace 3 output devinit[4] eedata eesk/ts4 serial eeprom serial clock or risctrace 4 output devinit[4] eesk dp[3:0]/ma[16:13] data parity or memory addresses [16:13] lcsnbrd[12] disabled eot0#/user3 dma end of transfer or user 3 input c0mode[14] user3 user3 data (input) locctl[16] ? eot1#/user4 dma end of transfer or user 4 input c1mode[14] user4 user4 data (input) locctl[17] ? lcs0#/dmpaf# local bus chip select or direct master programmable almost full signal locctl[0] lcs0# lcs0# enable lcs0base[0] enabled lcs1#/user0 local bus chip select output or user0 signal locctl[1] user0 lcs1# enable lcs1base[0] disabled user0 direction locctl[2] input (pull-up) user0 data locctl[3] 0 lcs2#/user1 local bus chip select output or user1 signal locctl[4] user1 lcs2# enable lcs2base[0] disabled user1 direction locctl[5] input (pull-up) user1 data locctl[6] 0 lcs3#/ma17 local bus chip select or memory address 17 locctl[7] lcs3# lcs3# enable lcs3base[0] disabled lholdack0 local bus hold acknowledge 0 ? input or output (determined by larbr[0]) input local arbiter enable larbr[0] enabled lholdreq0 local bus hold request 0 ? input or output (determined by larbr[0]) output local arbiter enable larbr[0] enabled section 18 pin descriptions iop 480 pin description iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 18-3 section 18 ? pin description note: the ? default value after reset ? is valid only if no programmed serial eeprom is present or until the serial eeprom has loaded new values to the configuration registers. cint/user2 critical interrupt input or user2 signal locctl[8] user2 user2 direction locctl[9] input (pull-up) user2 data locctl[10] 0 cint polarity lintenb[19] active low inti inti interrupt status lintstat[7] 0 inti polarity lintenb[18] active low into into polarity lintenb[17] active low mcas#/moe# column address strobe or memory output enable (determined by dram type and dram enable) moe# dram type dramctl[0] edo dram enable drambase[0] disabled ras[3:0]#/mcs[3:0]# row address strobe or memory chip selects (determined by dram type and dram enable) mcsn# dram type dramctl[0] edo dram enable drambase[0] disabled cas[3:0]#/mdqm[3:0]# column address strobe or data mask outputs (determined by dram type and dram enable) mdqmn# dram type dramctl[0] edo dram enable drambase[0] disabled tx/ts5 serial transmit or risctrace 5 output devinit[4] tx table 18-4. pin configuration control pins (continued) pin name pin configuration configuration register and bit default after reset section 18 iop 480 pin description pin descriptions iop 480 data book r2.0 18-4 ? 2000 plx technology, inc. all rights reserved. table 18-5. pci bus controller with i 2 o interface pins symbol signal name to ta l pin type pqfp pin # pbga pin # function ad[31:0] address and data 32 i/o ts bpci5_b and bpci5t_b 7-11, 13-15, 19-22, 24-25, 27-28, 43-45, 47-51, 55-59, 61-63 c1, d2, g6, e4, d1, e3, e2, f5, f2, f1, g4, g3, g1, h3, h4, h5, k5, m2, l4, m3, n2, k6, p1, n3, r2, p3, l5, n4, r3, k7, m5, r4 address and data signals multiplexed on the same pci pins. a bus transaction consists of an address phase followed by one or more data phases. the iop 480 supports both read and write bursts. c/be[3:0]# bus command and byte enables 4 i/o ts bpci5_b 16, 29, 42, 54 e1, j2, m1, m4 all multiplexed on the same pci pins during the address phase. these signals define the bus command. during the data phase they are used as byte enables. refer to pci specification r2.2 for further details. clk clock 1 i bpci5_a 3b1 provides timing for all transactions on the pci bus and is an input to every pci device. devsel# device select 1 i/o sts bpci5_b 34 j5 when actively driven, indicates the driving device has decoded its address of the current access target. as an input, indicates whether any bus device is selected. frame# cycle frame 1 i/o sts bpci5_b 31 j1 driven by the current master to indicate the beginning and duration of an access. when asserted, data transfers continue. when de-asserted, the transaction is in the final data phase. idsel initialization device select 1 i bpci5t_a 17 f4 used as a chip select during configuration read and write transactions. inta# interrupt 1 i/o od bpci5_a 65 n5 used by the iop 480 to request an interrupt, or as interrupt input to the iop 480. in adapter mode, inta# is an output only. in host mode, inta# is an input only. irdy# initiator ready 1 i/o sts bpci5_b 32 j3 indicates the initiating agent ? s ability (bus master) to complete the current transaction data phase. lock# lock 1 i/o sts bpci5t_b 37 k3 asserted by the master to indicate an atomic operation that may require multiple transactions to the target agent to complete. section 18 pin descriptions iop 480 pin description iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 18-5 section 18 ? pin description pa r pa r i t y 1 i/o ts bpci5_b 40 k4 even parity across ad and c/be signals. parity generation is required by all pci agents. par is stable and valid one clock after the address phase. for data phases, par is stable and valid one clock after either irdy# is asserted on a write transaction or trdy# is asserted on a read transaction. once par is valid, it remains valid until one clock after the current data phase completion. perr# parity error 1 i/o sts bpci5_b 38 j6 reports data parity errors during all pci transactions, except during a special cycle. pme# power management event 1 i/o od bpci5t_a 203 b3 wake up event pin. can be an output to signal a power management event, or as an input to receive power management events. rst# reset 1 i/o od, pu bpci5pu_a 2d4 used to bring pci-specific registers, sequencers, and signals to a consistent state. based on the hmode pin. can be a reset input or a reset output. serr# systems error 1 i/o od bpci5t_b 39 l2 reports address parity errors, data parity errors on the special cycle command, or any other system error where the result will be catastrophic. stop# stop 1 i/o sts bpci5t_b 35 k1 indicates the current target is requesting the master to stop the current transaction. trdy# target ready 1 i/o sts bpci5t_b 33 j4 indicates the target agent ability (selected device) to complete the current transaction data phase. to ta l 50 table 18-5. pci bus controller with i 2 o interface pins (continued) symbol signal name to ta l pin type pqfp pin # pbga pin # function section 18 iop 480 pin description pin descriptions iop 480 data book r2.0 18-6 ? 2000 plx technology, inc. all rights reserved. table 18-6. pci arbiter pins symbol signal name to ta l pin type pqfp pin # pbga pin # function gnt0#/req# grant 0/request 1 o ts bpci5_a 5e5 when the iop 480 is a pci arbiter (refer to the pcictl register), indicates to the master that bus access is granted. every master has its own gnt# and req# signals. indicates to the pci arbiter that bus use is required when the iop 480 is not a pci arbiter. gnt1# grant 1 1 o ts bpci5t_a 206 c3 when the iop 480 is a pci arbiter (refer to the pcictl register), indicates to the master that bus access is granted. every master has its own gnt# and req# signals. not used when the iop 480 is not a pci arbiter. gnt2#/ts1 grant 2/ risctrace 1 output 1 o ts bpci5_b 204 f6 when the iop 480 is a pci arbiter (refer to the pcictl register), indicates to the master that bus access is granted. every master has its own gnt# and req# signals. when enabled for risctrace (devinit[4]=1), ts1 is one of six output pins used in ibm risctrace mode. (when used for risctrace, only two pci bus masters are allowed.) not used when the iop 480 is not a pci arbiter and risctrace is not enabled. req0#/gnt# request 0/grant 1 i pu bpci5put_a 4c2 when the iop 480 is a pci arbiter (refer to the pcictl register), indicates a master requires bus use. every master has its own gnt# and req# signals. when the iop 480 is not a pci arbiter, indicates that bus access is granted. req1# request 1 1 i pu bpci5pu_a 207 b2 when the iop 480 is a pci arbiter (refer to the pcictl register), indicates a master requires bus use. every master has its own gnt# and req# signals. not used when the iop 480 is not a pci arbiter. req2#/ts2 request 2/ risctrace 2 output 1 i/o pu bpci5pu_a 205 a2 when the iop 480 is a pci arbiter (refer to the pcictl register), indicates that a master requires bus use. every master has its own gnt# and req# signals. when enabled for risctrace (devinit[4]=1), ts2 is one of six output pins used in ibm risctrace mode. (when used for risctrace, only two pci bus masters are allowed.) not used when the iop 480 is not a pci arbiter and risctrace is not enabled. to ta l 6 section 18 pin descriptions iop 480 pin description iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 18-7 section 18 ? pin description table 18-7. serial eeprom interface pins symbol signal name to ta l pin type pqfp pin # pbga pin # function eecs chip select 1 o tp 5 ma bt565_g_a 194 f7 chip select to serial eeprom. eedata/ts3 serial eeprom data/ risctrace 3 output 1 i/o tp, pu 5 ma bt565put_g_a 195 b5 read/write data from or to the serial eeprom. when enabled for risctrace (devinit[4]=1), ts3 is one of six output pins used in ibm risctrace mode. eesk/ts4 serial data clock/ risctrace 4 output 1 o tp 5 ma bt565_g_a 196 d6 serial eeprom clock. when enabled for risctrace (devinit[4]=1), ts4 is one of six output pins used in ibm risctrace mode. to ta l 3 table 18-8. hot swap pins symbol signal name to ta l pin type pqfp pin # pbga pin # function enum# hot swap 1 i/o od bpci5_a 202 c4 asserted when an adapter has been inserted, or ready to be removed from, a pci slot. can be an output to signal a hot swap event, or as an input to manage hot swapping of other adapter cards (mode is determined by the hmode pin). ledon/ledin led control pin 1 i/o ts 24 ma bt520_g_a 198 a7 as an input, monitors the compact pci board latch status. as an output, acts as the hot swap board indicator led. to ta l 2 table 18-9. 16450 compatible serial port pins symbol signal name to ta l pin type pqfp pin # pbga pin # function rx serial receive 1 i pu bt565put_g_a 199 e6 uart receive signal (ttl levels). tx/ts5 serial transmit/ risctrace 5 output 1 o tp 5 ma bt565_g_a 200 b4 uart transmit signal (ttl levels). when enabled for risctrace (devinit[4]=1), is one of six output pins used in ibm risctrace mode. to ta l 2 section 18 iop 480 pin description pin descriptions iop 480 data book r2.0 18-8 ? 2000 plx technology, inc. all rights reserved. table 18-10. memory controller pins symbol signal name to ta l pin type pqfp pin # pbga pin # function ma[12:0] memory address 13 o tp 7 ma bt535_g_b and bt535t_g_b 178-175, 173-169, 167-164 c9, d9, a10, b10, d10, a11, e10, b11, c11, a12, d11, f9, b12 edo dram: 13-bit multiplexed address allows access to 64 mb of edo dram per bank. 8 16 megabits x 4 devices = 64 mb 4 8 megabits x 8 devices = 32 mb 2 4 megabits x 16 devices = 16 mb 8 4 megabits x 4 devices = 16 mb 4 2 megabits x 8 devices = 8 mb 2 1 megabits x 16 devices = 4 mb sdram: 12-bit multiplexed address (ma[11:0]) allows access up to 16 mb of sdram per bank. 8 4 megabits x 4 devices = 16 mb 4 2 megabits x 8 devices = 8 mb 2 1 megabits x 16 devices = 4 mb 14-bit megabits multiplexed address (ma[13:0]) allows access up to 64 mb of sdram per bank. 8 16 megabits x 4 devices = 64 mb 4 8 megabits x 8 devices = 32 mb 2 4mx16 devices = 16 mb the address also provides the data for the mode register during initialization. if enabled by bits in the iop 480 configuration register, lcs3# becomes ma17, and dp[3:0] becomes ma[16:13] to expand the multiplexed memory bus. these signals can also be used with local chip selects (lcs[3:0]#) for accessing sram/eprom and peripherals. mcas#/ moe# column address strobe/ output enable 1 o tp 7 ma bt535_g_b 185 b7 edo dram: output enable used to enable the output buffers during a read cycle. sdram: column address strobe to memory devices. used with local chip selects (lcs[3:0]#) for accessing sram/eprom and peripherals. mcke clock enable 1 o tp 9 ma bt535_g_c 179 b9 edo dram: not used. sdram: clock enable to memory devices (lclko is used to clock memory transactions). may be used to place sdram devices in a reduce memory power consumption mode. section 18 pin descriptions iop 480 pin description iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 18-9 section 18 ? pin description ras[3:0]#/ mcs[3:0]# row address strobe/ memory chip selects 4 o tp 7 ma bt550t_g_b and bt550_g_b 184-183, 181-180 e8, d8, c8, a9 edo dram: row address strobe used to strobe the row address. also part of the cas-before-ras refresh sequence. each ras enables one of up to four banks of edo dram. sdram: chip select asserted to initiate read, write, and refresh cycles. each chip select enables one of up to four banks of sdram. cas[3:0]#/ mdqm[3:0]# column address strobe/ data mask outputs 4 o tp 7 ma bt550t_g_b and bt550_g_b 193-191, 189 c6, b6, a6, d7 edo dram: column address strobe. used to strobes the column address into the edo sdram. each casn# signal corresponds to one byte in the 32-bit-wide memory. sdram: data mask outputs to external memory devices. byte input enables during write cycles and output enables during read cycles. the mdqmn# signals can also be used with local chip selects (lcs[3:0]#) as byte write enables when accessing sram/eprom and peripherals. mras# row address strobe 1 o tp 7 ma bt535_g_b 187 a7 edo dram: not used. sdram: row address strobe to memory devices. mwe# write enable 1 o tp 9 ma bt535_g_c 188 c7 asserted for edo dram, sram and sdram during write cycles. to ta l 25 table 18-10. memory controller pins (continued) symbol signal name to ta l pin type pqfp pin # pbga pin # function section 18 iop 480 pin description pin descriptions iop 480 data book r2.0 18-10 ? 2000 plx technology, inc. all rights reserved. table 18-11. iop 480 cpu clock and test/debug pins symbol signal name total pin type pqfp pin # pbga pin # function halt# halt 1 i pu it5d1put_g_a 143 e14 halt from external debugger, active low. hmode host mode 1 i pu bt565pu_g_a 201 a3 used to select the iop 480 host mode. when high, the iop 480 drives the pci rst# and enum# signals. when low, the iop 480 is in the adapter mode and the pci rst# and enum# are inputs. lclk local clock input 1 i it5t_g_a 141 f13 processor clock input (33 mhz or 66 mhz) used to drive the iop 480 cpu and the local bus. note: may be used for the pll reference clock (refclk) in future designs. it must be located on a ? t ? (test) pin and near the vdda pin. mtp manufacturing test pin 1 i pd it5tepdt_g_a 151 c14 for manufacturing testing use (ibm). must remain open (no connect) or grounded, for normal operation. note: this is a special ibm test enable (te) receiver buffer. reset# reset input/ output 1 i/o od 7 ma bt535_g_b 117 l13 as an input, a logic 0 input placed on this pin for at least two lclk causes the iop 480 cpu to begin a system reset and asserts reset# to a logic 0 (output mode). as an output, reset# is asserted for the following conditions: processor reset# asserted; pci bus rst# asserted; or software reset bit in the devinit register set to 1. the reset# output pin becomes a logic 0 for 64 (minus 1 or 2) lclk cycles. notes: this pin is never an input in adapter mode. should only be driven by an ? open drain ? device. tck test clock input 1 i pu bt550pu_g_a 161 e11 tck is the clock source for the iop 480 cpu test access port (tap). the maximum clock rate into the tck pin is lclk rate or less than one-half of the lclk rate. tdi test data in 1 i it5rit_g_a (no internal pull-up) 132 h11 used to input serial data into the tap. when the tap enables this pin, it is sampled on the rising edge of tck and the data is input to the selected tap shift register. tdo test data output 1 o 5 ma bt550_g_a 153 b15 used to transmit data from the iop 480 cpu tap. data from the selected tap shift registers is shifted out on tdo. tms test mode select 1 i pu it5d2put_g_a 154 c13 sampled by tap on the rising edge of tck. the tap state machine uses the tms pin to determine the mode in which the tap operates. note: not used to select jtag operation. section 18 pin descriptions iop 480 pin description iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 18-11 section 18 ? pin description trst# test reset 1 i pu it5put_g_a 147 f11 the trst# signal is used by jtag testers (not required by ibm testers). ts6 risctrace 6 output 1 o tp 5 ma bt550_g_a 155 b14 when enabled for risctrace (devinit[4]=1), is one of six output pins used in ibm risctrace mode. to ta l 11 table 18-11. iop 480 cpu clock and test/debug pins (continued) symbol signal name total pin type pqfp pin # pbga pin # function table 18-12. power, ground and unused pins symbol signal name total pin type pqfp pin # pbga pin # function vdd power (3.3v) 22 vdd 1, 18, 26, 36, 41, 53, 70, 78, 88, 93, 105, 110, 118, 130, 139, 140, 145, 157, 162, 182, 190, 197 a1, a8, a15, c5, c12, e7, e13, f3, f14, f15, h1, h15, k2, l3, l14, m13, n6, n11, p10, r1, r8, r15 core and i/o power pins. vss common grounds 21/22 gnd 6, 12, 23, 30, 46, 52, 60, 64, 75, 82, 100, 104, 116, 125, 134, 150, 156, 168, 174, 186, 208 c10, d3, d13, f8, g2, g7-g9, h6-h10, j7-j9, j12, k8, k10, n1, p4, p7 ground pins. vss ground (pbga package only) 6gnd ? a5, d5, e9, l1, m11, r11 pbga ground pins. ? unused pbga pins 9 unused ? b8, e12, e15, g5, h2, j11, l7, p2, p8 available, but unused pbga pins. to ta l 43 (pqfp) 59 (pbga) section 18 iop 480 pin description pin descriptions iop 480 data book r2.0 18-12 ? 2000 plx technology, inc. all rights reserved. table 18-13. local bus interface (iop 480 cpu type) pins symbol signal name to ta l pin type pqfp pin # pbga pin # function ads# address strobe 1 i/o ts 7 ma bt535_g_b 123 k14 asserted by the master to indicate a valid address and the start of a new bus access. asserted for the first clock of a bus access. ale address latch enable 1 i/o ts, pd 7 ma bt550pd_g_b 149 c15 asserted by the master during the address phase and de-asserted before the data phase. used to latch the multiplexed address/data bus (lad) address portion. boff# backoff request out 1 o tp 7 ma bt550_g_b 131 h12 asserted to indicate that the iop 480 requires the bus to perform a direct pci-to-local bus access while a direct master access is pending on the local bus. used with external logic to generate backoff to a local bus master. its operational parameters are set up through the iop 480 configuration registers. blast# burst last 1 i/o ts 9 ma bt550t_g_c 124 k15 asserted by the master to indicate the last transfer in a bus access. bterm# bus terminate 1 i/o ts 7 ma bt550_g_b 113 j10 if bterm input is enabled through the configuration registers (dma channel x mode register), the iop 480 continues to burst until the bterm# input signal is asserted. if bterm input is disabled, the iop 480 bursts up to four lwords. bterm# is a ready input that breaks up a burst cycle and causes another address cycle to occur. it is used in conjunction with the pci iop 480 programmable wait state generator. when bterm# is an output, it is asserted, along with ready# output, to request the break up of a burst and the start of a new address cycle (abort only). dack0# dma acknowledge output channel 0 1 o tp 7 ma bt550_g_b 133 g14 when a channel is programmed through the configuration registers to operate in demand mode, its dack output indicates a dma transfer is being executed. dack1#/ dack2# dma acknowledge outputs channels 1 and 2 1 o tp 7 ma bt550_g_b 136 g13 when dma channel 1 or 2 is programmed through the configuration registers to operate in ? demand flyby ? mode, dack1/ dack2 output indicates a dma transfer is being executed. in flyby mode, dack indicates that the ready# output corresponds to memory data being valid. section 18 pin descriptions iop 480 pin description iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 18-13 section 18 ? pin description dp[3:0]/ ma[16:13] data parity/ memory address 4 i/o ts 7 ma bt535_g_b 148, 146, 144, 142 d14, d15, f12, g10 parity is programmable as even or odd for the four bytes lanes on the local bus. parity is checked by the master during read cycles and generated by the master for write cycles. also can be programmed to be memory address signals. upon power-up, dp mode is disabled and these ma signals are not driven (the signals must be held high by external pull-up resistors). only after the ma mode bit has been programmed (via the serial eeprom or processor), will these ma or dp signals be driven. dreq0# dma request input 1 i bt550_g_a 135 g15 when a channel is programmed through the configuration registers to operate in demand mode, the dreq0# input serves as a dma request. dreq1#/ dreq2# dma request inputs 1 i bt550t_g_a 137 g12 when dma channel 1 or 2 is programmed through the configuration registers to operate in demand flyby mode, dreq# input serves as a dma request for channel 1 or channel 2. eot0#/ user3 dma 0 end of transfer input/user input 1 i bt550_g_a 138 g11 when asserted, causes termination of corresponding dma channel transfer. used as a general purpose input signal controlled from the iop 480 locctl[16] register. eot1#/ eot2#/ user4 dma 1/2 end of transfer input/user input 1 i bt550_g_a 152 f10 when asserted, causes the termination of the corresponding dma channel transfer. used as a general purpose input signal controlled from the iop 480 c1mode register. lad[31:0] address and data bus 32 i/o 7 ma bt535_g_b and bt535t_g_b 106, 103-101, 99-94, 92-89, 87-83, 81-79, 77-76, 74-71, 69-66 m12, p14, n13, r14, p13, n12, r13, p12, l10, r12, m10, p11, k9, n10, r10, l9 m9, n9, r9, p9, l8, m8, n8, r7, n7, m7, r6, p6, m6, r5, l6, p5 multiplexed 32-bit address and data bus. note: lad31 corresponds to bit 31 (msb) and lad0 corresponds to bit 0 (lsb). table 18-13. local bus interface (iop 480 cpu type) pins (continued) symbol signal name to ta l pin type pqfp pin # pbga pin # function section 18 iop 480 pin description pin descriptions iop 480 data book r2.0 18-14 ? 2000 plx technology, inc. all rights reserved. lbe[3:0]# byte enables 4 i/o ts 7 ma bt535_g_b and bt535t_g_b 108, 109, 111, 112 n14, l11, n15, m14 encoded byte enables. encoding determined by the configured bus width (32-, 16-, or 8-bit). 32-bit bus the four byte enables indicate which of the four bytes are active during a data cycle: lbe3# byte enable 3 ? lad[31:24] lbe2# byte enable 2 ? lad[23:16] lbe1# byte enable 1 ? lad[15:8] lbe0# byte enable 0 ? lad[7:0] 16-bit bus lbe3#, lbe1#, and lbe0# are encoded to provide bhe#, a1, and ble#, respectively: lbe3# byte enable high (bhe#) ? lad[15:8] lbe2# not used lbe1# address bit 1 (a1) lbe0# byte enable low (ble#) ? lad[7:0] 8-bit bus lbe1# and lbe0# are encoded to provide a1 and a0, respectively: lbe3# not used lbe2# not used lbe1# address bit 1 (a1) lbe0# address bit 0 (a0) lcs0#/ dmpaf# local bus chip select/ direct master programmable almost full 1 o tp 7 ma bt550_g_b 158 d12 local bus chip select 0. asserted by the iop 480 when the lad bus address has decoded an address in the range programmed for the chip select. supports 8-, 16-, or 32-bit- wide sram, rom/eprom, or i/o devices. after reset, if no programmed serial eeprom is found, used to select the 8-bit boot rom device (in big endian mode). direct master write fifo almost full status output, pin selection programmable through locctl[0]. table 18-13. local bus interface (iop 480 cpu type) pins (continued) symbol signal name to ta l pin type pqfp pin # pbga pin # function section 18 pin descriptions iop 480 pin description iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 18-15 section 18 ? pin description lcs1#/ user0 local bus chip select/ user input/output 1 i/o ts 7 ma bt550_g_b 159 a14 local bus chip select 1. asserted by the iop 480 when the lad bus address has decoded an address in bit-wide range programmed for the chip select. supports 8-, 16-, or 32-bit-wide sram, eprom, or i/o devices. used as a general purpose input/output signal controlled from the iop 480 configuration registers. pin selection programmable through locctl[1]. lcs2#/ user1 local bus chip select/ user input/output 1 i/o ts 7 ma bt550t_g_b 160 b13 local bus chip select 2. asserted by the iop 480 when the lad bus address has decoded an address in the range programmed for the chip select. supports 8-, 16-, or 32-bit-wide sram, rom/eprom, or i/o devices. used as a general purpose input/output signal controlled from the iop 480 configuration registers. pin selection programmable through locctl[4]. lcs3#/ma17 local bus chip select 3/ memory address 17 1 o tp 7 ma bt535t_g_b 163 a13 local bus chip select 3. asserted by the iop 480 when the lad bus address has decoded an address in the range programmed for the chip select. supports 8-, 16-, or 32-bit-wide sram, rom/eprom, or i/o devices. if enabled by a bit in the configuration register, becomes multiplexed address bus signal ma17 (refer to the ma[12:0] signal description). pin selection programmable through locctl[3]. lwr# write/read# 1 i/o ts 7 ma bt550_g_b 107 p15 master asserts low for reads and high for writes. llock# bus lock 0/1 i/o ts 7 ma bt550_g_b_pu ? h14 available only in pbga package. indicates an atomic operation is required by the local bus master. an output when the direct slave pci bus requires multiple transactions to an external local bus device. an input when a local bus master retains bus control. table 18-13. local bus interface (iop 480 cpu type) pins (continued) symbol signal name to ta l pin type pqfp pin # pbga pin # function section 18 iop 480 pin description pin descriptions iop 480 data book r2.0 18-16 ? 2000 plx technology, inc. all rights reserved. ready# ready 1 i/o ts 7 ma bt550t_g_b 114 l12 asserted by the slave to indicate that the bus read data is valid or that the write data transfer is complete. wait states are inserted until ready# is asserted. if the ready# input is disabled for a local address space, then the number of wait states is determined by the internal wait state generator. rd# read strobe 1 o ts 7 ma bt550_g_b 120 l15 general purpose read strobe asserted by the iop 480. the timing is controlled by the bus region description registers. three-stated when the iop 480 is not the local bus master. can be used with devices such as external fifos. wait# wait 1 i/o ts 7 ma bt550_g_b 115 m15 during direct master accesses, wait# can be used to signal the iop 480 that the local bus master cannot accept/provide the data, and requires wait states inserted. when iop 480 is the local bus master, wait# is an output that provides the status of the internal wait state generators. to ta l 59 (pqfp) 60 (pbga) table 18-13. local bus interface (iop 480 cpu type) pins (continued) symbol signal name to ta l pin type pqfp pin # pbga pin # function section 18 pin descriptions iop 480 pin description iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 18-17 section 18 ? pin description table 18-14. local bus arbiter pins symbol signal name to ta l pin type pqfp pin # pbga pin # function lholdack0/ ldreq local bus hold acknowledge 0/ local bus hold request 1 o tp 7 ma bt550t_g_b 126 j13 when the iop 480 is a local bus arbiter (refer to the larbr register), indicates to the master that bus access is granted (acknowledged). every master has its own lholdack and lholdreq signals. asserted when the iop 480 requests local bus use when the iop 480 is not a local bus arbiter. lholdack1/ breq local bus hold acknowledge 1/ local bus request (preempt) 1 o tp 9 ma bt550t_g_c 128 j15 indicates to the master that access to the bus is granted (acknowledged). every master has its own lholdack and lholdreq signals. not used when the iop 480 is not a local bus arbiter (refer to the larbr register). note: breq output is asserted to request an external local master to release the local bus when there is a refresh cycle or the local latency timer is expired. lholdreq0/ lholdack local bus hold request 0/ local bus hold acknowledge 1 i pd bt550pd_g_a 127 j14 when the iop 480 is a local bus arbiter (refer to the larbr register), indicates that a master requires bus use. every master has its own lholdack and lholdreq signals. control has been granted to the iop 480 when it is not a local bus arbiter, nor is it asserted by the local bus arbiter. lholdreq1 local bus hold request 1 1 i pd bt550pd_g_a 129 h13 indicates that a master requires bus use. every master has its own lholdack and lholdreq signals. not used when the iop 480 is not a local bus arbiter (refer to the larbr register). to ta l 4 section 18 iop 480 pin description pin descriptions iop 480 data book r2.0 18-18 ? 2000 plx technology, inc. all rights reserved. note: edo/sdram uses lad[31:0] for the 32-bit data bus. table 18-15. local bus interrupt pins symbol signal name total pin type pqfp pin # pbga pin # function cint/ user2 critical interrupt 1 i/o ts 5 ma bt550t_g_a 119 k11 used as a general purpose input or output signal or iop 480 cpu critical interrupt source. the cint polarity is selectable by lintenb[19]. pin selection programmable through locctl[8]. inti interrupt input 1 i bt550t_g_a 121 k12 source for the iop 480 cpu interrupt. the polarity of inti is selectable by lintenb[18]. into interrupt output 1 o tp 5 ma bt550_g_a 122 k13 iop 480 interrupt output. the polarity of into is selectable by lintenb[17]. asserted each time the power state in the pmcsr register changes. to ta l 3 iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 19-1 section 19 ? electrical specs 19 electrical specifications 19.1 i/o timing specifications figure 19-1. iop 480 ale output delay from the local clock (min/max, in nanoseconds) notes: local output delays evaluated with 25 pf loading. pci output delays evaluated with 50 pf loading. timings may be derated at 0.8 ns per 10 pf. the maximum local bus frequency for the iop 480-aa60bi and iop 480-aa60pi is 60 mhz. n/a indicates ? not applicable. ? it is recommended that approximately 8 to 16 of either 0.1 f or 0.01 f decoupling capacitors be distributed evenly near the iop 480 power and ground pins. table 19-1. ac electrical characteristics (worst case process, t a =85 c, vcc=3.0v) synchronous signal output delay setup time hold time min max pci gnt# signals 3.0 ns 12.0 ns 10.0 ns 0.0 ns pci req# signals 3.0 ns 12.0 ns 12.0 ns 0.0 ns all other pci signals 3.0 ns 11.0 ns 7.0 ns 0.0 ns ladx 3.0 ns 10.0 ns 4.5 ns 1.0 ns lcsx#_userx 3.0 ns 10.0 ns 5.0 ns 1.0 ns ready# 3.0 ns 10.0 ns 5.5 ns 1.0 ns lwr# 3.0 ns 10.0 ns 10.0 ns 1.0 ns cas_mdqmx (iop 480 as master) 3.0 ns 8.5 ns n/a n/a cas_mdqmx (external local master) 3.0 ns 12.5 ns n/a n/a all other local pins (not serial eeprom) 3.0 ns 10.0 ns 10.0 ns 1.0 ns input clocks min max pci bus frequency 0 33 mhz local bus frequency 0 66 mhz 1.5v 1.5v address bus 12.7 / 17.7 3.7 / 8.3 4.0 / 10.0 local clock ale 8.0 / 10.0 section 19 electrical specifications i/o timing specifications iop 480 data book r2.0 19-2 ? 2000 plx technology, inc. all rights reserved. note: values provided are worst case of performance levels a, b, and c. the differences are very small. table 19-2. iop 480 local bus driver loading derating buffer type trans ition worst case (ps/pf) typical (ps/pf) best case (ps/pf) bt520 t plh 35 23 17 t phl 43 28 20 bt520 t plh 47 33 26 t phl 65 44 35 bt550 t plh 57 41 34 t phl 82 58 48 bt565 t plh 72 54 45 t phl 106 78 66 table 19-3. iop 480 pci buffer loading derating buffer type trans ition worst case (ps/pf) typical (ps/pf) best case (ps/pf) bpci5 t plh 40 28 21 t phl 44 30 22 table 19-4. absolute maximum ratings specification maximum rating storage temperature -55 to +125 o c ambient temperature with power applied -40 to +85 o c supply voltage to ground -0.5 to +4.6v input voltage (vin) vss -0.5v to 11.0v output voltage (vout) vss -0.5v to vdd +0.5 maximum power dissipation (208-pin pqfp) 1.0w maximum power dissipation (225-pin pbga) 1.0w table 19-5. operating ranges ambient temperature supply voltage (vdd) input voltage (vin) min max -40 to +85 o c 3.0 to 3.6v vss vdd table 19-6. capacitance (sample tested only) parameter test conditions pin type value units typical maximum cin vin = 0v input 4 8 pf cout vout = 0v output 6 12 pf section 19 i/o timing specifications electrical specifications iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 19-3 section 19 ? electrical specs table 19-7. package thermal resistance package type air flow 0m/s 1m/s 2m/s 3m/s 208-pin pqfp 65 (c/w) 45 35 30 225-pin pbga 72 (c/w) 46 37 32 table 19-8. electrical characteristics over operating range parameter description test conditions min max units voh output high voltage for 65-ohm driver, 50-ohm driver, 35-ohm driver, 20-ohm driver vdd = min vin = vih or vil ioh =-7.0,-10.0, -13.0, -23.0 ma 2.4 ? v vol output low voltage for 65-ohm driver, 50-ohm driver, 35-ohm driver, 20-ohm driver iol = 5.0, 7.0, 9.0, 16.0 ma ? 0.4 v vih input high level 1 ? ? 2.0 5.5 v vil input low level 1 ? ? -0.6 0.8 v voh3 pci 3.3v output high voltage vdd = min vin = vih or vil ioh = -500ua 0.9 vdd ? v vol3 pci 3.3v output low voltage iol = 1500ua ? 0.1 vdd v vih3 pci 3.3v input high voltage ? ? 0.5 vdd vdd + 0.5 v vil3 pci 3.3v input low voltage ? ? -0.5 0.3 vdd v iil input leakage vss<=vin<=vdd, vdd = max -10 +10 ua iil_rup input leakage with 10k-ohm pull-up resistors vss<=vin<=vdd, vdd = max -370 +10 ua iil_rdown input leakage with 10k-ohm pull-down resistors vss<=vin<=vdd, vdd = max -10 +370 ua ilpc dc current per pin during precharge 2 vdd = max, vp=1.0v 10% ? 4.0 ma ioz three-state output leakage current vdd = max vss<=vin<=vdd -10 +10 ua icc power supply current vdd = 3.6v, pclk = lclk=33mhz ? 200 ma iccl icch iccz quiescent power supply current vdd = max vin = gnd or vdd ? 50 ua 1. vih and vil limit for 5v tolerant receivers. 2. ilpc is the dc current flowing from vdd to ground during precharge, as both pmos and nmos devices remain on during precharge. it is not the leakage current flowing into or out of the pin under precharge. iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 20-1 section 20 ? package 20 package 20.1 208-pin pqfp package 208-pin pqfp, body size 30.80 x 30.80 mm. 20.1.1 208-pin pqfp package mechanical specifications figure 20-1. 208-pin pqfp package mechanical specifications note: drawing is not to scale. see your plx representative for released documentation. note: metric conversion to inches: x 0.03937. when designing patterns, use only metric dimensions. table 20-1. 208-pin pqfp mechanical specifications (legend for figure 20-1) symbol outside area (mm) dimensions symbol outside area (mm) dimensions a max 4.20 d min 30.40 b min 0.17 max 30.80 max 0.27 e min 30.40 d 1 min 27.90 max 30.80 max 28.10 e nominal 0.50 e 1 min 27.90 weight (g) ? 6.00 max 28.10 l min 0.50 ? max 0.75 section 20 package 208-pin pqfp package iop 480 data book r2.0 20-2 ? 2000 plx technology, inc. all rights reserved. 20.1.2 208-pin pqfp pinout figure 20-2. 208-pin pqfp pinout iop 480 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 vdd rst# clk req0# / gnt# gnt0# / req# vss ad31 ad30 ad29 ad28 ad27 vss ad26 ad25 ad24 c/be3# idsel vdd ad23 ad22 ad21 ad20 vss ad19 ad18 vdd ad17 ad16 c/be2# vss frame# irdy# trdy# devsel# stop# vdd lock# perr# serr# par vdd c/be1# ad15 ad14 ad13 vss ad12 ad11 ad10 ad9 ad8 52 vss 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 vss lad30 lad29 lad28 vss lad27 lad26 lad25 lad24 lad23 lad22 vdd lad21 lad20 lad19 lad18 vdd lad17 lad16 lad15 lad14 lad13 vss lad12 lad11 lad10 vdd lad9 lad8 vss lad7 lad6 lad5 lad4 vdd lad3 lad2 lad1 lad0 vss ad0 ad2 inta# ad1 vss ad3 ad4 ad5 ad6 ad7 c/be0# vdd 53 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 vdd lsc0# / dmpaf# lsc1# / user0 lcs2# / user1 tck vdd lcs3# / ma17 ma0 ma1 ma2 ma3 vss ma4 ma5 ma6 ma7 ma8 vss ma9 ma10 ma11 ma12 mcke vdd ras3# / mcs3# mcas# / moe# vss mras# mwe# vdd cas3# / mdqm3# eecs eedata / ts3 eesk / ts4 vdd ledon / ledin rx tx / ts5 hmode enum# pme# gnt2# / ts1 ras0# / mcs0# ras1# / mcs1# ras2# / mcs2# cas0# / mdqm0# cas1# / mdqm1# cas2# / mdqm2# req2# / ts2 207 req1# 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 vss ts6 tms tdo eot1# / eot2# / user4 mtp vss ale dp3 / ma16 trst# vdd halt# lclk vdd vdda eot0# / user3 dreq1# / dreq2# dack1# / dack2# dreq0# vss dack0# tdi boff# vdd lholdreq1 lholdack1 / breq lholdack0 / ldreq vss ads# into inti rd# cint / user2 vdd reset# vss wait# ready# bterm# lbe0# lbe1# vdd lbe2# lbe3# lwr# lad31 vdd dp2 / ma15 dp1 / ma14 dp0 / ma13 lholdreq0 / lholdack blast# 105 206 208 gnt1# vss section 20 208-pin pqfp package package iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 20-3 section 20 ? package 20.1.3 208-pin pqfp package materials and properties 20.1.4 208-pin pqfp printed circuit board (pcb) assembly compatibility all cmos 5 asic packaging products are compatible with existing surface-mount assembly tools and procedures. asic packages were qualified to use a range of solvents, fluxes, printed circuit board materials, and cross-sections. typical process conditions are listed in the following table. table 20-2. package materials and properties materials properties conductor au wire pin frame thermal conductivity (w/m- c) 155-351 pin frame thermal expansion coeff (ppm/ c) 17 inner lead pitch ( m) 190-220 maximum wire length (mm) 4.5 wire diameter ( m) 25-33 pin frame material copper pin alloy 85/15 snpb typical pin pitch (mm) 0.5 decoupling capacitors none signal interconnect wire bond die attachment material ag paste package encapsulation thermosetting epoxy resin (mold compound) mold compound tge (ppm/ c) 10-18 table 20-3. 208-pin pqfp pcb assembly compatibility process conditions pcb assembly infrared or vapor phase reflow pcb assembly temp 220 c (vps) or 235 c (ir) pcb clean process aqueous pcb rework remove / replace max placement force tbd bakeout 125 c / 24 hours section 20 package 225-pin pbga package iop 480 data book r2.0 20-4 ? 2000 plx technology, inc. all rights reserved. 20.2 225-pin pbga package pbga 225-pin, body size 27 x 27 x 2.65 mm. 20.2.1 225-pin pbga package mechanical specifications figure 20-3. 225-pin pbga package mechanical specifications note: metric conversion to inches: x 0.03937. when designing patterns, use only metric dimensions. table 20-4. 225-pin pbga package mechanical specifications (legend for figure 20-3) symbol tolerance (+/-) dimensions symbol tolerance (+/-) dimensions a 0.109 0.67 d1 and e1 0.051 21.00 b 0.100 1.20 e nominal 1.50 b 0.100 0.60 i/o matrix ? 15 x 15 c, max ? 2.65 populated rows (f) ? full d and e 0.203 27.00 ? pbga side viewed from die side viewed from a1 corner e1 e d d1 c b a b r p n m l k j h g f e d c b a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 section 20 225-pin pbga package package iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 20-5 section 20 ? package 20.2.2 225-pin pbga suggested land pattern for pcb layout figure 20-4. 225-pin pbga suggested land pattern for pcb layout topside view pin a1 pin a1 designator (silkscreen) copper crop lines (allows for visual inspection of whether the pbga is centered on the pads) 0.100" 0.010" 28.000 28.000 1.500 mm detail of each pad and breakout solder mask 0.011" fhs 0.009" 0.025" via pad diameter 0.028" diameter land solder mask keepout 0.002" - 0.003" 0.016" solder mask keepout around fhs section 20 package 225-pin pbga package iop 480 data book r2.0 20-6 ? 2000 plx technology, inc. all rights reserved. 20.2.3 225-pin pbga package layout figure 20-5. 225-pin pbga underside a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 viewed through pbga signal ground voltage a01 locator section 20 225-pin pbga package package iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 20-7 section 20 ? package 20.2.4 225-pin pbga pinout table 20-5. 225-pin pbga pinout pin # symbol pin # symbol pin # symbol pin # symbol a1 vdd c1 ad31 e1 c/be3# g1 ad19 a2 req2# / ts2 c2 req0# / gnt# e2 ad25 g2 vss a3 hmode c3 gnt1# e3 ad26 g3 ad20 a4 ledon / ledin c4 enum# e4 ad28 g4 ad21 a5 vss * c5 vdd e5 gnt0# / req# g5 nc a6 cas1# / mdqm1# c6 cas3# / mdqm3# e6 rx g6 ad29 a7 mras# c7 mwe# e7 vdd g7 vss a8 vdd c8 ras1# / mcs1# e8 ras3# / mcs3# g8 vss a9 ras0# / mcs0# c9 ma12 e9 vss * g9 vss a10 ma10 c10 vss e10 ma6 g10 dp0 / ma13 a11 ma7 c11 ma4 e11 tck g11 eot0# / user3 a12 ma3 c12 vdd e12 nc g12 dreq1# / dreq2# a13 lcs3# / ma17 c13 tms e13 vdd g13 dack1# / dack2# a14 lcs1# / user0 c14 mtp e14 halt# g14 dack0# a15 vdd c15 ale e15 nc g15 dreq0# b1 clk d1 ad27 f1 ad22 h1 vdd b2 req1# d2 ad30 f2 ad23 h2 nc b3 pme# d3 vss f3 vdd h3 ad18 b4 tx /ts5 d4 rst# f4 idsel h4 ad17 b5 eedata / ts3 d5 vss * f5 ad24 h5 ad16 b6 cas2# / mdqm2# d6 eesk / ts4 f6 gnt2# / ts1 h6 vss b7 mcas# / moe# d7 cas0# / mdqm0# f7 eecs h7 vss b8 nc d8 ras2# / mcs2# f8 vss h8 vss b9 mcke d9 ma11 f9 ma1 h9 vss b10 ma9 d10 ma8 f10 eot1# / eot2# / user4 h10 vss b11 ma5 d11 ma2 f11 trst# h11 tdi b12 ma0 d12 lcs0# / dmpaf# f12 dp1 / ma14 h12 boff# b13 lcs2# / user1 d13 vss f13 lclk h13 lholdreq1 b14 ts6 d14 dp3 / ma16 f14 vdd h14 llock# * b15 tdo d15 dp2 / ma15 f15 vdda h15 vdd section 20 package 225-pin pbga package iop 480 data book r2.0 20-8 ? 2000 plx technology, inc. all rights reserved. note: * pbga package only. j1 frame# l1 vss n1 vss r1 vdd j2 c/be2# l2 serr# n2 ad11 r2 ad7 j3 irdy# l3 vdd n3 ad8 r3 ad3 j4 trdy# l4 ad13 n4 ad4 r4 ad0 j5 devsel# l5 ad5 n5 inta# r5 lad2 j6 perr# l6 lad1 n6 vdd r6 lad5 j7 vss l7 nc n7 lad7 r7 lad8 j8 vss l8 lad11 n8 lad9 r8 vdd j9 vss l9 lad16 n9 lad14 r9 lad13 j10 bterm# l10 lad23 n10 lad18 r10 lad17 j11 nc l11 lbe2# n11 vdd r11 vss * j12 vss l12 ready# n12 lad26 r12 lad22 j13 lholdack0 / ldreq l13 reset# n13 lad29 r13 lad25 j14 lholdreq0 / lholdack l14 vdd n14 lbe3# r14 lad28 j15 lholdack1 / breq l15 rd# n15 lbe1# r15 vdd k1 stop# m1 c/be1# p1 ad9 ? k2 vdd m2 ad14 p2 nc k3 lock# m3 ad12 p3 ad6 k4 pa r m4 c/be0# p4 vss k5 ad15 m5 ad1 p5 lad0 k6 ad10 m6 lad3 p6 lad4 k7 ad2 m7 lad6 p7 vss k8 vss m8 lad10 p8 nc k9 lad19 m9 lad15 p9 lad12 k10 vss m10 lad21 p10 vdd k11 cint / user2 m11 vss * p11 lad20 k12 inti m12 lad31 p12 lad24 k13 into m13 vdd p13 lad27 k14 ads# m14 lbe0# p14 lad30 k15 blast# m15 wait# p15 lwr# table 20-5. 225-pin pbga pinout (continued) pin # symbol pin # symbol pin # symbol pin # symbol section 20 225-pin pbga package package iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 20-9 section 20 ? package 20.2.5 225-pin pbga package materials and properties 20.2.6 225-pin pbga printed circuit board (pcb) assembly compatibility all cmos 5 asics packaging products are compatible with existing surface mount assembly tools and procedures. our packages were qualified to use a range of fluxes, printed circuit board materials, and cross-sections. typical process conditions are listed in the following table. single-sided card assembly is qualified. contact your plx representative regarding dual-sided card assembly. 20.2.7 225-pin pbga die attach wire bond 20.2.8 225-pin pbga encapsulation molded resin table 20-6. pbga package materials/properties materials properties conductor copper dielectric bt epoxy dielectric constant 4.1-4.3 at 1 mhz thermal conductivity (w/m- c) 0.40 thermal expansion coeff (ppm/ c) 40-50 z-directions 10-15 xy-directions nom line width (mm) 0.102 nom line spacing (mm) 0.102 line thickness (mm) 0.033 dielectric thickness / layer (mm) 0.52 pin (ball) alloy 63/37 snpb pin (ball) pitch (mm) (225 pins) 1.5 pin (ball) diameter (mm) 0.75 discrete decoupling capacitor none die interconnect wire bond package encapsulation epoxy overmold table 20-7. pbga typical process conditions process conditions pcb assembly infrared reflow max pcb assembly temp 220 c pcb clean process aqueous pcb rework remove / replace iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 21-1 section 21 ? timing diagrams 21 timing diagrams reference list sections in which iop 480 timing diagrams can be found are listed in the following table, with a reference page to the beginning of each section. for a complete catalog of iop 480 timing diagrams, refer to the list of timing diagrams on page xxxiii. note: each section describes a specific operation. table 21-1. iop 480 timing diagram sections section page iop 480 cpu bootup cycle 6-3 vpd 15-3 big endian 2-14 pci signals 3-2 configuration cycle pci configuration reads or writes pci memory reads or writes local master configuration reads or writes 4-12 4-14 5-10 direct slave 4-16 direct slave burst 4-27 direct master pci configuration reads or writes direct master operation 5-8 5-10 dma 7-14 i 2 o 13-7 local bus controller wait states 2-7 local bus controller direct slave or dma burst 2-9 local bus controller arbiter round-robin arbitration 8-2 memory controller sram write access 12-6 memory controller sram read access 12-10 memory controller sdram initialization, refresh, start, and end 12-20 memory controller sdram write access 12-23 memory controller sdram read access 12-33 memory controller edo dram refresh 12-43 memory controller edo write access 12-44 memory controller edo read access 12-49 iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 22-1 section 22 ? spu 22 serial port operation this section describes the iop 480 asynchronous serial port unit (spu). included is information about the serial port hardware elements, operations and operating modes, and details of registers and buffers. the spu can be accessed only from the iop 480 cpu, although it uses local memory space. 22.1 overview the spu runs at speeds up to one-sixteenth of the external (lclk) clock rate and provides features typically found on advanced serial communications controllers, including internal loopback mode, automatic echo mode, and automatic handshaking capability on receive operations. the spu comprises three main elements ? receiver, transmitter, and baud rate generator (figure 22-1). figure 22-1. serial port functional block receiver transmitter lclk baud rate rx dtr /rts tx connected to 0 generator loopback automatic echo to opb from opb baud rate clock x 16 serial port serial port data data internal iop 480 (not connected) section 22 serial port operation spu operating mode selection iop 480 data book r2.0 22-2 ? 2000 plx technology, inc. all rights reserved. 22.2 spu operating mode selection the spu can be configured to operate in normal, loopback, or automatic echo mode by setting the loopback mode (lm) bits in the serial port control (spctl) register, as shown in table 22-1. 22.2.1 normal mode in normal mode, the spu performs as a standard uart. bytes of data are received and transmitted by way of the rx and tx lines, respectively. 22.2.2 internal loopback mode in internal loopback mode, data being transmitted is internally routed to the receiver. note: in this operation mode, both the transmitter and receiver must be enabled. 22.2.3 automatic echo mode in automatic echo mode, as each bit of data is received on the rx input, it is retransmitted on the tx output with a delay of one baud rate clock cycle. thus, the transmitter is acting in a ? pass-through ? mode, implying that any errors in the data stream are also transmitted as they are seen. all handshaking signals operate as they do in normal mode. note: in this operation mode, the receiver must be enabled and the transmitter must be disabled. 22.3 spu registers serial port registers are memory-mapped and are therefore accessed via load/store instructions at the address of the register. they can only be accessed by the internal iop 480 cpu. because the spu is a byte device, its registers are eight bits and are usually accessed using load byte and store byte instructions. load/store word and lword instructions can also access the serial port registers. when these instructions are used, the bus interface unit (biu) breaks register accesses into discrete byte operations. table 22-2 lists the memory-mapped addresses for the user-accessible registers in the serial port. note: although the sprb and sptb are logically separate registers, they are mapped to the same physical address. figure 22-2 represents the serial port registers as they relate to the individual components within the spu. the serial port control register (spctl) controls the overall operation of the serial port. it provides the data frame format to the transmitter and receiver (number of data/stop bits and parity generation/detection), controls the state of the dtr and rts signals (should always be inactive for the iop 480), and specifies the spu mode of operation (normal, internal loopback, auto echo). the line status register (spls) and handshake status register (sphs) gather status information for the serial port. the spls contains status information for the receiver (rxready, parity, framing and overrun errors, and line break detection) and the transmitter (tbr and tsre). the sphs contains the status of the input handshake signals ( cts / dsr inactive). the baud rate generator contains the two baud rate divisor registers, brdh and brdl. although both baud rate registers are 8-bit registers, only the least significant four bits of the brdh are implemented. (if this is true, then the slowest baud rate for the external 66 mhz clock is greater than 1000). the contents of these registers are concatenated to form a 12-bit divisor which is used to derive the frequency at which to transmit and receive data through the spu. table 22-1. spu operating mode selection mode spctl register bit settings normal lm = 00 internal loopback lm = 01 automatic echo lm = 10 section 22 spu registers serial port operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 22-3 section 22 ? spu figure 22-2. spu registers and buffers table 22-2. serial port register addresses, names, and access modes memory-mapped i/o address name mnemonic access modes 0x4000 0000 serial port line status register (clear) spls read/write 0x4000 0004 serial port line status register (set) ?? 0x4000 0008 serial port handshake status register sphs read/write 0x4000 000c reserved ?? 0x4000 0010 baud rate divisor high register brdh read/write 0x4000 0014 baud rate divisor low register brdl read/write 0x4000 0018 serial port control register spctl read/write 0x4000 001c serial port receiver command register sprc read/write 0x4000 0020 serial port transmitter command register sptc read/write 0x4000 0024 serial port receive/transmit buffer sprb/sptb sprb is read only sptb is write only spctl sptb sptsr brdh brdl sprc sprsr sprb opb sphs rx tx generator baud rate transmitter receiver clock source sptc baud rate clock x 16 spls section 22 serial port operation spu operations iop 480 data book r2.0 22-4 ? 2000 plx technology, inc. all rights reserved. the serial port transmitter (spt) consists of an 8-bit transmit buffer (sptb), a parallel-to-serial shift register (sptsr), and a command register (sptc). the sptc contains control information specific to the transmitter, such as the transmitter enable, interrupt enables, line break generation enable, pattern generation mode enable, and auto-handshaking enable (stop/pause on cts input). data to be transmitted is loaded into the sptb until the data is transferred into the sptsr when transmission begins. the transmitter reports sptsr and sptb full/empty status, reflected as tsre and tbr, respectively in the spls register. the transmitter also provides the status of the handshaking inputs for the sphs register. the serial port receiver (spr) consists of an 8-bit receive buffer (sprb), a serial-to-parallel shift register (sprsr), and a command register (sprc). the sprc contains control information specific to the receiver, such as the receiver enable, interrupt enables, and auto-handshaking enable (hardware/ software control of the rts output). when a data byte has been received by the sprsr, it is transferred to the sprb, provided that no errors were detected, and then sprb full status (reflected in rxready) is reported to the spls register. data characters that contain errors are discarded, and the error condition (framing, parity, overrun or line breaks) is posted in the spls register. for a complete bit description of these registers, refer to section 22.5, ? spu register descriptions. ? 22.4 spu operations 22.4.1 spu baud rate generator the frequency used to transmit and receive data through the spu is derived from the baud rate generator clock input and the contents of the baud rate divisor registers. the baud rate generator clock input comes from the external system clock (lclk). the baud rate generator divides the rate of the baud rate generator clock by the value obtained by the concatenated value of the two baud rate divisor registers, brdh and brdl, resulting in a clock frequency 16 times faster than the desired baud rate. as shown in figure 22-1, the output from the baud rate generator drives the transmitter and receiver baud rate inputs. those inputs are then divided by 16 internally to the receiver and the transmitter to generate the required baud rate clock frequency. the baud rate for the serial port can be calculated with the following equation. equation 22-1. calculating the serial port baud rate alternatively, the contents of brdh and brdl can be calculated from the baud rate with the following equation. equation 22-2. calculating the contents of brdh and brdl table 22-3 shows selected contents of the baud rate divisor registers and the resulting baud rates when a 66 mhz clock input is applied to the lclk input. (refer to equation 22-2.) 22.4.2 spu transmitter as mentioned previously, the main components of the spt are an 8-bit transmit buffer (sptb), a parallel-to- serial shift register (sptsr), and a command register (sptc). to enable the transmitter, the et bit of the sptc must be set to 1. if et is set to 0, the transmitter is disabled, no data is transmitted, and no interrupts (dsr inactive, cts inactive, transmit buffer ready, or transmitter shift register empty) are requested. if et is reset to 0 during transmission, the transmission immediately terminates and the tx output is driven to 1. table 22-3. baud rate divisor selection brdh contents brdl contents baud rate 0x35 0x6c 1200 0x0d 0xb5 2400 0x06 0x5a 4800 0x03 0xac 9600 0x01 0xd5 19200 0x00 0x6a 38400 baud rate = 1 16 x lclk frequency (in hz) (brdh || brdl) (brdh, brdl) = 1 16 x lclk baud rate () section 22 spu operations serial port operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 22-5 section 22 ? spu transmit buffer ready (tbr) and transmit shift register empty (tsre) are the only two bits in the spls register that reflect transmitter status (represented by bits tbr and tsr, respectively). the following table describes what the possible combinations of these status bits represent. data to be transmitted is first loaded into the sptb; tbr updates from a logic 1 to a logic 0. if the transmitter is enabled and the sptsr is empty (tsre = 1), then the data is immediately transferred to the sptsr, causing tsre to update from a logic 1 to a logic 0 and tbr to return to a value of logic 1, indicating that the sptb is ready to be loaded with another piece of data. when a piece of data is transferred to the sptsr, the start, stop, and parity bits are added, and the transmission of the character begins immediately. note: for 7-data bit frame formats, the least significant seven bits of the sptb are transmitted, least significant bit first. while the transmitter is shifting out the current piece of data, the sptb may be loaded with the next piece of data. when transmission of the current piece of data completes, the next piece of data is transferred to the sptsr and the process repeats. note: tsre stays at a value of logic 0 until either a handshaking error is flagged or no other characters are loaded into the sptb. 22.4.2.1 pattern generation mode pattern generation mode (pgm) is enabled by the pgm bit in the sptc, sptc[pgm] = 1. when pgm is enabled, the spt operates in basically the same way as when pgm is disabled, except that the generation of start and stop bits during character transmissions are suppressed. thus, the spu essentially becomes a pattern generator, where only the seven or eight data bits and parity bit (if enabled) will be transmitted. this allows the spt to be used for pulse width modulation, with duty-cycle variation controlled by frame size, baud rate, and data pattern. 22.4.2.2 transmitter line break generation setting the transmit break (tb) bit of the sptc to a logic 1 forces a continuous stream of zeros on the tx output, assuming that the transmitter is enabled. the spu transmitter will continue to transmit break characters until the tb bit is reset to a logic 0. setting the tb bit to 1 should only be done when the spt is idle. forcing the transmission of break characters when the spt is active has undefined results. 22.4.2.3 transmitter interrupts the spt interrupts can be generated from one of the following three conditions. each of these conditions has separate interrupt enables in the sptc. txready (tbr) is active in the spls register tsre is active in the spls register handshaking error (dis or cis) is flagged in the sphs register an interrupt is generated whenever the sptb is ready to be loaded with new data. the tie bit of the sptc is the enable for generating interrupts based on tsre. when tsre and tie are both set to 1, the spu will raise the transmitter interrupt request to the asynchronous interrupt controller unit to indicate that character transmission has completed. when a transmitter interrupt request to the asynchronous interrupt controller occurs, the serial port transmitter interrupt status (stis) bit of the external interrupt status register (exisr) is set. note: the exception is processed only if the serial port transmitter interrupt enable (stie) bit of the external interrupt enable register (exier) and the external interrupt enable (ee) bit of the machine state register (msr) are also set. 22.4.3 spu receiver the main components of the spu receiver are an eight-bit receive buffer (sprb), a serial-to-parallel shift register (sprsr), and a command register (sprc). to enable the receiver, the er bit of the table 22-4. tbr/tsre status representation tbr tsre description 11 transmitter is idle; no data in transmit buffer. note: this is the transmitter status out of reset. 01 transmitter is idle; data was either just loaded into transmit buffer, or is being held there due to handshaking line loss. 10 transmitter is transmitting a character; no new data loaded into transmit buffer. 00 transmitter is transmitting a character; next character waiting in transmit buffer. section 22 serial port operation spu register descriptions iop 480 data book r2.0 22-6 ? 2000 plx technology, inc. all rights reserved. sprc must be set to one. when the spr is enabled, data received from the rx pin is input to the sprsr. if a character is received without errors, the character is transferred from the sprsr to the sprb, and the rxready (rbr) bit in the spls is set. if the data frame is configured for seven bits, the most significant bit of the byte loaded from the sprb is set to 0 and the received data occupies the rest of the byte. the rbr bit of the spls register is reset to 0 when the data byte in the sprb is read by the processor. if errors are detected during the reception of a character, then the error condition (parity error, framing error, overrun error or line break detect) is posted in the spls register and the data byte discarded. parity errors are detected when the received parity of a data frame does not match the expected parity of the data frame. this causes the parity error (pe) bit of the spls register to be set. framing errors imply that one or both of the first stop bits of the received data frame were a zero. when this error is detected, the framing error (fe) bit of the spls register is set. a line break is detected when a character is received and all of the bits of the frame, including data, parity, and stop bits are zeros. this condition will cause the line break (lb) bit of the spls to be set to 1. notes: framing errors are also flagged when a line break is detected. line breaks are detected only on character boundaries. if a line break begins within a character, a framing error is detected. if the line break condition persists for the time equivalent to receiving another character, the line break error is detected. after a line break is detected, the spr begins searching for the end of the line break, defined as a period of logic equivalent to the time required to receive one data bit of a frame. when the end of the line break is detected, receiver operation continues normally. there are two cases where the sprsr receives a character without errors but that character is not transferred to the sprb and is instead held in the sprsr. the first is when the sprb is full, and the second is if there are any receiver errors (pe, fe, oe, lb) posted in the spls register. the character being held in the sprsr is not moved into the sprb until application software either removes the character currently in the sprb by performing a read operation, or clears the error condition(s) in the spls register. errors are cleared from the spls register by writing a logic 1 to the appropriate bit. an overrun error occurs when the sprsr is holding a valid character (it cannot move into the sprb due to the conditions mentioned) and another character starts to be received. in this event, the character in the sprsr is overwritten with the new character and the overrun error (oe) bit in the spls register is set. 22.4.3.1 receiver interrupts the spr interrupts are generated based on two conditions: rxready (rbr) being active, or any of the receiver errors (pe, fe, oe, lb) being active in the spls register. both of these conditions have separate interrupt enables in the sprc register. an interrupt request is sent to the asynchronous interrupt control unit whenever the sprb has received a new character. similarly, the error interrupt enable (eie) bit of the sprc register enables an interrupt request whenever a framing, parity, overrun error, or line break is detected. when a receiver interrupt request to the asynchronous interrupt controller occurs, the serial port receiver interrupt status (sris) bit of the external interrupt status register (exisr) is set. however, the exception is processed only if the serial port receiver interrupt enable (srie) bit of the external interrupt enable register (exier) and the external interrupt enable (ee) bit of the machine state register (msr) are also set. 22.5 spu register descriptions the following sections provide a complete bit description of the nine addressable spu registers. 22.5.1 baud rate divisor registers the brdh and brdl registers store a divisor for reducing the rate of the input clock source to a convenient baud rate. the contents of the brdh are concatenated with the contents of the brdl to form a 12-bit divisor. the baud rate calculation using the 12-bit divisor is described in section 22.4.1, ? spu baud rate generator. ? register 22-1 illustrates the brdh bits. register 22-2 illustrates the brdl bits. section 22 spu register descriptions serial port operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 22-7 section 22 ? spu 22.5.2 serial port control register (spctl) the spctl configures the serial port for normal, internal loopback, or automatic echo mode. this register also controls the activity of the dtr / rts signal and the frame format of the serial transfers. register 22-3 illustrates the spctl bits. register 22-1. baud rate divisor high register (brdh) 0:3 reserved 4:7 divisor high bits the four most significant bits of the baud rate divisor; concatenated with the contents of the brdl. register 22-2. baud rate divisor low register (brdl) 0:7 divisor low bits the eight least significant bits of the baud rate divisor; concatenated with the contents of the brdh. 47 03 07 register 22-3. serial port control register (spctl) 0:1 lm loopback modes 00 - normal mode 01 - internal loopback mode 10 - automatic echo mode 11 - reserved 2dtr data terminal ready 0 - dtr signal is inactive 1 - dtr signal is active 3rts request to send 0 - rts signal is inactive 1 - rts is active 4db data bits 0 - 7 data bits 1 - 8 data bits when db = 0, a data frame contains the least significant seven bits (bits 1:7) in the sptb or the sprb. 5pe parity enable 0 - no parity 1 - parity enabled when pe = 0, parity detection and generation are disabled for the serial port receiver and transmitter. 6pty parity 0 - even parity 1 - odd parity when pty = 0, even parity is used in parity detection and generation. when pty = 1, odd parity is used. 7sb stop bits 0 - one stop bit 1 - two stop bits when sb = 0, one stop bit is transmitted at the end of each data frame. when sb = 1, two stop bits are transmitted. in either case, the receiver only checks the first stop bit to detect the end of a received data frame. 012 34567 lm rts sb pty db dtr pe section 22 serial port operation spu register descriptions iop 480 data book r2.0 22-8 ? 2000 plx technology, inc. all rights reserved. 22.5.3 serial port handshake status register (sphs) the sphs reports the status of the dsr or cts signal while the spt is enabled. register 22-4 illustrates the sphs bits. 22.5.4 serial port line status register (spls) the spls reflects the status of the spr and spt, and it reports errors detected in a received character. the bits in the spls are reset to 0 by writing a 1 to the bit positions using a store instruction. writing a 0 to a bit position does not affect the bit value. register 22-5 illustrates the spls bits. register 22-4. serial port handshake register (sphs) 0dis dsr input inactive error: 0 - dsr input is active 1 - dsr input has gone inactive to reset the dis bit, the application software must store a 1 in this bit location at the address of the sphs. 1cs cts input inactive error: 0 - cts input is active 1 - cts input has gone inactive to reset the cs bit, the application software must store a 1 in this bit location at the address of the sphs. 2:7 reserved 0 1 dis cs 2 7 register 22-5. serial port line status register (spls) 0 rb r receive buffer ready 0 - receive buffer is not full 1 - receive buffer is full reset by hardware when received data is read from the sprb into a gpr using a load instruction or during chip reset; can be reset by software. 1fe framing error 0 - no framing error detected 1 - framing error detected must be reset by software. 2oe overrun error 0 - no overrun error detected 1 - overrun error detected must be reset by software. 3pe parity error 0 - no parity error detected 1 - parity error detected must be reset by software. 4lb line break 0 - no line break detected 1 - line break detected must be reset by software. 5tbr transmit buffer ready 0 - transmit buffer is full (not ready) 1 - transmit buffer is empty and ready tbr is set to 1 whenever the sptsr is loaded with a character from the sptb. tbr is reset to 0 when a new character is stored in the sptb. 6tsr transmitter shift register ready 0 - transmitter shift register is full 1 - transmitter shift register is empty tsr is set to 1 whenever the sptsr is empty. tsr is reset to 0 when a new character is transferred from the sptb into the sptsr and remains reset as characters are transmitted. 7 reserved 01 23456 rbr oe lb tsr tbr pe fe 7 section 22 serial port transmit command register (sptc) serial port operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 22-9 section 22 ? spu 22.5.5 serial port receive buffer (sprb) register 22-6 illustrates the sprb bits. 22.5.6 serial port receiver command register (sprc) the sprc controls the spr. register 22-7 illustrates the sprc bits. 22.5.7 serial port transmit buffer (sptb) the sptb holds characters to be transmitted using the sptsr. if the spt is enabled and the sptsr is empty, data loaded into the sptb is loaded into the sptsr and transmitted. when data is loaded from the sptb into the sptsr, then spls[tbr] is set to 1 and spls[tsr] is reset to 0. register 22-8 illustrates the sptb bits. 22.6 serial port transmit command register (sptc) register 22-9 illustrates the sptc bits. register 22-6. serial port receive buffer (sprb) 0:7 received data register 22-7. serial port receiver command register (sprc) 0er enable receiver 0 - disable receiver 1 - enable receiver for the spr to operate, er must be set to 1. if er is reset to 0, the spr is disabled, no data is shifted into the sprsr, and no spr interrupts are active. 1ie rbr interrupt enable 0 - disable rbr interrupt 1 - enable rbr interrupt 2 reserved 3eie error interrupt enable 0 - receiver error interrupt disabled 1 - receiver error interrupts enabled 4pme pause mode enable 0 - rts is controlled by software 1 - rts is controlled by hardware 5:7 reserved 07 034 er eie pme 7 5 12 register 22-8. serial port transmit buffer (sptb) 0:7 transmit data data to be transmitted by the sptsr register 22-9. serial port transmitter command register (sptc) 0et enable transmitter: 0 - disable transmitter 1 - enable transmitter chip reset or system reset clears to 0. 1ie tbr interrupt enable 0 - disable tbr interrupt 1 - enable tbr interrupt 2 reserved 3tie transmitter empty interrupt enable 0 - transmitter shift register empty interrupt disabled 1 - transmitter shift register empty interrupt enabled 4eie transmitter error interrupt enable: 0 - transmitter shift register error interrupt disabled 1 - transmitter shift register error interrupt enabled 07 034 et tie 7 6 5 eie spe tb pgm 12 section 22 serial port operation initialization and configuration iop 480 data book r2.0 22-10 ? 2000 plx technology, inc. all rights reserved. 22.7 initialization and configuration prior to enabling spu operation, spu configuration registers have to be written with appropriate initial settings. spu status registers have to be cleared to a clean initial idle state. following is a sample sequence for writing or clearing the spu registers: baud rate divisor high register baud rate divisor low register line status register handshake status register control register receiver command register transmitter command register the line status (spls) register is functionally two locations that either clear or set bits in the spls. the ? 0 ? location is written with zeros to clear (reset) selected bits in the spls, and the ? 1 ? location is written with ones to set selected bits in the spls. all register offsets are shown in table 22-2. during initialization the transmit buffer ready (tbr) bit in the line status register should be set to 1, or the invalid contents of the transmit buffer will be shifted into the transmit shift register and sent out as soon as transmitter operation is enabled. the handshake status (sphs) register is also functionally two locations that either clear or set bits in the sphs. the ? 2 ? location is written with zeros to clear (reset) selected bits in the spls, and the ? 3 ? location is written with ones to set selected bits in the spls. only these two status registers are organized in this manner. 22.7.1 initializing spu registers exact spu configuration settings vary, depending on specific operating system and application requirements affecting spu speed and operating mode. for that reason, the following pseudo code samples present a generalized sequence for configuring the spu status and control registers and for initializing normal operation. the following code is shown for example purposes only; however, the first seven commands must be implemented exactly as written, with the exact same values, and in the exact same order ( refer to the assembly code example provided in appendix c, ? real code example ? ). /* */ /* initialize and configure the serial port */ /**/ stb(brdh_addr, 0); /* clear serial port baud rate divisor high */ stb(brdl_addr, 0); /* clearserial port baud rate divisor low */ stb(spls_addr, 0x78); /* clear error bits in serial port line status */ stb(sphs_addr, 0xff); /* clear error bits in serial port handshake status*/ stb(spctl_addr, 0); /* clear serial port control register */ stb(sprc_addr, 0); /* clear serial port receiver command register */ stb(sptc_addr, 0); /* clear serial port transmitter command register*/ stb(brdh_addr, baud_rate_high); /* program desired baud rate divisor, high */ stb(brdl_addr, baud_rate_low); /* program desired baud rate divisor, low */ stb(spctl_addr, serial_port_config);/* configure serial port */ /* transmitter and receiver may be */ /* enabled any time after an interrupt service */ /* routine is available */ 5spe stop/pause on cts inactive 0 - pause mode when cts is inactive 1 - stop mode when cts is inactive 6tb transmit break 0 - disable break character generation 1 - enable break character generation 7pgm pattern generation mode 0 - disable pattern generation 1 - enable pattern generation chip reset or system reset clears to 0. register 22-9. serial port transmitter command register (sptc) (continued) section 22 initialization and configuration serial port operation iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 22-11 section 22 ? spu table 22-5 lists the parameters that must be initialized in the control register. 22.7.2 enabling normal spu operation spu data transfers may be handled either in polled mode or with normal interrupt processing. in polled mode, the receive buffer ready (rbr) bit and the pair of transmit buffer ready (tbr) transmit shift register ready (tsr) bits may be read to determine the status of the receive and transmit buffers. in interrupt mode, the interrupt control bits in the sprc and the sptb must be set to enable or disable interrupt generation from the receive or transmit buffers. in polled mode, the rbr bit in the line status register must be tested periodically to determine when the receive buffer is full. when rbr = 1, the receive buffer is full and should be read. prior to reading the byte from the buffer, test the framing error bit and the overrun error bit to determine whether errors were detected during the transfer. similarly, the tbr bit in the line status register must be tested periodically to determine when the transmit buffer is empty. when tbr = 1, the transmit buffer is ready to be written with another byte to be transmitted. in interrupt mode, the receiver or the transmitter sets an interrupt to indicate that an interrupt service routine (isr) needs to read or write the receive/transmit buffer. the receiver interrupt and receiver interrupt error bits are set in the sprc to enable receiver interrupt processing. the transmitter interrupt and transmitter error bits are set in the sptc to enable transmitter interrupt processing. in either polled or interrupt mode, the receiver enable bit sprc[er] or the transmitter enable bit sptc[te] is set to enable either unit to begin processing. in interrupt mode, the machine state register bit msr[ee] must also be set to enable interrupts from the spu so that normal spu interrupt service routine processing can begin. /* */ /* enable serial port operation and interrupt processing*/ /**/ stb(spctl_addr, 0x0c); /* enable normal serial port operating mode */ stb(sprc_addr, 0xa0); /* enable serial port receiver and interrupt */ stb(sptc_addr, 0x9a); /* enable serial port transmitter and interrupt */ lwz(gprn, 0x00029030);/* load msr configuration into gprn */ mtmsr(gprn);/* enable msr exception handling*/ the spu reads and writes are processed as loads and stores between gprs in the iop 480 cpu and the spu receive/transmit buffer. when an rbr interrupt is generated, the associated isr is called to test error status bits and load the byte from the receive buffer to a gpr. conversely, when a tbr interrupt is generated, an isr is called to store a byte from a gpr to the transmit buffer. interrupt processing continues as long as a unit and its interrupts are enabled. by contrast, the rate at which polling is scheduled depends on the selected spu operating speed. the spu polling routine can be configured to execute often enough to assure that the receive buffer is not overrun or that the transmit buffer does not go empty as long as data is available to process. error handlers are also required to handle anomalies in spu operations, especially considering that serial link speeds vary, affecting intercharacter timing, and links can time out altogether. error handlers can be written to handle many such anomalies, as well as processing interrupts from framing errors, receive buffer overruns, and other spu errors. table 22-5. initialized control register parameters parameter description mode spu set for normal operation. data length either seven or eight bits. stop bits either one or two bits. parity either disabled or enabled. if parity is enabled, whether odd or even parity. iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 23-1 section 23 ? cpu overview 23 iop 480 cpu overview the iop 480 incorporates the powerpc, 32-bit reduced instruction set computer (risc) embedded controller core, and in this document is referred to as the iop 480 cpu, which implements powerpc architecture with extensions for embedded applications. this section describes: iop 480 cpu features layered powerpc architecture iop 480 cpu implementation of ibm powerpc embedded environment, an extension of the powerpc architecture for embedded applications iop 480 cpu organization, including a block diagram and descriptions of the functional units iop 480 cpu registers iop 480 cpu addressing modes 23.1 features the iop 480 cpu 32-bit risc-embedded controller core provides high performance and low power consumption. the iop 480 cpu risc executes at sustained speeds approaching one cycle per instruction. the iop 480 cpu features follow. 23.1.1 powerpc risc fixed-point cpu thirty-two, 32-bit general purpose registers (gprs) branch prediction single-cycle execution for most instructions hardware multiply/divide for faster integer arithmetic enhanced string and multiple-word handling progammable interval timer (pit), fixed interval timer (fit), and watchdog timer support for trace and trace-back 23.1.2 storage control separate, configurable instruction and data cache units supports 4 kb and 2 kb instruction and data cache arrays flush queue for fill-first operations during cache misses operand forwarding during cache line fills 23.1.3 memory management translation of the 4-gb logical address space into physical addresses independent enabling of instruction and data translation/protection page level access control using the translation mechanism software control of page replacement strategy additional control over protection using zones wikge (write-through, cacheability, compressed, guarded, endian) storage attributes core interfaces that support a wide range of function and performance: separate 32-bit instruction and data interfaces to the processor local bus (plb) clock and power management jtag debug interface section 23 iop 480 cpu overview powerpc architecture iop 480 data book r2.0 23-2 ? 2000 plx technology, inc. all rights reserved. 23.2 powerpc architecture the powerpc architecture comprises three levels of standards: powerpc user instruction set architecture, including the base user-level instruction set, user-level registers, programming model, data types, and addressing modes. this is referred to as book i of the powerpc architecture. powerpc virtual environment architecture, describing the memory model, cache model, cache-control instructions, address aliasing, and related issues. while accessible from the user level, these features are intended to be accessed from within library routines provided by the system software. this is referred to as book ii of the powerpc architecture. powerpc operating environment architecture, including the memory management model, supervisor-level registers, and the exception model. these features are not accessible from the user level. this is referred to as book iii of the powerpc architecture. book i and book ii define instructions and facilities available to the application programmer. book iii defines features, such as system-level instructions, that are not directly accessible by user applications. the powerpc architecture guarantees application code compatibility across all powerpc implementations to help maximize the cross-platform portability of applications developed for powerpc processors. this is accomplished through compliance with the first level of architectural standard, the powerpc user instruction set architecture, which is common for all powerpc implementations. 23.3 iop 480 cpu as powerpc implementation the iop 480 cpu implements the powerpc user instruction set architecture, user-level registers, programming model, data types, and addressing modes for 32-bit fixed-point operations. the iop 480 cpu fully complies with specifications for 32-bit implementations of the powerpc user instruction set architecture. the 64-bit operations are not supported, nor are the floating point operations. such operations are trapped and can be emulated in software. most of the architected features of the iop 480 cpu are compatible with the specifications for the powerpc virtual environment and operating environment architectures, as specified for processors such as the 6xx family of powerpc processors. the iop 480 cpu also provides a number of optimizations and extensions to the lower layers of the powerpc architecture. the full architecture of the iop 480 cpu is defined by the powerpc embedded environment and the powerpc user instruction set architecture. the primary extensions of the powerpc architecture defined in the embedded environment are: a simplified memory management mechanism with enhancements for embedded applications an enhanced, dual-level interrupt structure the addition of several instructions to support these modified and extended resources finally, some of the specific implementation features of the iop 480 cpu are beyond the scope of powerpc architecture. these features are included to enhance performance, integrate functionality, and reduce system complexity in embedded control applications. section 23 iop 480 cpu organization iop 480 cpu overview iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 23-3 section 23 ? cpu overview figure 23-1. iop 480 cpu block diagram 23.4 iop 480 cpu organization the iop 480 cpu consists of a three-stage pipelined processor core, memory management unit (mmu), separate instruction and data cache units, jtag, debug, trace logic, and three timers. the powerpc user instruction set architecture and special purpose registers (sprs) provide a high degree of user control over configuration and operation of the functional units, both interface and core. figure 23-1 illustrates the logical organization of the iop 480 cpu. 23.4.1 risc processor core the risc processor core comprises a three-stage instruction pipeline with fetch, decode, and execute stages. the fetcher provides an instruction stream to the execution unit (exu). the fetcher speculatively requests up to two instructions from the instruction cache unit (icu), using two prefetch buffers (pfbs) to queue incoming instructions when the exu is busy. if the exu is not busy, instructions from the icu are forwarded directly to the decode stage. to reduce external bus contention, fetching is suspended when the pfbs are full or requests to fill available positions are pending. to save area, the pre-fetch buffers do not have dedicated address registers. because branches are only examined in decode, addresses associated with the pre-fetch buffers can be calculated from the internal decode address register as pre-fetched instructions move into the decode stage. when a branch is predicted taken, the next sequential instruction (nsi), if available, is saved in pfb 0. because a branch predicted taken, but determined to be not taken, does not need to refetch the nsi, instruction fetch latency is reduced. the fetcher uses an instruction bit to predict the direction of a conditional branch. if an unresolved conditional branch is encountered, the fetcher speculatively fetches along the predicted address path until the conditional branch is resolved. if the branch was incorrectly predicted, the fetcher aborts all instruction requests made down the mispredicted path. aborts from the fetcher can propagate through the icu to terminate requests to the biu. the iop 480 cpu exu is optimized for minimal area and power dissipation, yet completes most instructions in one cycle. the exu supports aligned and unaligned storage accesses. hardware multiply and divide is implemented using existing data flow; the apu interface can be used to attach hardware units to accelerate these operations. the exu provides a 32 x 32 register file with two read ports and one write port. although store instructions require three operands, and the load with update instructions require two write ports for single-cycle performance, significant area was saved by the reducing the register ports and the associated dataflow, resulting in 2-cycle loads and stores. when the exu is presented with a load or store instruction, the exu decomposes the instruction into pseudo operations. all load and store operations, including strings and multiples, share the same structure. this simplifies the control logic. the control logic to support unaligned accesses was a natural risc processor core cache data timers: pit, fit, watchdog memory management unit controller cache instruction controller i-cache jtag/debug/trace array d-cache array section 23 iop 480 cpu overview iop 480 cpu organization iop 480 data book r2.0 23-4 ? 2000 plx technology, inc. all rights reserved. extension of the byte steering logic required to handle string operations combined with the similar structure created by the pseudo operations. such support for unaligned storage accesses can eliminate gaps, traditionally found in data structures where data must be aligned, to reduce system memory size. an adjunct register improves the performance of string and unaligned storage accesses, and enables the data cache unit (dcu) to handle 1-, 2-, 3-, or 4-byte requests. the 1-, 2-, and 3-byte requests allow the exu to align to an lword boundary in one transfer. once on an lword boundary, lword requests are made until the byte count is exhausted, or until the transfer is completed by a 1-, 2-, or 3-byte transfer. the adjunct register collects the unaligned data for load/store operations to allow lword accesses to be made to the dcu. the exu uses one carry-skip adder for all arithmetic operations, including multiply/divide, and effective address calculation. the adjunct register stores the multiplier and dividend for multiply and divide operations. 23.4.2 instruction and data cache controllers the iop 480 cpu core provides an instruction cache unit (icu) and a data cache unit (dcu) that allow concurrent accesses and minimize pipeline stalls. both cache units are two-way set associative, use a 16-byte line size, and provide array built-in self test (abist) for manufacturing. the instruction set provides a rich assortment of cache control instructions, including instructions to read tag information and data arrays. see section 25, ? iop 480 cpu cache operations, ? for detailed information about the icu and dcu. the cache units, optimized for minimal size and power consumption, maintain high performance. 23.4.2.1 instruction cache unit (icu) the icu provides one instruction per cycle to the exu over a 32-bit bus. a line buffer (built into the output of the array for manufacturing test) enables the icu to be accessed only once for every four instructions, to reduce power consumption by the array. the icu can forward any or all of the four lwords of a line fill to the exu to minimize pipeline stalls caused by cache misses. the icu aborts speculative fetches abandoned by the exu, eliminating unnecessary line fills and enabling the icu to handle the next exu fetch. aborting abandoned requests also eliminates unnecessary external bus activity to increase external bus utilization. cache line locking can completely eliminate icu misses in critical code. cache line locking can be performed line by line, and is controlled by the cache debug control register (cdbcr) and powerpc 4xx instructions. 23.4.2.2 data cache unit (dcu) the dcu transfers one, two, three, or four bytes per cycle, depending on the number of byte enables presented by the cpu. the dcu contains a single- element command and store data queue to reduce pipeline stalls; this queue enables the dcu to independently process load/store and cache control instructions. dynamic plb request prioritization reduces pipeline stalls even further. when the dcu is busy with a low-priority request while a subsequent storage operation requested by the cpu is stalled, the dcu automatically increases the priority of the current request to the plb. the dcu uses a two-line flush queue to minimize pipeline stalls caused by cache misses. line flushes are postponed until after a line fill is completed. registers comprise the first position of the flush queue; the line buffer built into the output of the array for manufacturing test serves as the second position of the flush queue. pipeline stalls are further reduced by forwarding the requested lword to the cpu during the line fill. single-queued flushes are non-blocking. when a flush operation is pending, the dcu can continue to access the array to determine subsequent load or store hits. under these conditions, load hits can occur concurrently with store hits to write-back memory without stalling the pipeline. requests abandoned by the cpu can also be aborted by the cache controller. cache line locking can completely eliminate dcu line misses in critical data. cache line locking can be performed line by line, and is controlled by the cdbcr and iop 480 cpu instructions. section 23 iop 480 cpu organization iop 480 cpu overview iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 23-5 section 23 ? cpu overview the dcu provides two additional features that allow the programmer to tailor its performance for a given application. the dcu can function in write-back or write-through mode, as controlled by the data cache write-thru register (dcwr) or the translation look- aside buffer (tlb); performance of the cache controller can be tuned for a balance of performance and memory coherency. write-on-allocate, controlled by the cdbcr[woa] field, can inhibit line fills caused by a store miss to further reduce potential pipeline stalls and unwanted external bus traffic. 23.4.3 timers the iop 480 cpu contains a time base and three timers: programmable interval timer (pit) fixed interval timer (fit) watchdog timer the time base is a 64-bit counter incremented either by an internal signal equal to the cpu clock rate or by a separate external timer clock signal. no interrupts are generated when the time base rolls over. the pit is a 32-bit register that is decremented at the same rate as the time base is incremented. the user loads the pit register with a value to create the desired delay. when the register is decremented to zeros, the timer stops decrementing, a bit is set in the timer status register (tsr), and a pit interrupt is generated. optionally, the pit can be programmed to reload automatically the last value written to the pit register, after which the pit begins decrementing again.the timer control register (tcr) contains the interrupt enable for the pit interrupt. the fit generates periodic interrupts based on selected bits in the time base. users can select one of four intervals for the timer period by setting the appropriate bits in the tcr. when the selected bit in the time base changes from 0 to 1, a bit is set in the tsr and a fit interrupt is generated. the fit interrupt enable is contained in the tcr. the watchdog timer generates a periodic interrupt based on selected bits in the time base. users can select one of four time periods for the interval and the type of reset generated if the watchdog timer expires twice without an intervening clear from software. 23.4.4 memory management unit (mmu) the iop 480 cpu has a 4-gb address space, which is presented as a flat address space. the iop 480 cpu mmu provides address translation, protection functions, and storage attribute control for embedded applications. the mmu supports demand paged virtual memory and other management schemes that require precise control of logical-to- physical address mapping and flexible memory protection. working with appropriate system level software, the mmu provides the following functions: translation of the 4-gb logical address space into physical addresses independent enabling of instruction and data translation/protection page level access control using the translation mechanism software control of page replacement strategy additional control over protection using zones storage attributes for cache policy and speculative memory access control the mmu can be disabled under software control. if the mmu is not used, the iop 480 cpu provides other storage control mechanisms. the translation lookaside buffer (tlb) is the hardware resource that controls translation and protection. it consists of 64 entries, each specifying a page to be translated. the tlb is fully associative; a given page entry can be placed anywhere in the tlb. the translation function of the mmu occurs pre-cache. cache tags and indexing use physical addresses. software manages the establishment and replacement of tlb entries. this gives system software significant flexibility in implementing a custom page replacement strategy. for example, to reduce tlb thrashing or translation delays, software can reserve several tlb entries in the tlb for globally accessible static mappings. the instruction set provides several instructions used to manage tlb entries. these instructions are privileged and require the software to be executing in supervisor state. additional tlb instructions are provided to move tlb entry fields to and from gprs. section 23 iop 480 cpu overview iop 480 cpu organization iop 480 data book r2.0 23-6 ? 2000 plx technology, inc. all rights reserved. the mmu divides logical storage into pages. eight page sizes (1 kb, 4 kb, 16 kb, 64 kb, 256 kb, 1 mb, 4 mb, 16 mb) are simultaneously supported, such that, at any given time, the tlb can contain entries for any combination of page sizes. in order for a logical to physical translation to exist, a valid entry for the page containing the logical address must be in the tlb. addresses for which no tlb entry exists cause tlb-miss exceptions. to improve performance, four instruction-side tlb entries are kept in a shadow array. the shadow array helps to avoid tlb contention with load/store operations. hardware manages the replacement and invalidation of shadow-tlb entries; no system software action is required. the shadow array can be thought of as a level 1 instruction-side tlb, with the main tlb serving as a level 2 instruction-side and a level 1 data-side tlb. when address translation is enabled, the translation mechanism provides a basic level of protection. physical addresses not mapped by a page entry are inaccessible when translation is enabled. read access is implied by the existence of the valid entry in the tlb. the ex and wr bits in the tlb entry further define levels of access for the page, by permitting execute and write access, respectively. the zone protection register (zpr) enables the system software to override the tlb access controls. for example, the zpr provides a way to deny read access to application programs. the zpr can be used to classify storage by type; access by type can be changed without manipulating individual tlb entries. when translation is disabled, the iop 480 cpu uses several registers to control the storage attribute settings. 23.4.5 debug the iop 480 cpu debug facilities include debug modes for the various types of debugging used during hardware and software development. also included are debug events that allow developers to control the debug process. debug modes and debug events are controlled using debug registers in the chip. the debug registers are accessed either through software running on the processor, or through the jtag port. the jtag port can also be used for board test. the debug modes, events, controls, and interfaces provide a powerful combination of debug facilities for a complete set of hardware and software development tools such as riscwatch and os open from ibm. 23.4.5.1 development tool support the iop 480 cpu provides powerful debug support for a wide range of hardware and software development tools. the os open real-time operating system debugger is an example of an operating system-aware debugger, implemented using software traps. riscwatch an example of a development tool that uses the external debug mode, debug events, and the jtag port to support hardware and software development and debugging. logic analyzers from hewlett-packard and tektronix provide the iop 480 cpu disassembler with support as well as support for the risctrace feature of riscwatch. 23.4.5.2 debug modes the iop 480 cpu supports two debug modes, internal and external; each mode supports a different type of debug tool used in embedded systems development. internal debug mode supports rom monitors, and external debug mode supports emulators. both modes can be enabled simultaneously. the debug modes are controlled by the debug control register (dbcr). internal debug mode supports accessing architected processor resources, setting hardware and software breakpoints, and monitoring processor status. in internal debug mode, debug events can generate debug exceptions, which can interrupt normal program flow so that monitor software can collect processor status and alter processor resources. internal debug mode relies on exception-handling software, running in the processor, and an external communications path, to debug software problems. this mode is used while the processor is executing instructions and enables debugging of problems in application or operating system code. section 23 iop 480 cpu organization iop 480 cpu overview iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 23-7 section 23 ? cpu overview access to debugger software executing in the processor, while in internal debug mode, is through a communications port on the processor board, such as a serial port. external debug mode, accessed through a jtag port, supports stopping and starting the processor, accessing architected processor resources, setting hardware and software breakpoints, and monitoring processor status. in external debug mode, debug events can architecturally ? freeze ? the processor. while the processor is frozen, normal instruction execution stops, and the architected processor resources can be accessed and altered. external debug mode relies only on internal processor resources to debug system hardware and software problems. this mode can also be used for software development on systems without a control program, or to debug control program code. 23.4.5.3 plb (processor local bus) the plb-compliant interface provides separate 32-bit address and data buses for the instruction and data sides. 23.4.5.4 jtag the iop 480 cpu jtag port is enhanced to support the attachment of a debug tool such as the riscwatch product from ibm microelectronics. through the jtag test access port, a debug workstation can single-step the processor and interrogate internal processor state to facilitate software debugging. the enhancements comply with the ieee 1149.1 specification for vendor-specific extensions, and are therefore compatible with standard jtag hardware for boundary-scan system testing. 23.4.5.5 interrupts the iop 480 cpu provides an interface to an interrupt controller that is logically outside the iop 480 cpu processor core. this controller combines the asynchronous interrupt inputs and presents them to the core as a single interrupt signal. the sources of asynchronous interrupts are external signals, the jtag/debug unit, and any implemented peripherals. 23.4.6 data types the iop 480 cpu operands are bytes, words, or lwords. multiple words or strings of bytes can be transferred using the load/store multiple and load/store string instructions. data is represented in twos complement notation or in unsigned fixed-point format. the address of a multi-byte operand is always the lowest memory address occupied by that operand. 23.4.7 register set summary the registers can be grouped into basic categories based on function and access mode ? general purpose registers (gprs), special purpose registers (sprs), the machine state register (msr), the condition register (cr), and, in standard products, device control registers (dcrs). section 29, ? iop 480 cpu register summary, ? provides a register diagram and a register field description table for each register. 23.4.7.1 general purpose registers the iop 480 cpu contains thirty-two 32-bit gprs. the contents of the gprs can be transferred from memory using load instructions and stored to memory using store instructions. gprs, which are specified as operands in many of the iop 480 cpu instructions, can also hold instruction results and contents of other registers. 23.4.7.2 special purpose registers special purpose registers (sprs), which are part of the powerpc architecture, are accessed using the mtspr and mfspr instructions. sprs control the use of the debug facilities, timers, interrupts, storage control attributes, and other architected processor resources. the only sprs that are not privileged for read and write access are the count register (ctr), link register (lr), and fixed point exception register (xer). user-mode programs have read-only access to the time base high user-mode (tbhu) and time base low user-mode (tblu) time base registers. section 23 iop 480 cpu overview iop 480 cpu organization iop 480 data book r2.0 23-8 ? 2000 plx technology, inc. all rights reserved. 23.4.7.3 machine state register the iop 480 cpu contains a 32-bit machine state register (msr). the contents of a gpr can be written to the msr using the mtmsr instruction, and the msr contents can be read into a gpr using the mfmsr instruction. the msr contains fields that control the operation of the iop 480 cpu. 23.4.7.4 condition register the iop 480 cpu contains a 32-bit condition register (cr). these bits are grouped into eight 4-bit fields, cr[cr0] ? cr[cr7]. instructions are provided to perform logical operations on cr fields and bits within fields and to test cr bits within fields. the cr fields, which are set by compare instructions, can be used to control branches. cr[cr0] can be set implicitly by arithmetic instructions. 23.4.7.5 device control registers device control registers (dcrs), which are architecturally outside of the processor core, are accessed using the mtdcr and mfdcr instructions. dcrs are used to control, configure, and hold status for various functional units that are not part of the processor core. although the iop 480 cpu does not contain dcrs, the mtdcr and mfdcr instructions are provided. the mtdcr and mfdcr instructions are privileged, for all dcrs; therefore, all accesses to dcrs are privileged. see section 24.8, ? privileged mode operation, ? on page 24-27. all dcr numbers are reserved , and should not be read nor written, unless they are part of an ibm core+asic implementation. 23.4.8 addressing modes the iop 480 cpu supports the following addressing modes to allow efficient retrieval and storage of data in memory: base plus displacement addressing indexed addressing base plus displacement addressing and indexed addressing, with update in the base plus displacement addressing mode, an effective address (ea) is formed by adding a displacement to a base address contained in a gpr (or to an implied base of 0). the displacement is an immediate field in an instruction. in the indexed addressing mode, the ea is formed by adding an index contained in a gpr to a base address contained in a gpr (or to an implied base of 0). the base plus displacement and the indexed addressing modes also have a ? with update ? mode. in ? with update ? mode, the effective address calculated for the current operation is saved in the base gpr, and can be used as the base in the next operation. the ? with update ? mode relieves the processor from repeatedly loading a gpr with an address for each piece of data, regardless of the proximity of the data in memory. iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-1 section 24 ? cpu pgmg model 24 iop 480 cpu programming model the programming model of the iop 480 cpu embedded controller describes how the following features and operations appear to programmers: memory organization and addressing registers data types and alignment byte ordering instruction processing branching control speculative accesses privileged mode operation synchronization instruction set 24.1 memory organization and addressing the powerpc architecture defines a 32-bit, 4 gb flat address space for instructions and data. the user ? s manuals for standard products containing the iop 480 cpu describe their memory organizations and physical address maps. 24.1.1 storage attributes powerpc architecture defines storage attributes that control data and instruction accesses. storage attributes are provided to control cache write-through policy (the w storage attribute), cacheability (the i storage attribute), memory coherency in multiprocessor environments (the m storage attribute), and guarding against speculative memory accesses (the g storage attribute). the ibm powerpc embedded environment defines additional storage attributes for storage compression (the k storage attribute) and byte ordering (the e storage attribute). the iop 480 cpu provides control mechanisms for the wigke attributes. because the iop 480 cpu does not provide hardware support for multiprocessor environments, the m storage attribute, when present, has no effect. when the iop 480 cpu operates in virtual mode (address translation is enabled), each storage attribute is controlled by the wigek fields in the tlb entry for each memory page. (an m field is present but ignored.) the size of memory pages, and hence the size of storage attribute control regions, can be set to 1 kb, 4 kb, 16 kb, 64 kb, 256 kb, 1 mb, 4 mb, or 16 mb. multiple sizes can be in effect simultaneously on different pages. when the iop 480 cpu operates in real mode (address translation is disabled), the storage attribute control registers control the storage attributes. these registers are: data cache write-thru register (dcwr) data cache cacheability register (dccr) instruction cache cacheability register (iccr) storage guarded register (sgr) storage compression register (skr) storage little-endian register (sler) section 29, ? iop 480 cpu register summary, ? contains bit descriptions for these registers. when the iop 480 cpu operates in virtual mode (address translation is enabled), the storage attribute control registers are ignored. each storage attribute control register contains 32 bits; each bit controls one of thirty-two 128 mb storage attribute control regions. bit 0 of each register controls the lowest-order region, with ascending bits controlling ascending regions in memory. each region is selected by address bits a[0:4]. the storage attributes in each storage attribute region are set independently. 24.2 registers some of the more commonly-used registers are described in this section. other registers are covered in their respective topic sections ( for example , the cache registers are described in section 25, ? iop 480 cpu cache operations ? ). all registers are summarized in section 29, ? iop 480 cpu register summary. ? section 24 iop 480 cpu programming model registers iop 480 data book r2.0 24-2 ? 2000 plx technology, inc. all rights reserved. all registers in the iop 480 cpu are 32-bit registers. the registers are grouped into categories, based on access mode: general purpose registers (gprs), special purpose registers (sprs), the time base, the machine state register (msr), the condition register (cr), and, in standard products, device control registers (dcrs). for all registers with fields marked as reserved , the reserved fields should be written as 0 and read as undefined . that is, when writing to a register with a reserved field, write a 0 to the reserved field. when reading from a register with a reserved field, ignore that field. a good coding practice is to perform the initial write to a register with reserved fields as described, and to perform all subsequent writes to the register using a read-modify-write strategy: read the register, use logical instructions to alter defined fields, leaving reserved fields unmodified, and write the register. 24.2.1 general purpose registers the iop 480 cpu contains 32 general purpose registers (gprs); each contains 32 bits. data from memory can be loaded into gprs using load instructions; the contents of gprs can be stored in memory using store instructions. most integer instructions reference gprs. see register 24-1 for gpr numbering. 24.2.2 special purpose registers special purpose registers (sprs), which are part of the powerpc architecture and the ibm powerpc embedded environment, are accessed using the mtspr and mfspr instructions. sprs control the use of the debug facilities, timers, interrupts, storage control attributes, and other architected processor resources. table 24-1 shows the mnemonic, name, and number for each spr. table 24-1 also lists the iop 480 cpu sprs by function and points to the pages where the sprs are described more fully. register 24-1. general purpose register (r0-r31) 0:31 gpr data section 24 registers iop 480 cpu programming model iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-3 section 24 ? cpu pgmg model table 24-1. iop 480 cpu sprs function register access page branch control ctr user 24-4 lr user 24-4 debug cdbcr privileged 25-7 dac1 privileged 26-7 dbcr privileged 26-3 dbsr privileged 26-5 iac1 privileged 26-8 icdbdr privileged 25-9 fixed-point exception xer user 24-5 general purpose sprg0 sprg1 sprg2 sprg3 privileged 24-6 interrupts and exceptions dear privileged 11-19 esr privileged 11-17 evpr privileged 11-17 srr0 srr1 privileged 11-15 srr2 srr3 privileged 11-15 processor version pvr privileged, read-only 24-6 storage attributes dccr privileged 27-13 dcwr privileged iccr privileged sgr privileged skr privileged sler privileged timer facilities tbhi tblo privileged 11-30 tbhu tblu user read-only 11-30 pit privileged 11-26 tcr privileged 11-36 tsr privileged 11-35 section 24 iop 480 cpu programming model registers iop 480 data book r2.0 24-4 ? 2000 plx technology, inc. all rights reserved. except for the link register (lr), the count register (ctr), the fixed-point exception register (xer), and the time base high user-mode (tbhu) and thetime base low user-mode (tblu), all sprs are privileged. see section 24.8.3, ? privileged sprs, ? on page 24-28. the processor version register (pvr) is read-only. 24.2.2.1 count register (ctr) the ctr is written from a gpr using the mtspr instruction. the ctr contents can be used as a loop count that is decremented and tested by some branch instructions. this usage does not incur any performance penalty; the branches execute in the normal branch instruction execution time. alternatively, the ctr contents can specify a target address for the bcctr instruction, enabling indirectly-addressed branching to any address. the ctr is available to user programs. register 24-2 lists the ctr bits. 24.2.2.2 link register (lr) the lr is written from a gpr using the mtspr instruction or branch instructions that have the lk bit set to 1. such branch instructions load the lr with the address of the instruction following the branch instruction (4 + address of the branch instruction). thus, the lr contents can be a return address for a subroutine which was entered using the branch. the lr contents can be used as a target address for the bclr instruction. this allows indirectly-addressed branching to any address. when the lr contents represent an instruction address, lr 30:31 are assumed to be zero, because all instructions must be lword-aligned. however, when lr is written using mtspr and then read using mfspr , all 32 bits are returned. the lr is available to user programs. register 24-3 lists the lr bits. register 24-2. count register (ctr) 0:31 count used as count for branch conditional with decrement instructions, or as address for branch-to-counter instructions. register 24-3. link register (lr) 0:31 link registers contents if (lr) represents an instruction address, lr 30:31 should be zero. section 24 registers iop 480 cpu programming model iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-5 section 24 ? cpu pgmg model 24.2.2.3 fixed point exception register (xer) the xer records overflow and carry conditions from arithmetic operations. the summary overflow (so) field does not necessarily indicate that an overflow occurred on the most recent arithmetic operation, but that one occurred previously sometime since the last clearing of the xer. xer[so] can be set to zero only by using the mtspr instruction or the mcrxr instruction. the tbc field can be written, using mtspr , with a byte count for load/store string instructions. the xer is available to user programs. several special cases are associated with the use of the xer bits, as documented in the sections that follow. register 24-4 illustrates the xer bits. register 24-4. fixed point exception register (xer) 0 so summary overflow 0 no overflow has occurred. 1 overflow has occurred. can be set by mtspr or using arithmetic instructions with the ? oe ? option (see table 24-2); can be reset by mtspr or by mcrxr . 1ov overflow 0 no overflow has occurred. 0 overflow has occurred. can be set by mtspr or arithmetic instructions with the ? oe ? option (see table 24-2); can be reset by mtspr , by mcrxr , or by arithmetic instructions with the ? oe ? option. 2ca carry 0 carry has not occurred. 1 carry has occurred. can be set by mtspr or arithmetic instructions that update the ca field (see table 24-2); can be reset by mtspr , by mcrxr , or by arithmetic instructions that update the ca field. 3:24 reserved table 24-2. xer-updating arithmetic instructions update xer[ca] update xer[ov] set xer[so] addc addc. addco addco. adde adde. addeo addeo. addic addic. addme addme. addmeo addmeo. addze addze. addzeo addzeo. subfc subfc. subfco subfco. subfe subfe. subfeo subfeo. subfic subfme subfme. subfmeo subfmeo. subfze subfze. subfzeo subfzeo. addo addo. addco addco. addeo addeo. addmeo addmeo. addzeo addzeo. divwo divwo. divwuo divwuo. mullwo mullwo. nego nego. subfo subfo. subfco subfco. subfeo subfeo. subfmeo subfmeo. subfzeo subfzeo. 012 25 31 3 24 so ca tbc ov section 24 iop 480 cpu programming model registers iop 480 data book r2.0 24-6 ? 2000 plx technology, inc. all rights reserved. 24.2.2.3.1 xer[so] summary overflow; set to 1 when an instruction causes xer[ov] to be set to 1, except for mtspr (xer), which sets xer[so,ov] to the value of bit positions 0 and 1 in the source register, respectively. once set, xer[so] is not reset until an mtspr (xer) is executed with data that explicitly puts a 0 in the so bit, or until an mcrxr instruction is executed. 24.2.2.3.2 xer[ov] overflow; set to indicate whether or not an instruction that updates xer[ov] produces a result that ? overflows ? the 32-bit target register. xer[ov] = 1 indicates overflow. for arithmetic operations, this occurs when an operation has a carry-in to the most- significant bit of the instruction result that does not equal the carry-out of the most-significant bit (that is, the exclusive-or of the carry-in and the carry-out is 1). the following instructions set xer[ov] differently.the specific behavior is indicated in the instruction descriptions. move instructions mcrxr , mtspr (xer) multiply and divide instructions mullwo , mullwo. , divwo , divwo. , divwuo, divwuo. 24.2.2.3.3 xer[ca] carry; set to indicate whether or not an instruction that updates xer[ca] produces a result that has a carry-out of the most-significant bit. xer[ca] = 1 indicates a carry. the following instructions set xer[ca] differently. the specific behavior is indicated in the instruction descriptions. move instructions mcrxr , mtspr (xer) shift-algebraic operations sraw , srawi 24.2.2.3.4 xer[tbc] transfer byte count. this field provides a byte count for the lswx and stswx instructions. this field is updated by mtspr (xer). 24.2.2.4 special purpose register general (sprg0-sprg3) these four registers are provided as temporary storage locations. for example , a supervisor routine might save the contents of a gpr to an sprg, and later restore the gpr from it. this is faster than the standard save/restore to a memory location. these registers are written to using the mtspr instruction and read from using the mfspr instruction. access to the sprgs is privileged. see section 24.8.3, ? privileged sprs, ? on page 24-28 for more information. see register 24-5 for numbering. 24.2.2.5 processor version register (pvr) pvr is a read-only register that identifies the processor by version and revision numbers. software can use features that depend upon an exact identification of the target processor. such software can examine the pvr to select appropriate features dynamically. the 16-bit version number (comprised of the fam and mem fields) is assigned by the powerpc architecture process. the 16-bit revision number (comprised of the core and chip fields) is assigned by the chip implementer. access to the pvr is privileged. see section 24.8.3, ? privileged sprs, ? on page 24-28 for more information. register 24-6 illustrates the pvr bits. section 24 registers iop 480 cpu programming model iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-7 section 24 ? cpu pgmg model 24.2.3 condition register (cr) the condition register (cr) contains eight 4-bit fields (cr0 ? cr7), as shown in register 24-7. the cr reflects the results of some operations (as indicated in the instruction descriptions in section 28, ? iop 480 cpu instruction set ? ). the cr supports condition testing and conditional branching. fields of the cr can be set in any of the following ways: specified fields can be set by writing to the cr from a gpr ( mtcrf instruction). a specified field can be set by writing to the field from another cr field ( mcrf instruction) or from the xer ( mcrxr instruction). cr[cr0] can be set as the implicit result of various fixed-point instructions. the bits in a specified field can be set as the result of a compare instruction. additional instructions perform logical operations on one or more bits in a cr field (the cr-logical instructions); other instructions (the branch conditional instructions) test the bits in a cr field. if a cr field is set by a compare instruction, the bits in the selected field are set as described in section 24.2.3.1, ? cr fields after compare instructions, ? on page 24-8. further, cr[cr0] field is altered implicitly by numerous instructions and the interpretation of cr[cr0] is discussed further in section 24.2.3.1, ? cr fields after compare instructions, ? on page 24-8. the cr is non-privileged. see section 24.8.3, ? privileged sprs, ? on page 24-28 for more information. register 24-7 illustrates the cr bits. register 24-5. special purpose register general (sprg0-sprg3) 0:31 general data privileged user-specified; no hardware usage. register 24-6. processor version register (pvr) 0:11 fam processor family. identifies a powerpc family, such as 4xx or 6xx. 0x002 for the 4xx family. 12:15 pcfn processor core function. identifies a specific processor core implementation. 2 for ppc401b2. 16:20 pcrv processor core revision. identifies a revision of the processor core defined by the pfn field. 21:27 afn asic function. an assigned identifier for an asic containing a powerpc 400 series processor core. 28:31 arv asic revision. an assigned identifier for a revision of the asic defined by the afn field. 015162731 afn fam arv 11 12 pcfn pcrv 20 21 28 section 24 iop 480 cpu programming model registers iop 480 data book r2.0 24-8 ? 2000 plx technology, inc. all rights reserved. 24.2.3.1 cr fields after compare instructions compare instructions compare the values of two 32-bit numbers. the two types of compare instructions, arithmetic and logical , are distinguished by the interpretation given to the 32-bit numbers. for arithmetic compares, the numbers are considered to be signed, where 31 bits are significant; the most- significant bit is a sign bit. for logical compares, the numbers are considered to be unsigned (all 32 bits are significant; there is no sign bit). as an example, consider the comparison of 0 with 0xffff ffff. in an arithmetic compare, 0 is larger; in a logical compare, 0xffff ffff is larger. a compare instruction can direct its results to any cr field. the bf field (bits 6:8) of the instruction specifies the cr field. the first data operand of a compare instruction specifies a gpr. the second data operand specifies another gpr, or immediate data derived from the im field (bits 16:31) of the immediate instruction form. the contents of the gpr specified by the first data operand are compared with the contents of the gpr specified by the second data operand (or with the immediate data). see descriptions of the compare instructions for precise details. after a compare, the specified cr field is interpreted as follows: lt (bit 0) the first operand is less than the second operand. gt (bit 1) the first operand is greater than the second operand. eq (bit 2) the first operand is equal to the second operand. so (bit 3) summary overflow; a copy of xer[so]. 24.2.3.2 cr0 field after the execution of compare instructions with bf=0, the cr[cr0] is interpreted as described in section 24.2.3.1, ? cr fields after compare instructions, ? above. the ? dot ? forms of arithmetic and logical instructions also alter cr[cr0]. after most fixed-point instructions that update cr[cr0], the bits of cr0 are interpreted as follows: lt (bit 0) less than 0; set if the most-significant bit of the 32-bit result is 1. gt (bit 1) greater than 0; set if the 32-bit result is non-zero and the most-significant bit of the result is 0. eq (bit 2) equal to zero; set if the 32-bit result is 0. so (bit 3) summary overflow; a copy of xer[so] at instruction completion. register 24-7. condition register (cr) 0:3 cr0 condition register field 0 cr[crn] 0:3 indicate less than, greater than, equal to, and summary overflow, respectively. 4:7 cr1 condition register field 1 see the description of cr[cr0]. 8:11 cr2 condition register field 2 see the description of cr[cr0]. 12:15 cr3 condition register field 3 see the description of cr[cr0]. 16:19 cr4 condition register field 4 see the description of cr[cr0]. 20:23 cr5 condition register field 5 see the description of cr[cr0]. 24:27 cr6 condition register field 6 see the description of cr[cr0]. 28:31 cr7 condition register field 7 see the description of cr[cr0]. cr2 034781112 16 20 31 cr0 cr3 cr4 15 19 cr1 23 28 27 24 cr5 cr6 cr7 section 24 registers iop 480 cpu programming model iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-9 section 24 ? cpu pgmg model the cr[cr0] lt, gt, eq subfields are set as the result of an algebraic comparison of the instruction result to 0, regardless of the type of instruction that sets cr[cr0]. if the instruction result is 0, the eq subfield is set to 1. if the result is not 0, whether the lt subfield or the gt subfield is set depends on the value of the most-significant bit of the instruction result. when updating cr[cr0], the most significant bit of an instruction result is considered a sign bit, even for instructions that produce results that are not usually thought of as signed. for example , logical instructions such as and. , or. , and nor. update cr[cr0] lt, gt, eq using such an arithmetic comparison to 0, although the result of such a logical operation is often not actually an arithmetic result. note: if an arithmetic overflow occurs, the ? sign ? of an instruction result indicated by cr[cr0] lt, gt, eq might not represent the ? true ? (infinitely precise) algebraic result of the instruction that set cr0. for example, if an add . instruction adds two large positive numbers and the magnitude of the result cannot be represented as a twos-complement number in a 32-bit register, an overflow occurs and cr[cr0] lt, so are set, although the infinitely precise result of the add is positive. adding the largest 32-bit twos -complement negative number, 0x8000 0000, to itself results in an arithmetic overflow and 0x0000 0000 is recorded in the target register. cr[cr0] eq, so is set, indicating a result of 0, but the infinitely precise result is negative. the cr[cr0] so subfield is a copy of xer[so]. instructions that do not alter the xer[so] bit cannot cause an overflow, but even for these instructions cr[cr0] so is a copy of xer[so]. some instructions set cr[cr0] differently or do not specifically set any of the subfields. these instructions include: compare instructions cmp , cmpi , cmpl , cmpli cr logical instructions crand , crandc , creqv , crnand , crnor , cror , crorc , crxor , mcrf move cr instructions mtcrf , mcrxr stwcx the instruction descriptions provide detailed information about how the listed instructions alter cr[cr0]. 24.2.4 time base the iop 480 cpu implements a 64-bit time base. the time base, which increments once during each period of the time base clock, provides a time reference. the time base is accessed using the 32-bit registers tblo and tbhi. software access to the time base is through the mfspr and mtspr instructions. access to the time base registers tbhi and tblo is privileged. user-mode read-only access to the time base is provided by reading from different spr numbers. specifically, read-only access to tbhi is accomplished by reading tbhu, and read-only access to tblo is accomplished by reading tblu. both tbhu and tblu are read using mfspr instructions. an mtspr to these registers is boundedly undefined. the time base differs from the time base described in the powerpc architecture. see section 11.7.18.1, ? time base, ? on page 11-30 for detailed differences between the iop 480 cpu time base and the time base described in powerpc architecture. 24.2.5 machine state register (msr) the machine state register (msr) controls important chip functions, such as the enabling or disabling of interrupts and debugging exceptions. the msr can be written from a gpr using the mtmsr instruction. the contents of the msr can be written into a gpr using the mfmsr instruction. the msr[ee] (external interrupt enable) bit may be set/cleared atomically using the wrtee or wrteei instructions. the msr contents are automatically saved, altered, and restored by the interrupt-handling mechanism. see section 11.7.3, ? general exception handling registers, ? on page 11-13. register 24-8 illustrates the msr bits. section 24 iop 480 cpu programming model registers iop 480 data book r2.0 24-10 ? 2000 plx technology, inc. all rights reserved. register 24-8. machine state register (msr) 0:10 reserved 11 ape auxiliary processor exception enable 0 auxiliary processor exception disabled. 1 auxiliary processor exception enabled. 12 apa auxiliary processor available 0 auxiliary processor not available. 1 auxiliary processor available. 13 we wait state enable 0 the processor is not in the wait state. 1 the processor enters the wait state until an exception is taken, or the iop 480 cpu is reset, or an external debug tool clears we. 14 ce critical interrupt enable 0 critical interrupts are disabled. 1 critical interrupts are enabled. ce controls the critical interrupt input and watchdog timer first timeout interrupts. 15 ile interrupt little endian 0 interrupt handlers execute in big endian mode. 1 interrupt handlers execute in powerpc little endian mode. msr(ile) is copied to msr(le) when an interrupt is taken. 16 ee external interrupt enable 0 asynchronous exceptions are disabled. 1 asynchronous exceptions are enabled. ee controls the non-critical external interrupt input, programmable interval timer, and fixed interval timer interrupts. 17 pr problem state 0 supervisor state (all instructions allowed) 1 problem state (some instructions not allowed) 18 reserved 19 me machine check enable 0 machine check exceptions are disabled 1 machine check exceptions are enabled. 20:21 reserved 22 de debug exception enable 0 debug exceptions are disabled. 1 debug exceptions are enabled. 23:25 reserved 26 ir instruction relocate 0 instruction address translation is disabled. 1 instruction address translation is enabled. if tie_cpummuen is 0, reading or writing this bit has no effect. 27 dr data relocate 0 data address translation is disabled. 1 data address translation is enabled. if tie_cpummuen is 0, reading or writing this bit has no effect. 28:30 reserved 31 le little endian 0 processor executes in big endian mode. 1 processor executes in powerpc little endian mode. 13 14 16 19 22 28 29 01215 17 18 20 21 23 27 30 31 we pr de ce ee me ile le 26 25 ir dr 28 11 apa ape 10 section 24 data types and alignment iop 480 cpu programming model iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-11 section 24 ? cpu pgmg model 24.2.6 device control registers device control registers (dcrs), on-chip registers that exist architecturally outside the processor core, are not part of the ibm powerpc embedded environment. the embedded environment simply defines the existence of a dcr address space and the instructions that access the dcrs, but does not define any dcrs. the instructions that access the dcrs are mtdcr (move to device control register) and mfdcr (move from device control register). 24.3 data types and alignment the iop 480 cpu data types consist of bytes (8 bits), words (16 bits), lwords (32 bits), and strings (one or more bytes containing character data). figure 24-1 shows the byte, word, and lword data types and their bit and byte definitions. data is represented in twos complement notation or in an unsigned integer format; data representation is independent of alignment issues. the address of an a data object is always the lowest address of any byte comprising the object. all instructions are lwords, and are lword-aligned (the byte address is divisible by 4). 24.3.1 alignment for storage reference and cache control instructions the storage reference instructions (loads and stores; see table 24-11 on page 24-32) move data to and from storage. the data cache control instructions (see table 24-17 on page 24-34) control the contents and operation of the data cache unit (dcu). both types of instructions form an effective address (ea). the method of calculating the ea for the storage reference and cache control instructions is detailed in the description of those instructions. see section 28, ? iop 480 cpu instruction set, ? for more information. cache control instructions ignore the four least significant bits in the ea; no alignment restrictions exist in the dcu because of eas. however, storage control attributes for a storage region can cause alignment exceptions. specifically, when data translation is disabled and a dcbz instruction references a region that is non-cacheable or for which write-through caching is enabled, an alignment exception is taken. such exceptions result from the storage control attributes, not from ea alignment. alignment requirements for the eas of the storage reference instructions and the dcread cache control instruction depends on the instruction and the endian mode of the iop 480 cpu (see section 24.4, ? byte ordering, ? on page 24-13 for information about endian operation). table 24-3 on page 24-12, summarizes the instructions that cause alignment exceptions. the data targets of instructions are of types that depend upon the instruction. the load/store instructions have the following ? natural ? alignments: load/store lword instructions have lword targets, lword-aligned load/ store word instructions have word targets, word-aligned load/store byte instructions have byte targets, byte-aligned (that is, any alignment) note: the iop 480 cpu implementation handles misalignments within and across lword boundaries. misalignments are addresses that are not naturally aligned on data type boundaries. an address not divisible by four is misaligned with respect to lword instructions. an address not divisible by two is misaligned with respect to word instructions. byte word bit figure 24-1. iop 480 cpu data types 3 2 1 0 0 31 byte 0 15 1 0 0 0 7 lword section 24 iop 480 cpu programming model data types and alignment iop 480 data book r2.0 24-12 ? 2000 plx technology, inc. all rights reserved. 24.3.2 alignment and endian operation the iop 480 cpu is operating as a big endian processor (msr[le] = 0), and ea misalignments do not cause alignment exceptions except as summarized in table 24-3. 24.3.3 instructions causing alignment exceptions summary table 24-3 summarizes the instructions that cause alignment exceptions and the conditions under which the alignment exceptions occur. table 24-3. alignment exception summary iop 480 cpu msr instructions causing alignment exceptions conditions msr[le] = 0 dcbz ea in non-cacheable or write-through storage dcread, lwarx, stwcx. ea not lword-aligned msr[le] = 1 dcbz ea in non-cacheable or write-through storage lha, lhau, lhaux, lhax, lhbrx, lhz, lhzu, lhzux, lhzx, sth, sthbrx, sthu, sthux, sthx ea not word-aligned dcread, lwarx, lwbrx, lwz, lwzu, lwzux, lwzx, stw, stwbrx, stwcx., stwu, stwux, stwx ea not lword-aligned lmw, lswi, lswx, stmw, stswi, stswx, stswcx. always section 24 byte ordering iop 480 cpu programming model iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-13 section 24 ? cpu pgmg model 24.4 byte ordering if scalars (individual data items and instructions) were indivisible, there would be no such concept as ? byte ordering. ? it is meaningless to consider the order of bits or groups of bits within the smallest addressable unit of storage; nothing can be observed about such order. only when scalars, which the programmer and processor regard as indivisible quantities, can comprise more than one addressable unit of storage does the question of order arise. for a machine in which the smallest addressable unit of storage is the 64-bit double lword, there is no question of the ordering of bytes within double lwords. all transfers of individual scalars between registers and storage are of double lwords, and the address of the byte containing the high-order eight bits of a scalar is no different from the address of a byte containing any other part of the scalar. for powerpc architecture, as for most computer architectures currently implemented, the smallest addressable unit of storage is the 8-bit byte. many scalars are words, lwords, or double lwords, which consist of groups of bytes. when an lword-length scalar is moved from a register to storage, the scalar occupies four consecutive byte addresses. it thus becomes meaningful to discuss the order of the byte addresses with respect to the value of the scalar: which byte contains the highest-order eight bits of the scalar, which byte contains the next-highest-order eight bits, and so forth. given a scalar that contains multiple bytes, the choice of byte ordering is essentially arbitrary. there are 4! = 24 ways to specify the ordering of four bytes within an lword, but only two of these orderings are sensible: the ordering that assigns the lowest address to the highest-order ( ? leftmost ? ) eight bits of the scalar, the next sequential address to the next-highest-order eight bits, and so forth. this ordering is called big endian because the ? big end ? of the scalar, considered as a binary number, comes first in storage. ibm risc system/6000, ibm system/390, and motorola 680x0 are examples of computers using this byte ordering. the ordering that assigns the lowest address to the lowest-order ( ? rightmost ? ) eight bits of the scalar, the next sequential address to the next-lowest-order eight bits, and so forth. this ordering is called little endian because the ? little end ? of the scalar, considered as a binary number, comes first in storage. dec vax and intel x86 are examples of computers using this byte ordering. 24.4.1 structure mapping examples the following c language structure s contains an assortment of scalars and a character string. the comments show the value assumed to be in each structure element; these values show how the bytes comprising each structure element are mapped into storage. struct { int a; /* 0x1112_1314 lword */ long long b;/* 0x2122_2324_2526_2728 double lword */ char *c; /* 0x3132_3334 lword */ char d[7];/* 'a','b','c','d','e','f','g' array of bytes */ short e; /* 0x5152 word */ int f; /* 0x6162_6364 lword */ } s; c structure mapping rules permit the use of padding (skipped bytes) to align scalars on desirable boundaries. the structure mapping examples show each scalar aligned at its natural boundary. this alignment introduces padding of four bytes between a and b , one byte between d and e , and two bytes between e and f . the same amount of padding is present in both big endian and little endian mappings. section 24 iop 480 cpu programming model byte ordering iop 480 data book r2.0 24-14 ? 2000 plx technology, inc. all rights reserved. 24.4.1.1 big-endian mapping the big endian mapping of structure s follows. the data is highlighted in the structure mappings. addresses, in hexadecimal, are below the data stored at the address. the contents of each byte, as defined in structure s , is shown as a (hexadecimal) number or character (for the string elements). 24.4.2 powerpc byte ordering by default, the powerpc architecture is big endian. this book describes the processor as if it operated only in a big endian fashion. iop 480 bus control mechanisms support little endian operation. subsequent sections explain these mechanisms in more detail. 24.4.3 powerpc endian mode powerpc endian mode is useful for system environments in which some processes and their associated data structures are written as little endian, and other processes are written as big endian. the powerpc endian mode mechanism handles such bi-endian systems and manages communications and data sharing between processes running in the system. however, because of how powerpc endian mode operates, it does not provide for direct processor connections to little endian hardware, nor for operating the iop 480 cpu in a hardware system environment that is connected in a little endian manner. instead, for such environments, one should use the endian (e) storage attribute described in section 24.4.4, ? endian storage attribute, ? on page 24-18. when the iop 480 cpu operates with the powerpc endian mode set to little endian, instructions and data in memory appear , from the programmer's point of view, to be arranged in little endian format. however, instructions and data in memory are arranged in a unique order that is neither big endian nor little endian. in addition, the processor manipulates the low-order address bits used for all instruction fetches and data references such that, when combined with the unique ordering of the bytes in memory, the instructions and data appear to the executing program to be arranged in true little endian order. section 24.4.3.1, ? byte ordering in powerpc little endian mode ? below describes this unique byte arrangement and the address manipulation in detail, while section 24.4.3.2, ? control of powerpc endian mode ? explains how the powerpc endian mode is controlled. 24.4.3.1 byte ordering in powerpc little endian mode when the processor operates in powerpc little endian mode, bytes, in memory , are rearranged from the order in which they would appear in a true little endian environment. specifically, for each aligned double lword (eight bytes) of memory, the eight bytes are reversed across the double lword. for example , for the aligned double lword at addresses a0 ? a7, the byte at a0 in little endian format is instead placed at a7 for powerpc little endian mode. likewise, the byte from a1 is moved to a6, a2 to a5, a3 to a4, a4 to a3, a5 to a2, a6 to a1, and a7 to a0. this is repeated for the next double lword at addresses a8 ? a15, and so forth. 11 12 13 14 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 21 22 23 24 25 26 27 28 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 31 32 33 34 'a' 'b' 'c' 'd' 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 'e' 'f' 'g' 51 52 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 61 62 63 64 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 section 24 byte ordering iop 480 cpu programming model iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-15 section 24 ? cpu pgmg model structure s (defined in section 24.4.1, ? structure mapping examples, ? on page 24-13) appears in memory as follows after being rearranged as described. this arrangement of bytes is neither big endian nor little endian, but is rather the result of taking the bytes from the little endian mapping and ? swapping ? them byte-for-byte across each double lword. for this unique arrangement of bytes to appear to the executing program as equivalent to a true little endian arrangement, the address of each storage reference (whether for instruction fetches or for data accesses from load and store instructions) must be modified. specifically, the address of each storage access is modified by exclusive-oring the low-order three bits of the address (addresses for instruction fetches are modified as for lword accesses, because all powerpc instructions are lwords). to see how this address modification, combined with the unique ordering of bytes in memory, results in the appearance to the executing program of a true little endian byte arrangement, consider the following example, using the value of the lword a from structure s . if a were stored, in little endian format, to address 00, it would appear as follows: this memory could be accessed using lword, word, or byte accesses in a true little endian system with the following results: for programmers to view memory in powerpc little endian mode as equivalent to memory in a true little endian system, the values observed for each kind of access must match those shown. this example shows how a is arranged in memory when stored, in powerpc little endian mode, to address 0: this lword could then be accessed using lword, word, or byte accesses in powerpc little endian mode with the following results: 11 12 13 14 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 21 22 23 24 25 26 27 28 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 'd' 'c' 'b' 'a' 31 32 33 34 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 51 52 'g' 'f' 'e' 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 61 62 63 64 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 access type address modification byte xor with 0b111 word xor with 0b110 lword xor with 0b100 14 13 12 11 0x00 0x01 0x02 0x03 lword load from address 00 0x1112_1314 word load from address 00 0x1314 word load from address 02 0x1112 byte load from address 00 0x14 byte load from address 01 0x13 byte load from address 02 0x12 byte load from address 03 0x11 11 12 13 14 0x04 0x05 0x06 0x07 lword load from (processor) address 00 converts to (memory) address 04 0x1112_1314 word load from (processor) address 00 converts to (memory) address 06 0x1314 word load from (processor) address 02 converts to (memory) address 04 0x1112 byte load from (processor) address 00 converts to (memory) address 07 0x14 byte load from (processor) address 01 converts to (memory) address 06 0x13 byte load from (processor) address 02 converts to (memory) address 05 0x12 byte load from (processor) address 03 converts to (memory) address 04 0x11 section 24 iop 480 cpu programming model byte ordering iop 480 data book r2.0 24-16 ? 2000 plx technology, inc. all rights reserved. this example shows that a program, running on the iop 480 cpu operating in powerpc little endian mode, views lword a in memory as if it were instead arranged in true little endian format. similar results are obtained for the other members of structure s . it should be recognized that because instructions in powerpc architecture are defined as aligned lwords, their addressing is also affected by endian mode. specifically, each pair of lwords in an aligned double lword of memory are reversed with respect to each other when operating in powerpc little endian mode. so, although a big endian and little endian program may have a sequence of instructions at addresses 00, 04, 08, 12, and so forth, and the executing program requested these instructions in order, the address modification causes the little endian program executing in powerpc little endian mode to receive the instructions from memory in the following order of addresses: 04, 00, 12, 08, and so forth. care must be taken when loading little endian programs into memory to ensure that the instructions are arranged in the proper order. see section 24.4.3.5, ? switching endian modes, ? on page 24-17, for more detailed information. 24.4.3.2 control of powerpc endian mode the selection of the powerpc endian mode is controlled by two bits in the msr: the little endian mode bit (msr[le]) and the interrupt little endian bit (msr[ile]). msr[le] describes the current endian mode. if msr[le] = 1, the processor is executing in powerpc little endian mode. otherwise, the processor executes in big endian mode. when the iop 480 cpu takes an interrupt, the msr contents are saved in either save/restore register 1 (srr1) or save/restore register 3 (srr3), depending on the interrupt type. the content of msr[ile] replaces the content of msr[le]. the iop 480 cpu can switch endian modes in this fashion when entering an interrupt handler. the original value of msr[le] is restored from srr1 or srr3 upon leaving the interrupt handler (using an rfi or rfci instruction as appropriate) and returning to the previously executing program. hence, the iop 480 cpu can also switch endian modes when leaving an interrupt handler. this mode-switching capability enables an operating system written in one endian mode to support application programs written in the other mode. the iop 480 cpu resets to big endian mode, msr[le] = 0 and msr[ile] = 0. 24.4.3.3 addressing in powerpc little endian mode the address modification performed in powerpc little endian mode affects only those addresses that are presented to the storage subsystem (including the caches). specifically, it does not affect the original calculation of addresses, nor the value of addresses saved in registers as part of the semantics of instruction execution. for example , the following address values are calculated independently of endian mode, and are stored in the appropriate registers without modification: the address placed into the lr by a branch with link update instruction, which is equal to the program counter (pc) + 4 the offset in a relative branch instruction, which reflects the difference between the addresses of the branch and target instructions as they appear to the executing program ( not necessarily as they appear in the actual memory arrangement) the address placed into ra by a load/store with update instruction, which is the value computed as described in the instruction description the address saved in system registers, such as srr0, srr2, and the dear, as computed by the executing program and as defined for these registers these examples do not include all addresses that are not affected by the little endian address modification. the cache management instructions ( dcbi , icbi , and others) are unaffected by endian mode, because the addresses used by these instructions refer to an entire cache block (16 bytes) and the low-order four bits of the address are not used. section 24 byte ordering iop 480 cpu programming model iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-17 section 24 ? cpu pgmg model 24.4.3.4 little endian mode alignment requirements the ? trick ? of exclusive or-ing the low-order three bits of the address of an individual scalar does not work unless the scalar is aligned in memory to the size of the scalar. to illustrate, consider the following example of an lword w (containing 0x1112_1314) stored in memory at address 05, and arranged in little endian format: in powerpc little endian mode, lword w would be arranged in memory as follows (remember that the bytes in each aligned double lword are reversed in the format used by powerpc little endian mode): the unaligned lword w spans two double lwords. the two parts of the unaligned lword are not contiguous in memory. applying the address modification to a load lword at address 0x05 results in address 0x01; the load lword from address 0x05 causes the four bytes at addresses 0x01, 0x02, 0x03, and 0x04 to be accessed ? clearly an incorrect result. because of the complexity of dealing with this unusual arrangement of unaligned scalars when operating in powerpc little endian mode, the iop 480 cpu generates alignment exceptions when attempting to execute any of the following instruction types, if the iop 480 cpu is in powerpc little endian mode: unaligned word or lword load/store instruction string or multiple instruction ( lmw , lswi , lswx , stmw , stswi , stswx ) note: although there are other conditions that can result in alignment exceptions, the alignment exceptions caused by those conditions occur regardless of endian mode. see section 11.7.9, ? alignment exception, ? on page 11-24, for more information. 24.4.3.5 switching endian modes because bytes in memory are arranged differently when operating in the different endian modes, care must be taken, when switching modes, to convert programs and data structures to the new mode. the operating system must understand the differences in the two memory formats, and must reorder the bytes in memory, as appropriate, before dispatching a new process that accesses these memory structures in the new endian mode. for example , if a process executing in big endian mode creates a data structure, and a new process executing in little endian mode accesses this data structure, the operating system must reverse the eight bytes within each aligned double lword in the data structure before passing control to the new process. 24.4.3.6 direct memory access in powerpc little endian mode another aspect of the unique arrangement of bytes used by powerpc little endian mode that must be considered is that of access to memory by devices other than the iop 480 cpu. because these other devices, such as a direct memory access (dma) device or another non-powerpc processor, are not likely to handle the special address modifications associated with powerpc little endian mode, they must be aware of the special arrangement of bytes used by iop 480 cpu when they operate in little endian mode. for example , if an i/o device loads a little endian program and data structure from a disk and places it into memory so that the iop 480 cpu can execute the program in little endian mode, the i/o device must reverse the eight bytes in each aligned double lword after reading the data from the disk and before writing it to memory. alternatively, the operating system running on the iop 480 cpu must understand that the program image loaded from the disk was placed into memory in true little endian format, in which case the operating system must rearrange the bytes before executing the program. 14 13 12 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 11 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 12 13 14 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 11 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f section 24 iop 480 cpu programming model byte ordering iop 480 data book r2.0 24-18 ? 2000 plx technology, inc. all rights reserved. 24.4.4 endian storage attribute the endian storage attribute (e bit), defined in the ibm powerpc embedded environment, also supports using the iop 480 cpu in a little endian system. for every storage reference (instruction fetch or load/store access), an e bit is associated with the address region of the storage reference. the e bit specifies whether that region is organized as big endian (e = 0) or little endian (e = 1). unlike the organization of memory when using the powerpc little endian mode, bytes in storage regions that are programmed as little endian using the e bit are arranged in true little endian format. furthermore, no address modification is performed when accessing storage regions programmed as e = 1. instead, when accessing storage regions with e = 1, the iop 480 cpu reorders the bytes as they are transferred between the processor and memory. unlike powerpc little endian mode, the e storage attribute supports direct connections to little endian hardware and to memory containing little endian programs and data structures that may be shared with other little endian devices. the on-the-fly reversal of bytes accessed in little endian storage regions is handled in one of two ways, depending on whether the storage access is an instruction fetch or a data (load/store) access. the following sections describe byte reversal for the two kinds of storage accesses. 24.4.4.1 fetching instructions from little endian storage regions powerpc architecture defines instructions as aligned lwords (four bytes) in memory. as such, instructions in a big endian program image are arranged with the most significant byte (msb) of the instruction lword at the lowest numbered address. consider the big endian mapping of instruction p at address 00, where, for example , p = add r7, r7, r4: on the other hand, in a little endian program the same instruction is arranged with the least significant byte (lsb) of the instruction lword at the lowest numbered address: when an instruction is fetched from memory, the instruction must be placed in the pipeline in the proper order. otherwise, the instruction decoder cannot recognize it. because the powerpc architecture, by default, is big endian, the msb of an instruction lword is assumed to be at the lowest address. therefore, when instructions are fetched from little endian storage regions, the four bytes of an instruction lword must be reversed before the instruction is decoded. in the iop 480 cpu, the byte reversal occurs between memory and the instruction cache unit (icu). the icu always contains instructions in big endian format, regardless of whether the storage region containing the instruction was programmed as big endian or little endian. thus, the bytes are already in the proper order when an instruction is transferred from the icu to the decode stage of the pipeline. if a storage region is reprogrammed from one endian format to the other, the contents of the storage region must be reloaded with program and data structures in the appropriate endian format. if the contents of instruction memory change, the icu must be made coherent with the updates. the icu must be invalidated and the updated memory contents must be fetched in the new endian format so that the proper byte reversal (or for big endian, no byte reversal) occurs before the new instructions are placed in the icu. 24.4.4.2 accessing data in little endian storage regions unlike instruction fetches from little endian storage regions, data accesses from little endian storage regions are not byte-reversed between memory and the dcu. data byte ordering, in memory, depends on the data type (byte, word, or lword) of a specific data item. it is only when moving a data item of a specific type from or to a gpr that it becomes known whether byte reversal is required due to the endian format of the data item. therefore, byte reversal during load/ msb lsb 0x00 0x01 0x02 0x03 lsb msb 0x00 0x01 0x02 0x03 section 24 byte ordering iop 480 cpu programming model iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-19 section 24 ? cpu pgmg model store accesses is performed between the dcu and the gpr file, depending on whether the load/store was for a byte, word, or lword. referring to the big endian and little endian mappings of structure s (as shown in section 24.4.1, ? structure mapping examples, ? on page 24-13), the differences between the byte locations of any data item in the structure depends upon the size of the particular data item. for example (again referring to the big endian and little endian mappings of structure s ) : the lword a has its four bytes reversed within the lword spanning addresses 00 ? 03 the word e has its two bytes reversed within the word spanning addresses 1c ? 1d the array of bytes d , where each data item is a byte, is not reversed when the big endian and little endian mappings are compared. for example , the character ? a ? is located at address 14 in both the big endian and little endian mappings. the size of the data item being loaded or stored must be known before the processor can decide whether, and if so, how to reorder the bytes when moving them between a gpr and storage. when accessing data in a little endian storage region: for byte loads/stores, no reordering of bytes occurs for word loads/stores, bytes are reversed within the word for lword loads/stores, bytes are reversed within the lword this mechanism applies, regardless of the alignment of data. for example , when loading a data lword from a little endian storage region, all four bytes of the lword are retrieved from memory (or the dcu). then, the bytes are placed in the gpr so that the byte from the lowest address is placed in the lsb of the gpr. in little endian storage regions, the alignment of data is treated as it is in big endian storage regions. unlike powerpc little endian mode, no special alignment exceptions occur when accessing data in little endian storage regions. note that the alignment exceptions that apply to big endian region accesses also apply to little endian storage region accesses. see section 11.7.9, ? alignment exception, ? on page 11-24, for detailed descriptions of conditions causing alignment exceptions. 24.4.4.3 endian storage attribute control control of the endian (e) storage attribute, for a given access, depends upon whether the iop 480 cpu is operating with the associated msr relocation bit on or off (msr[ir] for instruction fetches and msr[dr] for data accesses). in virtual mode (address translation is enabled: msr[ir] = 1 for instruction fetches, or msr[dr] = 1 for data accesses), the e storage attribute for an access is supplied as the e bit from the tlb entry for the page containing the addressed memory. if the e bit is 1, the page is little endian. otherwise the page is big endian. see section 27, ? iop 480 cpu memory management, ? for more information about the tlb and the storage attribute control registers. in real mode (msr[ir] = 0 or msr[dr] = 0), the e storage attribute, for a given access, is controlled by the storage little-endian register (sler), which is a storage attribute control register similar to those controlling the other storage attributes. the sler is a 32-bit register that provides the e storage attribute for each 128-mb storage attribute control region in the 4-gb address space. the high- order five bits of the storage address select, from the sler, the e storage attribute associated with the address region. setting a bit to 1 in the sler specifies that the associated storage region is little endian. 24.4.4.4 powerpc byte-reverse instructions powerpc architecture defines byte-reverse load/store instructions, which can perform a function similar to the action taken automatically by the iop 480 cpu when it accesses data in little endian storage regions using the normal load/store instructions. however, the byte-reverse load/store instructions are not as generally useful as the endian storage attribute mechanism. for big endian storage regions, the normal (non-byte- reverse) load/store instructions operate as defined in the instruction descriptions, moving the more significant bytes of the register to and from the lower- numbered memory addresses. the load/store with section 24 iop 480 cpu programming model byte ordering iop 480 data book r2.0 24-20 ? 2000 plx technology, inc. all rights reserved. byte-reverse instructions move the more significant bytes of the register to and from the higher numbered memory addresses. the opposite is true for little endian storage regions, where the normal load/store instructions give the same results that load/store with byte-reverse instructions do in big endian storage regions. load/ store with byte-reverse instructions give the same results that normal load/store instructions do in big endian storage regions. as figure 24-2 through figure 24-5 illustrate, a normal store to a big endian storage region is the same as a byte-reverse store to a little endian storage region, while a normal store to a little endian storage region is the same as a byte-reverse store to a big endian storage region. figure 24-4 illustrates the contents of a gpr and memory (starting at address 00) after a normal load/ store in a big endian storage region. note that the results are identical to the results of a load/store with byte-reverse in a little endian storage region, as illustrated in figure 24-3. figure 24-4 illustrates the contents of a gpr and memory (starting at address 00) after a load/store with byte-reverse in a big endian storage region. note that the results are identical to the results of a normal load/store in a little endian storage region, as illustrated in figure 24-5. gpr lsb msb memory 0x00 0x01 0x02 0x03 11 12 13 14 11 12 13 14 figure 24-2. normal lword load or store (big endian storage region) gpr lsb msb memory 0x00 0x01 0x02 0x03 11 12 13 14 11 12 13 14 figure 24-3. byte-reverse lword load or store (little endian storage region) gpr lsb msb memory 0x00 0x01 0x02 0x03 11 12 13 14 14 13 12 11 figure 24-4. byte-reverse lword load or store (big endian storage region) section 24 instruction processing iop 480 cpu programming model iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-21 section 24 ? cpu pgmg model . the e storage attribute augments the byte-reverse load/store instructions in two important ways: the load/store with byte-reverse instructions do not solve the problem of fetching instructions from a program image in true little endian format. only the endian storage attribute mechanism supports the fetching of true little endian program images. typical compilers cannot make general use of the byte-reverse load/store instructions, so these instructions are ordinarily used only in special, hand-coded device drivers. compilers can, however, take full advantage of the endian storage attribute mechanism, enabling application programmers working in a high-level language, such as c, to compile programs and data structures into little endian format. 24.5 instruction processing the instruction queue, illustrated in figure 24-6, contains three queue locations ? prefetch buffer 1 (pfb1), pfb0, and decode (dcd). this queue implements a pipeline with the following functional stages: fetch, decode, and execute. instructions are fetched from the instruction cache unit (icu) and dispatched to the execution unit (exu). instructions are fetched, at the request of the exu, from the icu. cacheable instructions are forwarded directly to the instruction queue and stored in the cache. non-cacheable instructions are also forwarded directly to the instruction queue, but are not stored in the cache. fetched instructions drop to the empty queue location closest to the exu. if the queue is empty, an entering instruction drops directly to dcd. pfb0 and pfb1 simply buffer instructions when the pipeline stalls. instructions are decoded entirely in dcd. branches are predicted and determined during decoding. after decoding (and determination, for branch instructions), the instruction is dispatched to the execution unit (exu), where it is executed. 24.6 branching control the iop 480 cpu, which provides a variety of conditional and unconditional branching instructions, uses the branch prediction techniques described in section 24.6.5, ? branch prediction, ? on page 24-23. 24.6.1 aa field on unconditional branches the unconditional branches ( b , ba , bl , bla ) carry the displacement to the branch target address as a 26-bit value (the 24-bit li field right-extended with two zeroes). this displacement is regarded as a signed 26-bit number covering an address range of 32 mb. for the relative (aa = 0) forms ( b , bl ), the target address is the current instruction address (cia, the address of the branch instruction) plus the signed displacement. for the absolute (aa = 1) forms ( ba , bla ), the target address is zero plus the signed displacement. if the sign bit (li[0]) is zero, the displacement is the target address. if the sign bit is one, the address is ? below zero ? and wraps to high memory. for example , if the displacement is 0x3ff fffc (the 26-bit representation of negative four), the target address is 0xffff fffc (zero minus four bytes, or four bytes from the top of memory). gpr lsb msb memory 0x00 0x01 0x02 0x03 11 12 13 14 14 13 12 11 figure 24-5. normal lword load or store (little endian storage region) section 24 iop 480 cpu programming model branching control iop 480 data book r2.0 24-22 ? 2000 plx technology, inc. all rights reserved. 24.6.2 aa field on conditional branches the conditional branches ( bc , bca , bcl , bcla ) carry the displacement to the branch target address as a 16-bit value (the 14-bit bd field right-extended with two zeroes). this displacement is regarded as a signed 16-bit number, covering an address range of 32 kb. for the relative (aa = 0) forms ( bc , bcl ), the target address is the current instruction address (cia, the address of the branch instruction) plus the signed displacement. for the absolute (aa = 1) forms ( bca , bcla ), the target address is zero plus the signed displacement. if the sign bit (bd[0]) is zero, the displacement is the target address. if the sign bit is one, the address is ? below zero ? and wraps to high memory. for example , if the displacement is 0xfffc (the 16-bit representation of negative four), the target address is 0xffff fffc (zero minus four bytes, or four bytes from the top of memory). 24.6.3 bi field on conditional branches conditional branch instructions can test one bit of the condition register (cr). the value of the bi field specifies the bit to be tested (bit 0 ? 31). the content of the bi field is meaningless unless bo[0] = 0. 24.6.4 bo field on conditional branches the bo field specifies the condition under which a branch is taken, and how the branch affects the ctr. conditional branch instructions can test one bit in the cr. this option is selected when bo[0] = 0; if bo[0] = 1, the cr does not participate in the branch condition test. if this option is selected, the condition is satisfied (branch can occur) if cr[bi] = bo[1]. conditional branch instructions can decrement the count register (ctr) by one, and after the decrement, test the ctr value. this option is selected when bo[2] = 0. if this option is selected, bo[3] specifies the condition that must be satisfied to allow a branch to be taken. if bo[3] = 0, ctr 0 is required for a branch to occur. if bo[3] = 1, ctr = 0 is required for a branch to occur. if bo[2] = 1, the contents of ctr remain unchanged, and the ctr does not participate in the branch condition test. exu dcd pfb0 pfb1 icu figure 24-6. iop 480 cpu instruction queue fetch dispatch section 24 branching control iop 480 cpu programming model iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-23 section 24 ? cpu pgmg model table 24-4 summarizes the usage of the bits of the bo field. bo[4] is further discussed in section 24.6.5, ? branch prediction, ? on page 24-23. table 24-5 lists specific bo field contents, and the resulting actions. in table 24-5, z represents a mandatory value of zero, and y is a branch prediction option discussed in section 24.6.5, ? branch prediction, ? on page 24-23, . 24.6.5 branch prediction conditional branches present a problem to the fetcher. a branch might be taken; if not taken, the branch simply falls through to the next sequential instruction. the iop 480 cpu attempts to predict whether a branch is taken before all information necessary to determine the branch direction is available. this decision is called a branch prediction . the fetcher can then prefetch instructions down the predicted path. if the prediction is correct, time is saved because the branched-to instruction is available in the instruction queue. otherwise, time is lost while the correct instruction is fetched into the instruction queue. to be effective, branch prediction must be correct most of the time. the iop 480 cpu uses powerpc branch prediction to minimize incorrect predictions, and enables software to reverse the standard branch prediction, which is defined as follows: predict that the branch is to be taken if ((bo[0] bo[2]) s)=1 where s is bit 16 of the instruction (the sign bit of the displacement for all bc forms, and zero for all bclr and bcctr forms). (bo[0] bo[2]) = 1 only when the conditional branch tests nothing (the ? branch always ? condition). obviously, the branch should be predicted taken for this case. if the branch tests anything, (bo[0] bo[2]) = 0, and s entirely controls the prediction. the standard prediction for this case derives from considering the relative form of bc , often used at the end of loops to control the number of times that a loop is executed. the branch is taken each time the loop is executed except the last, so it is best if the branch is predicted taken. the branch target is the beginning of the loop, so the branch displacement is negative and s = 1. because this situation is so common, a branch is taken if s = 1. if branch displacements are positive, s = 0, and the branch is predicted not taken. if the branch instruction is any form of bclr or bcctr except the ? branch always ? forms, then s = 0, and the branch is predicted not taken . there is a peculiar consequence of this prediction algorithm for the absolute forms of bc ( bca and bcla ). table 24-4. bits of the bo field bo bit description bo[0] cr test control 0 test cr bit specified by bi field for value specified by bo[1] 1 do not test cr bo[1] cr test value 0 if bo[0] = 0, test for cr[bi] = 0. 1 if bo[0] = 0, test for cr[bi] = 1. bo[2] ctr test control 0 decrement ctr by one and test whether ctr satisfies the condition specified by bo[3]. 1 do not change ctr, do not test ctr. bo[3] ctr test value 0 if bo[2] = 0, test for ctr 0. 1 if bo[2] = 0, test for ctr = 0. bo[4] branch prediction reversal 0 apply standard branch prediction. 1 reverse the standard branch prediction. table 24-5. conditional branch bo field bo value description 0000y decrement the ctr, then branch if the decremented ctr 0 and cr[bi]=0. 0001y decrement the ctr, then branch if the decremented ctr = 0 and cr[bi] = 0. 001zy branch if cr[bi] = 0. 0100y decrement the ctr, then branch if the decremented ctr 0 and cr[bi] = 1. 0101y decrement the ctr, then branch if the decremented ctr=0 and cr[bi] = 1. 011zy branch if cr[bi] = 1. 1z00y decrement the ctr, then branch if the decremented ctr 0. 1z01y decrement the ctr, then branch if the decremented ctr = 0. 1z1zz branch always. section 24 iop 480 cpu programming model speculative accesses iop 480 data book r2.0 24-24 ? 2000 plx technology, inc. all rights reserved. as described in section 24.6.2, ? aa field on conditional branches, ? on page 24-22, if s = 1, the branch target is in high memory. if s = 0, the branch target is in low memory. because these are absolute- addressing forms, there is no reason to treat high and low memory differently. nevertheless, for the high memory case the standard prediction is taken, and for the low memory case the standard prediction is not taken . bo[4] is the prediction reversal bit . if bo[4] = 0, the standard prediction is applied. if bo[4] = 1, the reverse of the standard prediction is applied. for the cases in table 24-5 where bo[4] = y, software can reverse the standard prediction. this should only be done when the standard prediction is likely to be wrong. note that for the ? branch always ? condition, reversal of the standard prediction is not allowed. powerpc architecture requires assemblers to provide a way to conveniently control branch prediction. for any conditional branch mnemonic, a suffix may be added to the mnemonic to control prediction, as follows: + predict branch to be taken ? predict branch to be not taken for example , bcctr+ causes bo[4] to be selected appropriately to force the branch to be predicted taken. 24.7 speculative accesses the powerpc architecture permits implementations to perform speculative accesses to memory, either for instruction fetching, or for data loads. a speculative access is defined as any access which is not required by a sequential execution model. for example , prefetching instructions beyond an undetermined conditional branch is a speculative fetch; if the branch is not in the predicted direction, the program, as executed, never needs the instructions from the predicted path. similarly, in a superscalar processor that performs out-of-order execution, a program can speculatively fetch a load instruction that is past an undetermined branch. sometimes speculative accesses are inappropriate, however. for example , attempting to fetch instructions from addresses that cannot contain instructions can cause problems.to protect against errant accesses to ? sensitive ? memory or i/o devices, the powerpc architecture provides the g (guarded) storage attribute, which can be used to specify memory pages from which speculative accesses are prohibited. (actually, speculative accesses to guarded storage are allowed in certain limited circumstances; if an instruction in a cache block is executed, the remainder of the cache block can be speculatively accessed. 24.7.1 speculative accesses in iop 480 cpu the iop 480 cpu does not perform out-of-order execution, nor does it perform speculative loads. the iop 480 cpu provides two methods to enable or disable speculative instruction fetching. if address translation is enabled (msr[ir] = 1), the g (guarded) field in each translation lookaside buffer (tlb) entry controls speculative accesses. each tlb entry controls speculative access for a page of virtual memory, which can range in size from 1 kb ? 16 mb. if address translation is disabled (msr[ir] = 0), the storage guarded register (sgr) controls speculative accesses for regions of memory. when a page is guarded (speculative fetching is disallowed), prefetching is disabled for that page. a fetch request must be completely resolved (no longer speculative) before it is issued. there is a considerable performance penalty for fetching from guarded storage, so guarding should be used only when required. note: following any reset, the iop 480 cpu operates with all of the storage guarded. when address translation is enabled, an attempt to access guarded storage results in an instruction storage exception. because the mmu provides high granularity (pages can be as small as 1 kb), fetching instructions from guarded storage should be unnecessary. 24.7.1.1 prefetch distance down an unresolved branch path the fetcher speculatively accesses up to five instructions down a predicted branch path, whether taken or sequential. the unresolved branch is in the dcd stage of the instruction queue (see section 24.5, ? instruction processing, ? on page 24-21 for a description of the instruction queue). if pfb0 and section 24 speculative accesses iop 480 cpu programming model iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-25 section 24 ? cpu pgmg model pfb1 are full, no further speculative accesses occur. if pfb0 or pfb1 is empty, the fetcher requests the next speculative instruction from the icu; that instruction is placed in pfb0 or pfb1. if the fetched instruction is at the end of a cache line, and if pfb1 is empty, the fetcher requests the next cache line. the instruction at the beginning of the cache line is placed in pfb1. in this case, five instructions are speculatively accessed. the fetcher can speculatively access no more than four instructions (a cache line) from the cache with a single request, assuming the speculative address is cacheable. if the address is non-cacheable [as controlled by the instruction cache cacheability register (iccr)], no more than two instructions are speculatively accessed. 24.7.1.2 prefetch of branches to count register and branches to link register when the fetcher predicts that a bctr or blr instruction is taken, it does not attempt to access the target address in the count register (ctr) or link register (lr) if an executing instruction updates the ctr or lr ahead of the branch in dcd in the instruction queue. (see section 24.5, ? instruction processing, ? on page 24-21 for description of the instruction queue). the fetcher recognizes that the ctr or lr contains data from an earlier use of the ctr or lr. such data is probably not valid. in such cases, the fetcher does not fetch the instruction at the target address until the instruction updating the ctr or lr completes and exu is empty; only then are the ? correct ? ctr or lr contents known. this prevents the fetcher from speculatively accessing a completely ? random ? address. when the ctr or lr contents are known to be correct, the fetcher accesses no more than five instructions down the sequential or taken path of an unresolved branch, or at the address contained in the ctr or lr. 24.7.2 preventing inappropriate speculative accesses a memory-mapped i/o device that has a status register that is automatically reset when read provides a simple example of storage that should not be speculatively accessed. consider a serial port that reads the receive buffer on the port and then resets the rxrdy bit in the status register. if the processor speculatively loads from this register, and an intervening branch or interrupt takes the program flow away from the code containing the load instruction and then returns, the wrong result is obtained when the status register is read again. similarly, if the program code is in memory ? next to ? the i/o device ( for example , code goes from 0x0000 0000 to 0x0000 0fff, and the i/o device is at 0x0000 1000), prefetching past the end of the code can ? hit ? the i/o device. guarded storage can prevent prefetching past the ? end ? of memory. the fetcher attempts to fetch past the last valid address, likely getting machine checks on the fetches to invalid addresses. while the machine checks do not result in an exception until the processor attempts to execute an instruction at an invalid address, some systems may suffer from the attempt to access such an invalid address. for example , an external memory controller might log the error. system designers can avoid problems from speculative fetching in other ways, without using the guarded storage attributes. the remainder of this section describes ways to guard against speculative instruction fetches to sensitive addresses in unguarded memory regions. section 24 iop 480 cpu programming model speculative accesses iop 480 data book r2.0 24-26 ? 2000 plx technology, inc. all rights reserved. 24.7.2.1 fetching past an interrupt-causing or interrupt-returning instruction suppose a bctr or blr instruction follows an interrupt- causing or interrupt-returning instruction ( sc , rfi , or rfci ). the fetcher does not prevent speculatively fetching past one of these instructions. in other words, the fetcher does not treat the interrupt-causing and interrupt-returning instructions specially when deciding whether to predict down a branch path. instructions after an rfi , for example , are considered to be on the determined branch path. to understand the implications of this situation, consider the code sequence: handler: aaa bbb rfi subroutine: bctr when executing the interrupt handler, the fetcher does not recognize the rfi as a break in the program flow, and speculatively fetches the target of the bctr , which is really the first instruction of a subroutine that has not been called. therefore, the ctr might contain an invalid pointer. to protect against such a prefetch, the software should insert an unconditional branch hang ( b $ ) just after the rfi . this prevents the hardware from prefetching the wrong ? target ? of the bctr . consider also the above code sequence, with the rfi instruction replaced by an sc instruction. the purpose of the system call is to initialize the ctr with the appropriate value for the bctr to branch to, upon return from the system call. the sc handler returns to the instruction following the sc , which can ? t be a branch hang. instead, software could put a mtctr just before the sc to load a nonsensitive address into the ctr. this address is used as the prediction address before the sc executes. an alternative would be to put a mfctr or mtctr between the sc and the bctr ; the mtctr prevents the fetcher from speculatively accessing the address contained in the ctr before initialization. 24.7.2.2 fetching past tw or twi instructions the interrupt-causing instructions, tw and twi , do not require the special handling described in section 24.7.2.1, ? fetching past an interrupt-causing or interrupt-returning instruction, ? on page 24-26. these instructions are typically used by debuggers, which implement software breakpoints by substituting a trap instruction for the instruction originally at the breakpoint address. in a code sequence mtlr followed by blr (or mtctr followed by bctr ), replacement of mtlr / mtctr by tw or twi leaves the lr/ctr uninitialized. it would be inappropriate to fetch from the blr / bctr target address. this situation is common, and the fetcher is designed to prevent the problem. 24.7.2.3 fetching past an unconditional branch when an unconditional branch is in dcd in the instruction queue, the fetcher recognizes that the sequential instructions following the branch are unnecessary. these sequential addresses are not accessed. addresses at the branch target are accessed instead. therefore, placing an unconditional branch just before the start of a sensitive address space ( for example , at the ? end ? of a memory area that borders an i/o device) guarantees that addresses in the sensitive area are not speculatively fetched. 24.7.2.4 suggested locations of memory-mapped hardware table 24-6 shows two address regions of the iop 480 cpu. suppose a system designer can map all i/o devices and all rom and sram devices, for example , anywhere into either region. the choices made by the designer can prevent speculative accesses to the memory-mapped i/o devices. table 24-6. example memory mapping 0x7800 0000 ? 0x7fff ffff (sgr bit 15) 128 mb region 2 0x7000 0000 ? 0x77ff ffff (sgr bit 14) 128 mb region 1 section 24 privileged mode operation iop 480 cpu programming model iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-27 section 24 ? cpu pgmg model a simple way to avoid the problem of cacheable instruction fetches colliding with i/o devices meant to be non-cacheable would be to map all rom and sram devices into region 2, and all i/o devices into region 1. thus, addresses in region 1 should be accessed only by non-cacheable load/store instructions accessing i/ o devices; no speculative fetches should occur. region 1 could be set as guarded in the sgr; no performance penalty would result, since by design there is no possibility of prefetching from region 1. accesses to region 2 would be for code and program data. speculative fetches in region 2 can never access addresses in region 1. note that this hardware organization makes the use of the sgr to protect region 1 redundant and optional. the use of these regions could be reversed (code in region 1 and i/o devices in region 2), if region 2 is set as guarded in the sgr. prefetching from the top of region 1 could attempt to speculatively access the bottom of region 2, but guarding prevents a speculative access from occurring. the performance penalty is slight, under the assumption that code infrequently executes near the top of region 1. 24.7.3 summary in summary, software should take the following actions to prevent speculative accesses to sensitive data areas, if the sensitive data areas are not in guarded storage: protect against accesses to ? random ? values in the lr or ctr on blr or bctr branches following rfi , rfci , or sc instructions by putting appropriate instructions before or after the rfi , rfci , or sc instruction. see section 24.7.2.1, ? fetching past an interrupt-causing or interrupt-returning instruction, ? on page 24-26. protect against ? running past ? the end of memory into a bordering i/o device by putting an unconditional branch at the end of the memory area. see section 24.7.2.3, ? fetching past an unconditional branch, ? on page 24-26. recognize that a maximum of five lwords (20 bytes) can be prefetched past an unresolved conditional branch, either down the target path or the sequential path. see section 24.7.1.1, ? prefetch distance down an unresolved branch path, ? on page 24-24. of course, software should not code branches with known unsafe targets (either instruction counter- relative or lr- or ctr-based), on the assumption that they are ? protected ? by guaranteeing that the unsafe direction is ? not-taken. ? the prefetcher can assume that if a branch ? might ? be taken, it is safe to fetch down the target path. 24.8 privileged mode operation in powerpc architecture, several terms describe two operating modes that have different instruction execution privileges. when a processor is ? privileged mode, ? it can execute all instructions in the instruction set. this mode is also called the ? supervisor state. ? the other mode, in which certain instructions cannot be executed, is called the ? user mode, ? or ? problem state. ? these terms are used in pairs: the architecture uses the pr in the machine status register (msr) to controls the execution mode. when msr[pr] = 1, the processor is in user mode (problem state); when msr[pr] = 0, the processor is in privileged mode (supervisor state). 24.8.1 msr bits and exception handling attempting to execute a privileged instruction while msr[pr] = 1 causes a privileged violation program exception (see section 11.7.10, ? program exceptions, ? on page 11-24). the iop 480 cpu does not execute the instruction, and the least-significant 16 bits of the program counter are loaded with 0x0700, the address of an exception processing routine. the current value of the msr[pr] bit is saved in the srr1/srr3 (along with all the other msr bits) upon any interrupt, and the msr[pr] bit is set to 0, in all cases. this means that all exception handlers operate in privileged mode. table 24-7. instruction execution privileges and operating modes privileged nonprivileged privileged mode user mode supervisor state problem state section 24 iop 480 cpu programming model synchronization iop 480 data book r2.0 24-28 ? 2000 plx technology, inc. all rights reserved. the exception syndrome register (esr) distinguishes different types of program exceptions. esr[ppr] is set when the exception was caused by a privileged exception. software is not required to clear this esr bit. 24.8.2 privileged instructions the following instructions are privileged and cannot be executed when msr[pr] = 1: 24.8.3 privileged sprs all sprs are privileged, except for the lr, the ctr, the tbhu, the tblu, and the xer except for moves to and from non-privileged sprs, attempts to execute mfspr and mtspr instructions while in user mode result in privileged violation program exceptions. in a mfspr or mtspr instruction, the 10-bit sprn field specifies the spr number of the source or destination spr. the sprn field contains two five-bit subfields, sprn 0:4 and sprn 5:9 . the assembler handles the unusual register number encoding to generate the sprf field. in the machine code for the mfspr and mtspr instructions, the sprn subfields are reversed (ending up as sprf 5:9 and sprf 0:4 ) for compatibility with the power architecture. in the powerpc architecture, spr numbers having a 1 in the most-significant bit of the sprf field are privileged. the following example illustrates how spr numbers appear in assembler language coding and in machine coding of the mfspr and mtspr instructions. in assembler language coding, srr0 is spr 26. note that the assembler handles the unusual register number encoding to generate the sprf field. mfspr r5,26 when the spr number is considered as a binary number (0b00000 11010), the most-significant bit is 0. however, the machine code for the instruction reverses the subfields, resulting in the following sprf field: 0b11010 00000. the most-significant bit is 1; srr0 is privileged. when an spr number is considered as a hexadecimal number, the second digit of the three-digit hexadecimal number indicates whether an spr is privileged. if the second digit is odd (1, 3, 5, 7, 9, b, d, f), the spr is privileged. for example , the spr number of srr0 is 26 (0x01a). the second hexadecimal digit is odd; srr0 is privileged. in contrast, the lr is spr 8 (0x008); the second hexadecimal digit is not odd; the lr is nonprivileged. 24.8.4 privileged dcrs the mtdcr and mfdcr instructions themselves are privileged, in all cases. all dcrs are privileged. 24.9 synchronization the iop 480 cpu supports the synchronization operations of powerpc architecture. the following book, chapter, and section numbers refer to related information in the powerpc architecture: a specification for a new family of risc processors : book ii, section 1.8.1, ? storage access ordering ? and ? enforce in-order execution of i/o ? book iii, section 1.7, ? synchronization ? book iii, chapter 7, ? synchronization requirements for special registers and lookaside buffers ? table 24-8. privileged instructions dcbi dccci dcread icbt iccci icread mfdcr mfmsr mfspr for all sprs except ctr, lr, tbhu, tblu, xer. see section 24.8.3 mtdcr mtmsr mtspr for all sprs except ctr, lr, xer. see section 24.8.3 rfci rfi wrtee wrteei section 24 synchronization iop 480 cpu programming model iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-29 section 24 ? cpu pgmg model 24.9.1 context synchronization the context of a program is the environment ( for example , privilege and relocation) in which the program executes. context is controlled by the content of certain registers, such as the machine state register (msr), and includes the content of all gprs and sprs. an instruction or event is ? context synchronizing ? if it satisfies the following requirements: 1. all instructions that precede a context synchronizing operation must complete in the context that existed before the context synchronizing operation. 2. all instructions that follow a context synchronizing operation must complete in the context that exists after the context synchronizing operation. such instructions and events are called ? context synchronizing operations. ? in the iop 480 cpu, these include most interrupts and the isync , rfci , rfi , and sc instructions. however, ? context ? specifically excludes the contents of memory. a context synchronizing operation does not guarantee that subsequent instructions observe the memory context established by previous instructions. to guarantee memory access ordering in the iop 480 cpu, one must use either an eieio instruction or a sync instruction. for the iop 480 cpu, the eieio and sync instructions are implemented identically. see section 24.9.3, ? storage synchronization, ? on page 24-31. the contents of dcrs are not considered as part of the processor ? context ? managed by a context synchronizing operation. dcrs are peripherals of a processor, and are analogous to memory-mapped registers. their context is managed in a manner similar to that of memory contents. finally, implementations of the powerpc architecture can exempt the machine check exception from context synchronization control. if the machine check exception is exempted, an instruction that precedes a context synchronizing operation can cause a machine check exception after the context synchronizing operation occurs and additional instructions have completed. the following scenarios use psuedocode examples to illustrate these limitations of context synchronization. subsequent text explains software can further guarantee ? storage ordering. ? 1. consider the following instruction sequence: store non-cacheable to address xyz isync xyz instruction in this sequence, the isync instruction does not guarantee that the xyz instruction is fetched after the store has occurred to memory. there is no guarantee which xyz instruction executes; either the old version or new (stored) version might. 2. this assumes that the iop 480 cpu is part of a standard product that uses dcrs to provide bus region control using dcr: store non-cacheable to address xyz isync mtdcr to change a bus region containing xyz in this sequence, there is no guarantee that the store occurs before the mtdcr instruction changing the bus region control dcr. the store could fail because of a configuration error. how can software ensure that the contents of memory and dcrs are synchronized in the instruction stream? the eieio instruction or the sync instruction perform this task. these instructions guarantee storage ordering; all memory accesses that precede eieio or sync affect the results of all subsequent memory accesses. neither eieio nor sync guarantee that instruction prefetching follows the eieio or sync . the instructions do not cause the prefetch queues to be purged and instructions to be refetched. see section 24.9.3, ? storage synchronization, ? on page 24-31 for more information about sync and eieio . instruction cache state is part of context. a context synchronization operation is required to guarantee instruction cache access ordering. section 24 iop 480 cpu programming model synchronization iop 480 data book r2.0 24-30 ? 2000 plx technology, inc. all rights reserved. consider the following instruction sequence, which is required for self-modifying code: similarly, if software wishes to ensure that all storage accesses are complete before executing a mtdcr to change a bus region (example 2), the software must issue a sync after all storage accesses and before the mtdcr . likewise, if the software is to ensure that all instruction fetches after the mtdcr use the new bank register contents, the software must issue an isync , after the mtdcr and before the first instruction that should be fetched in the new context. the isync instruction guarantees that all subsequent instructions are fetched and executed using the context established by all previous instructions. the isync instruction is a context synchronizing operation; isync causes all prefetched instructions to be discarded and refetched. the following example illustrates the use of isync with debug exceptions: 24.9.2 execution synchronization for completeness, consider the definition of execution synchronizing as it relates to context synchronization. execution synchronization is architecturally a subset of context synchronization. execution synchronization guarantees that the following requirement is met: all instructions that precede an execution synchronizing operation must complete in the context that existed before the execution synchronizing operation. the following requirement need not be met: all instructions that follow an execution synchronizing operation must complete in the context that exists after the execution synchronizing operation. execution synchronization ensures that preceding instructions execute in the old context; subsequent instructions might execute in either the new or old context (indeterminate). the iop 480 cpu provides three execution synchronizing operations: the eieio , mtmsr , and sync instructions. because mtmsr is execution synchronizing, it guarantees that previous instructions complete using the old msr value. (consider the previous example of using mtmsr to change the endian mode.) however, to guarantee that subsequent instructions use the new msr value, we have to insert a context synchronization operation, such as isync . the powerpc architecture requires msr[ee] (the external interrupt bit) to be, in effect, execution synchronizing: if a mtmsr turns on the ee bit, and an external interrupt is pending, the exception must be taken before the instruction that follows mtmsr is executed. however, the mtmsr instruction is not a context synchronizing operation, so the iop 480 cpu does not, for example , discard prefetched instructions and refetch. note that the wrtee and wrteei instructions can change the value of msr[ee], but are not execution synchronizing. finally, while sync and eieio are execution synchronizing, they are also more restrictive in their requirement of memory ordering. stating that an operation is execution synchronizing does not imply storage ordering. this is an additional specific requirement of sync and eieio . store change data cache contents. dcbst flush the new data cache contents to memory. sync guarantee that dcbst completes before subsequent instructions begin. icbi context changing operation; invalidates instruction cache contents. isync context synchronizing operation; causes refetch using new instruction cache context text and new memory context, due to the previous sync. mtdbcr set up an instruction address compare (iac) event. isync wait for the new debug control register (dbcr) context to be established. xyz this instruction is at the iac address; an isync was necessary to guarantee that the iac event happens at the execution of this instruction. section 24 instruction set iop 480 cpu programming model iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-31 section 24 ? cpu pgmg model 24.9.3 storage synchronization the sync instruction guarantees that all previous storage references complete with respect to the iop 480 cpu before the sync instruction completes (therefore, before any subsequent instructions begin to execute). the sync instruction is execution synchronizing. consider the following use of sync : the eieio instruction guarantees the order of storage accesses. all storage accesses that precede eieio complete before any storage accesses that follow the instruction, as in the following example: the iop 480 cpu implements both sync and eieio identically, in the manner described above for sync . in the powerpc architecture, sync can function across all processors in a multiprocessor environment; eieio functions only within its executing processor. the iop 480 cpu is a uniprocessor; in this implementation, sync does not guarantee memory ordering across multiprocessors. 24.10 instruction set the iop 480 cpu instruction set contains instructions defined in the powerpc architecture and instructions specific to the ibm powerpc 400 family of embedded controllers. section 28, ? iop 480 cpu instruction set, ? contains detailed descriptions of each instruction, including psuedocode. appendix a, ? iop 480 cpu instruction summary ?? alphabetically lists each instruction and extended mnemonic and provides a short-form description. appendix b, ? iop 480 cpu instructions by category ?? provides short-form descriptions of instructions, grouped by the instruction categories listed in table 24-10. table 24-10 also summarizes iop 480 cpu instruction set functions by categories. instructions within each category are described in subsequent sections. 24.10.1 instructions specific to ibm powerpc embedded controllers to support functions required in embedded real-time applications, the ibm powerpc 400 family of embedded controllers defines instructions that are not defined in the powerpc architecture. table 24-9 lists the instructions specific to ibm powerpc embedded controllers. programs using these instructions are not portable to powerpc implementations that are not part of the ibm powerpc 400 family of embedded controllers. 24.10.2 storage reference instructions load and store instructions transfer data between memory and the gprs. these instructions operate on bytes, words, and lwords. storage reference instructions also support loading or storing multiple registers, character strings, and byte-reversed data. table 24-11 shows the storage reference instructions in the iop 480 cpu. stw store to i/o device. sync wait for store to actually complete off chip. mtdcr reconfigure device. stb x store to i/o device, address x; this resets a status bit in the device. eieio guarantee stb x completes before next instruction. lbz y load from i/o device, address y; this is the status register updated by stb x. eieio was necessary, because the read and write addresses are different, but affect one other. table 24-9. instructions specific to ibm powerpc-embedded controllers dccci dcread iccci icbt icread mfdcr mtdcr rfci tlbre tlbsx tlbsx. tlbwe wrtee wrteei section 24 iop 480 cpu programming model instruction set iop 480 data book r2.0 24-32 ? 2000 plx technology, inc. all rights reserved. . table 24-10. iop 480 cpu instruction set functional summary storage reference load, store arithmetic and logical add, subtract,negate, multiply, divide, and, andc, or, orc, xor, nand, nor, xnor, sign extension, count leading zeros comparison compare, compare logical, compare immediate branch branch, branch conditional, branch to lr, branch to ctr cr logical crand, crandc, cror, crorc, crnand, crnor, crxor, crxnor, move cr field rotate/shift rotate and insert, rotate and mask, shift left, shift right cache control invalidate, touch, zero, flush, store, read interrupt control write to external interrupt enable bit, move to/from msr, return from interrupt, return from critical interrup t processor management system call, synchronize, trap, move to/from dcrs, move to/from sprs, move to/from cr table 24-11. storage reference instructions loads stores byte word algebraic word multiple and string lword byte word multiple and string lword lbz lbzu lbzux lbzx lha lhau lhaux lhax lhbrx lhz lhzu lhzux lhzx lmw lswi lswx lwarx lwbrx lwz lwzu lwzux lwzx stb stbu stbux stbx sth sthbrx sthu sthux sthx stmw stswi stswx stw stwbrx stwu stwux stwx stwcx. table 24-12. arithmetic and logical instructions arithmetic logical add add. addo addo. addc addc. addco addco. adde adde. addeo addeo. addi addic addic. addis addme addme. addmeo addmeo. addze addze. addzeo addzeo. divw divw. divwo divwo. divwu divwu. divwuo divwuo. mulhw mulhw. mulhwu mulhwu. mulli mullw mullw. mullwo mullwo. neg neg. nego nego. subf subf. subfo subfo. subfc subfc. subfco subfco. subfe subfe. subfeo subfeo. subfic subme subme. submeo submeo. subfze subfze. subfzeo subfzeo. and and. andc andc. andi. andis. cntlzw cntlzw. eqv eqv. extsb extsb. extsh extsh. nand nand. nor nor. or or. orc orc. ori oris xor xor. xori xoris section 24 instruction set iop 480 cpu programming model iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-33 section 24 ? cpu pgmg model 24.10.3 arithmetic and logical instructions arithmetic operations are performed on integer or ordinal operands stored in registers. instructions that perform operations on two operands are defined in a three-operand format; an operation is performed on the operands, which are stored in two registers. the result is placed in a third register. instructions that perform operations on one operand are defined in a two-operand format; the operation is performed on the operand in a register and the result is placed in another register. several instructions also have immediate formats in which an operand is a field in the instruction. most arithmetic and logical instructions can set the condition register (cr) based on the result of the instruction. the instructions having mnemonics ending in . (period) are the forms that set the cr. table 24-12 on page 24-32 lists the arithmetic and logical instructions in the iop 480 cpu. 24.10.4 compare instructions these instructions perform arithmetic or logical comparisons between two operands and set the cr. table 24-13 lists the comparison instructions in the iop 480 cpu. 24.10.5 branch instructions these instruction unconditionally or conditionally branch to any address. conditional branch instructions can test condition codes set by a previous instruction and branch accordingly. conditional branch instructions can also decrement and test the count register as part of branch determination, and can save the return address in the link register.the target address for a branch can be a displacement from the current instruction address or an absolute address, or contained in the link or count registers. table 24-14 lists the branch instructions in the iop 480 cpu. 24.10.6 condition register logical instructions these instructions combine the results of several comparisons without incurring the overhead of conditional branching. code performance can significantly improve if multiple conditions are tested before a branch decision. table 24-15 lists the condition register logical instructions in the iop 480 cpu. 24.10.7 rotate and shift instructions these instructions rotate or shift operands stored in the gprs. rotate instructions can also mask rotated operands. table 24-16 lists the rotate and shift instructions in the iop 480 cpu. table 24-13. compare instructions arithmetic logical cmp cmpi cmpl cmpli table 24-14. branch instructions unconditional conditional b ba bl bla bc bca bcl bcla bcctr bcctrl bclr bclrl table 24-15. condition register logical instructions crand crandc creqv crnand crnor cror crorc crxor mcrf table 24-16. rotate and shift instructions rotate shift rlwimi rlwimi. rlwinm rlwinm. rlwnm rlwnm. slw slw. sraw sraw. srawi srawi. srw srw. section 24 iop 480 cpu programming model instruction set iop 480 data book r2.0 24-34 ? 2000 plx technology, inc. all rights reserved. 24.10.8 cache control instructions these instructions indirectly control the contents of the data and instruction caches. users can fill, flush, invalidate, and zero blocks (16-byte lines) in the data cache. users can invalidate and fill individual lines in the instruction cache, and invalidate congruence classes in both caches. table 24-17 lists cache control instructions in the iop 480 cpu. 24.10.9 interrupt control instructions these instructions move data between gprs and the msr, return from interrupts, and enable or disable maskable external interrupts. table 24-18 lists the interrupt control instructions in the iop 480 cpu. 24.10.10 tlb management instructions the tlb management instructions read and write entries of the tlb array in the mmu, search the tlb array for an entry which translates a given address, invalidate all tlb entries, and synchronize tlb updates with other processors. table 24-19 lists the tlb management instructions in the iop 480 cpu 24.10.11 processor management instructions these instructions move data between the gprs and control registers in the iop 480 cpu, and provide traps, system calls, and synchronization controls. table 24-20 lists the processor management instructions in the iop 480 cpu. 24.10.12 extended mnemonics in addition to mnemonics for instructions supported directly by hardware, the powerpc architecture defines numerous extended mnemonics . an extended mnemonic translates directly into the mnemonic of a hardware instruction, typically with carefully specified operands. for example , the powerpc architecture does not define a ? shift right lword immediate ? instruction, because the ? rotate left lword immediate then and with mask, ? ( rlwinm ) instruction, can accomplish the same result: rlwinm ra,rs,32 ? n,n,31 table 24-17. cache control instructions data cache instruction cache dcba dcbf dcbi dcbst dcbt dcbtst dcbz dccci dcread icbi icbt iccci icread table 24-18. interrupt control instructions mfmsr mtmsr rfi rfci wrtee wrteei table 24-19. tlb management instructions tlbia tlbre tlbsx tlbsx. tlbsync tlbwe table 24-20. processor management instructions eieio isync sync mcrxr mfcr mfdcr mfspr mtcrf mtdcr mtspr sc tw twi section 24 instruction set iop 480 cpu programming model iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 24-35 section 24 ? cpu pgmg model however, because the required operands are not obvious, the powerpc architecture defines an extended mnemonic: srwi ra,rs,n extended mnemonics transfer the problem of remembering complex or frequently used operand combinations to the assembler, and can more clearly reflect a programmer ? s intentions. thus, programs can be more readable. see the following sections and appendices for lists of the extended mnemonics: section 28, ? iop 480 cpu instruction set, ? lists extended mnemonics under the associated hardware instruction mnemonics. appendix a, ? iop 480 cpu instruction summary ?? lists extended mnemonics alphabetically, along with the hardware instruction mnemonics. table b-4 in appendix b, ? iop 480 cpu instructions by category ?? lists all extended mnemonics. iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 25-1 section 25 ? cpu cache ops 25 iop 480 cpu cache operations the iop 480 cpu incorporate two internal caches, an instruction cache unit (icu) and a data cache unit (dcu). the icu controls instruction accesses to main memory and, if an instruction cache array is implemented, stores frequently used instructions to reduce the overhead of instruction transfers between the instruction queue and external memory, minimizing access latency for frequently executed instructions. the dcu controls data accesses to main memory and, if a cache array is implemented, stores frequently used data to reduce the overhead of data transfers between the gprs and external memory, minimizing access latency for frequently used data. instructions and data can be accessed in the cache much faster than in main memory. the icu and dcu feature: line fills in target-lword-first, sequential, or any other order a separate bypass path to handle instructions and data in cache-inhibited memory, and to improve performance during line fills cache line locking the dcu features byte-writeability to improve the performance of byte and word operations, and supports write-back and write-through write strategies. the iop 480 cpu differ visibly in the size of their implemented cache arrays, which store cached instructions and data. section 25.1, ? icu and dcu organization, ? on page 25-1, describes the organization of the icu and dcu. 25.1 icu and dcu organization the icu and dcu contain control logic and, possibly, cache arrays. the control logic, which handles data transfers between the cache units, main memory, and the risc core, differs significantly between the icu and dcu. the icu and dcu cache arrays, which (when implemented) store instructions and data from main memory, respectively, are almost identical. (the dcu array adds a ? dirty ? bit to mark modified lines.) the icu and dcu cache arrays are two-way set- associative. in both cache units, a cache line can be in one of two locations in the cache array. the two locations are members of a set of locations. each set is divided into two ways, way a and way b; a cache line can be located in either way. each way is organized as n lines of four lwords each, where n is the cache size, in kilobytes, multiplied by 32. for example, a 2 kb cache array contains 64 lines. table 25-1. cache array size by core core icu cache array size dcu cache array size powerpc risc 4 kb 2 kb table 25-2. icu and dcu cache array organization tags (two-way set) cache lines (two-way set) way a way b way a way b a 0: m ? 1 line 0 a 0: m ? 1 line 0 line 0 line 0 a 0: m ? 1 line 1 a 0: m ? 1 line 1 line 1 line 1 ? ? ? ? ? ? ? ? ? ? ? ? a 0: m ? 1 line n ? 2a 0 m ? 1 line n ? 2 line n ? 2 line n ? 2 a 0: m ? 1 line n ? 1a 0: m ? 1 line n ? 1 line n ? 1 line n ? 1 section 25 iop 480 cpu cache operations icu overview iop 480 data book r2.0 25-2 ? 2000 plx technology, inc. all rights reserved. cache lines are addressed using a tag field and an index. the tag fields are also two-way set-associative. as shown in table 25-2 on page 25-1, the tag fields in ways a and b store address bits a 0: m ? 1 for each cache line; m is the number of address bits that specify the tag field. the remaining address bits (a m :27 ) serve as an index to the cache array. the two cache lines that correspond with the same line index are called a congruence class. table 25-3 shows the values of m and n for various cache array sizes. when the icu or dcu requests a cache line from main memory (an operation called a cache line fill), a least-recently-used (lru) policy determines which cache line way receives the requested line. the index, determined by the instruction or data address, selects a congruence class. within a congruence class, the most recently accessed line (in either way a or way b) is retained and the lru bit in the associated tag array marks the other line as lru. the lru line then receives the requested instruction or data lwords. after the cache line fill, the lru bit is set to identify as lru the line opposite the line just filled. to determine a real cache array size, use an mfspr instruction to read the instruction cache debug data register (icdbdr) after a system reset, before executing an icread instruction. the size information is in the following icdbdcr fields: the effective size of the cache arrays can be changed, using fields in the cache debug control register (cdbcr), to model the performances of various cache array sizes. section 25.7, ? icu and dcu performance modeling, ? on page 25-14, describes how effective cache array sizes are changed. note that effective cache array sizes cannot exceed the corresponding actual cache array sizes. 25.2 icu overview the icu manages data transfers between external cacheable memory and the instruction queue in the execution unit. figure 25-1 shows the relationship between the icu and instruction queue. table 25-3. cache sizes, tag fields, and lines cache size m (tag field bits) n (cache array lines) 0 kb ?? 2 kb 22 64 4 kb 21 128 0:3 icsz icu array size 0 kb 2 kb 4 kb 8 kb 16 kb 4:7 dcsz dcu array size 0 kb 2 kb 4 kb 8 kb 16 kb section 25 icu overview iop 480 cpu cache operations iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 25-3 section 25 ? cpu cache ops the bypass path handles instructions in cache- inhibited memory and improves performance during line fill operations. if a request from the fetcher obtains an entire line from memory, the queue does not have to wait for the entire line to reach the cache. the target lword (the lword requested by the fetcher) is sent on the bypass path to the queue while the line fill proceeds, even if the selected line fill order is not target-lword-first. instructions from cacheable memory regions are copied into the instruction cache, from which they can be accessed by the fetcher far more quickly than they can be obtained from memory. cache lines are loaded either target-lword-first or sequentially, or in any order. target-lword-first fills start at the requested lword, continue to the end of the line, and then wrap to fill the remaining lwords at the beginning of the line. sequential fills start at the first lword of the cache line and proceed sequentially to the last lword of the line. cache line fills always run to completion, even if the instruction stream branches away from the rest of the line. as requested instructions are received, they go to the fetcher before the line fills in the cache. the filled line is always placed in the icu; if an external memory subsystem error occurs during the fill, the line is marked as invalid. during a clock cycle, the icu can send one instruction to the fetcher. 25.2.1 instruction cacheability control when instruction address translation is disabled (the ir field of the machine state register (msr) is 0), instruction cacheability is controlled by the instruction cache cacheability register (iccr). each bit in the iccr (iccr[s0:s31]) controls the cacheability of a 128 mb region (see section 27.8, ? real-mode storage attribute control, ? on page 27-13). if iccr[s n ] = 1, caching is enabled for the specified region. when instruction address translation is enabled (msr[ir] = 1), instruction cacheability is controlled by the i storage attribute in the translation lookaside buffer (tlb) entry for the memory page. if tlb_entry[i] = 1, caching is inhibited; otherwise caching is enabled. cacheability is controlled separately for each page, which can range in size from 1 kb to 16 mb. section 27.3, ? translation lookaside buffer (tlb), ? on page 27-2, describes the tlb. the performance of the iop 480 cpu is significantly lower while executing in cache-inhibited regions. execute pfb1 pfb0 decode addresses from fetcher instruction arrays ta g arrays addresses instructions figure 25-1. instruction flow bypass path instruction queue section 25 iop 480 cpu cache operations icu overview iop 480 data book r2.0 25-4 ? 2000 plx technology, inc. all rights reserved. following system reset, address translation is disabled and all iccr bits are reset to 0 so that no memory regions are cacheable. before regions can be designated as cacheable in the iccr, it is necessary to execute the iccci instruction n times (once for each congruence class in the cache array). this invalidates all congruence classes before enabling the cache. the iccr can then be reconfigured appropriately and the icu can begin normal operation. 25.2.2 icu coherency the icu does not ? snoop ? external memory or the dcu. programmers must follow special procedures for icu synchronization when self-modifying code is used or if a peripheral device updates memory containing instructions. the following code example illustrates the necessary steps for self-modifying code. this example assumes that addr1 is both data and instruction cacheable. 25.2.3 dcu overview the dcu manages data transfers between external cacheable memory and the general-purpose registers in the execution unit. a bypass path handles data operations in cache- inhibited memory and improves performance during line fill operations. data from cacheable memory regions are copied into lines in the data cache, either target-lword-first or sequentially, or in any other order. target-lword-first fills start at the requested lword, continue to the end of the line, and then wrap to fill the remaining lwords at the beginning of the line. sequential fills start at the first lword of the cache line and proceed sequentially to the last lword of the line. in both types of fills, the line is marked valid when the fourth lword is filled. gprs receive the requested byte, word, or lword of data immediately upon being received from main storage using a cache bypass mechanism. as requested data is received, it is forwarded to the target at the same time the data is written to the cache. the filled line is always placed in the dcu. the dcu can send a byte, word, or lword to the target in two clock cycles. cache flushing (copying data in the cache that has been updated by the processor to main storage) and filling (loading requested data from main storage into the cache) are triggered by load, store and cache control instructions executed by the processor. cache flushes are always sequential, starting at the first lword of the cache block and proceeding sequentially to the end of the block. cache lines are always completely flushed or filled, even if the program does not request the rest of the bytes in the line, or if a bus error occurs after a bus interface unit accepts the request for the line fill. if a bus error occurs during a line fill, the line is filled and the data is marked valid. however, the line can contain invalid data, and a machine check exception occurs. the dcu supports byte-writeability to improve the performance of byte and word store operations. 25.2.4 dcu write strategies dcu operations can use write-back or write-through strategies to maintain coherency with external cacheable memory. the write-back strategy updates only the data cache, not external memory, during store operations. only modified data lines are flushed to external memory, and then only when necessary to free up locations for incoming lines, or when lines are explicitly flushed using dcbf or dcbst instructions. cache flushes are always sequential, starting at the first lword of the cache block and proceeding sequentially to the end of the block. the write-back strategy minimizes the amount of external bus activity and avoids unnecessary contention for the external bus between the icu and the dcu. stw regn, addr1 # the data in regn is to become an instruction at addr1 dcbst addr1 # forces data from the data cache to memory sync # wait until the data actually reaches the memory icbi addr1 # the previous value at addr1 might already be in the instruction cache; invalidate it in the cache isync # the previous value at addr1 may already have been pre-fetched into the queue; invalidate the queue so that the instruction must be re-fetched section 25 cache instructions iop 480 cpu cache operations iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 25-5 section 25 ? cpu cache ops the write-back strategy is contrasted with the write-through strategy, in which stores are written simultaneously to the cache and to external memory. a write-through strategy can simplify maintaining coherency between cache and memory. however, because the dcu cannot accept a new command until such a store completes in external memory, performance is generally slower. when data address translation is disabled (msr[dr] = 0), the write strategy is controlled by the data cache write-thru register (dcwr). each bit in the dcwr (dcwr[w0:w31]) controls the write strategy of a 128 mb storage region (see section 27.8, ? real-mode storage attribute control, ? on page 27-13). if dcwr[w n ] = 0, the write-back strategy is enabled for the specified region; if dcwr[w n ] = 1, the write- through strategy is enabled. when data address translation is enabled (msr[ir] = 1), the write strategy is controlled by the w storage attribute in the tlb entry for the memory page. if tlb_entry[w] = 0, the write-back write strategy is selected. if tlb_entry[w] = 1, the write-through write strategy is selected. the write strategy is controlled separately for each page, which can range in size from 1 kb to 16 mb. section 27.3, ? translation lookaside buffer (tlb), ? on page 27-2, describes the tlb. note: powerpc architecture does not support memory models in which write-through is enabled and caching is inhibited. the dcu can control whether a cache line is allocated in the cache on store misses. the cache debug control register (cdbcr) write-on-allocate (woa) bit controls the allocate-on-write policy. if cdbcr[woa] = 0, store misses cause a line fill. if cdbcr[woa] = 1, store misses do not cause a line fill, but result in a non-cacheable store. 25.2.5 data cacheability control when data address translation is disabled (msr[dr] = 0), data cacheability is controlled by the data cache cacheability register (dccr). each bit in the dccr (dccr[s0:s31]) controls the cacheability of a 128 mb region (see section 27.8, ? real-mode storage attribute control, ? on page 27-13). if dccr[s n ] = 1, caching is enabled for the specified region. when data address translation is enabled (msr[dr] = 1), data cacheability is controlled by the i bit in the tlb entry for the memory page. if tlb_entry[i] = 1, caching is inhibited; otherwise caching is enabled. cacheability is controlled separately for each page, which can range in size from 1 kb to 16 mb. section 27.3, ? translation lookaside buffer (tlb), ? on page 27-2, describes the tlb. the performance of the iop 480 cpu is significantly lower while executing in cache-disabled regions. following system reset, address translation is disabled and all dccr bits are reset to 0 so that no memory regions are cacheable. before regions can be designated as cacheable in the dccr, it is necessary to execute the dccci instruction n times (once for each congruence class in the cache array). this invalidates all congruence classes before enabling the cache. the dccr can then be reconfigured appropriately and the icu can begin normal operation. note: if a data block corresponding to the effective address (ea) exists in the cache, but the ea is non-cacheable, loads and stores (including dcbz ) to that address are considered programming errors (the cache block should previously have been flushed). the only instructions that can legitimately access such an ea in the data cache are the cache management instructions dcbf , dcbi , dcbst , dcbt , dcbtst , dccci , and dcread . 25.2.6 dcu coherency the dcu does not provide snooping. application programs must carefully use cache-inhibited regions and cache control instructions to ensure proper operation of the cache in systems where external devices can update memory. 25.3 cache instructions for detailed descriptions of the instructions described in the following sections, see section 28, ? iop 480 cpu instruction set. ? in the instruction descriptions, the term ? block ? is synonymous with cache line. a block is the unit of storage operated on by all cache block instructions. section 25 iop 480 cpu cache operations cache instructions iop 480 data book r2.0 25-6 ? 2000 plx technology, inc. all rights reserved. 25.3.1 icu instructions the following instructions control instruction cache operations: 25.3.2 idcu instructions data cache flushes and fills are triggered by load, store and cache control instructions. cache control instructions are provided to fill, flush, or invalidate cache blocks. the following instructions control data cache operations: icbi instruction cache block invalidate invalidates a cache block. if the data cache unlock exception is enabled, a data storage exception occurs, regardless of whether the target line is locked. icbt instruction cache block touch initiates a block fill, enabling a program to begin a cache block fetch before the program needs an instruction in the block. the program can subsequently branch to the instruction address and fetch the instruction without incurring a cache miss. this is a privileged-mode instruction. iccci instruction cache congruence class invalidate invalidates a congruence class (in the iop 480 cpu, both ways). this is a privileged-mode instruction. icread instruction cache read reads either an instruction cache tag entry or an instruction lword from an instruction cache line, typically for debugging. bits in the cdbcr control instruction behavior (see ? cache control and debugging features ? on page 25-7.). this is a privileged-mode instruction. dcba data cache block allocate speculatively establishes a line in the cache and marks the line as modified. if the line is not currently in the cache, the line is established and marked as modified without actually filling the line from external memory. if the line is marked as either non-cacheable or write-through, or if the target is not in the cache and the data cache lock-out exception is enabled, dcba is treated as a no-op. if dcba references a non-cacheable address, or cdbcr[dlxe] = 1 and msr = 1 (which would otherwise cause a data storage exception), dcba is treated as a no-op. if dcba references a cacheable address, write-through required (which would otherwise cause an alignment exception), or cdbcr[dlxe] = 1 (which would otherwise cause a data storage exception), dcba is treated as a no-op. dcbf data cache block flush flushes a line, if found in the cache and marked as modified, to external memory; the line is then marked invalid. if the line is found in the cache and is not marked modified, the line is marked invalid but is not flushed. this operation is performed regardless of whether the address is marked cacheable. if the data cache unlock exception is enabled, a data storage exception occurs, regardless of whether the target line is locked. dcbi data cache block invalidate invalidates a block, if found in the cache, regardless of whether the address is marked cacheable. any modified data is not flushed to memory. this is a privileged-mode instruction. dcbst data cache block store stores a block, if found in the cache and marked as modified, into external memory; the block is not invalidated but is no longer marked as modified. if the block is marked as not modified in the cache, no operation is performed. this operation is performed regardless of whether the address is marked cacheable. section 25 cache control and debugging features iop 480 cpu cache operations iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 25-7 section 25 ? cpu cache ops 25.4 cache control and debugging features registers and instructions are provided to control cache operation and to resolve debug cache problems. for icu debug, the icread instruction and the instruction cache debug data register (icdbdr) are provided (see section 25.4.1, ? icu debugging, ? on page 25-9). for dcu debug, the dcread instruction is provided (see section 25.4.2, ? dcu debugging, ? on page 25-10). the cdbcr controls the behavior of the icread and the dcread instructions. register 25-1 illustrates the cdbcr bits. dcbt data cache block touch fills a block with data, if the address is cacheable and the data is not already in the cache. if the address is non-cacheable, this instruction is a no-op. dcbtst data cache block touch for store implemented identically to the dcbt instruction in the iop 480 cpu for compatibility with compilers and other tools. dcbz data cache block set to zero fills a line in the cache with zeros and marks the line as modified. if the line is not currently in the cache (and the address is marked as cacheable and non- write-through), the line is established, filled with zeros, and marked as modified without actually filling the line from external memory. if the line is marked as either non-cacheable or write-through, an alignment exception results. if the target is not in the cache and the data cache lock-out exception is enabled, a data storage exception occurs. dccci data cache congruence class invalidate invalidates a congruence class (in the iop 480 cpu, both ways). this is a privileged-mode instruction. dcread data cache read reads either a data cache tag entry or a data lword from a data cache line, typically for debugging. bits in the cdbcr control instruction behavior. (see ? cache control and debugging features ? on page 25-7.) this is a privileged-mode instruction. section 25 iop 480 cpu cache operations cache control and debugging features iop 480 data book r2.0 25-8 ? 2000 plx technology, inc. all rights reserved. register 25-1. cache debug control register (cdbcr) 0:1 dsd dcu size disable 00 the connected cache size is the real cache size. 01 the connected cache size is the real cache size/2. 10 the connected cache size is the real cache size/4. 11 the connected cache size is the real cache size/8. see table 25-5 for more information on bit settings for various real and effective cache sizes. 2:3 isd icu size disable 00 the connected cache size is the real cache size. 01 the connected cache size is the real cache size/2. 10 the connected cache size is the real cache size/4. 11 the connected cache size is the real cache size/8. see table 25-5 for more information on bit settings for various real and effective cache sizes. 4:17 reserved 18 dwda delayed write data acknowledge 0 normal processor write data acknowledge 1 write data acknowledge is delayed one processor clock cycle see section 25.6.5, ? core clock frequency and write data acknowledge, ? on page 25-14. 19 woa write-on-allocate 0 all store misses result in a line fill. 1 store misses do not cause a line fill, but result in a non-cacheable store. 20 ddk disable data-side compression 0 use k storage attribute to specify data compression 1 disable data-side compression, regardless of k attribute 21 ocm instruction-side ocm (iocm) mode 0 iocm is presented only with cacheable fetches 1 iocm is presented with cacheable and non- cacheable fetches 22 ldbe load debug enable 0 load data is invisible on data-side ocm. 1 load data is visible on data-side ocm. 23 dlxe dcu lock-out exception enable 0 dcu lock-out exception is disabled. 1 dcu lock-out exception is enabled. 24 iuxe icu unlock exception enable 0 icu unlock exception is disabled. 1 icu unlock exception is enabled. 25 duxe dcu unlock exception enable 0 dcu unlock exception is disabled. 1 dcu unlock exception is enabled. 26 lke lock enable 0 line locking is disabled. 1 line locking is enabled. 27 cis cache information select 0 information is cache data. 1 information is cache tag. 28:30 reserved 26 27 28 30 31 cis 25 24 23 4 lke duxe dlxe iuxe 22 20 19 18 woa 21 ddk ocm 0 12 3 dsd isd 17 dwda ldbe cws section 25 cache control and debugging features iop 480 cpu cache operations iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 25-9 section 25 ? cpu cache ops 25.4.1 icu debugging the icread instruction enables the reading of the instruction cache entries for the congruence class specified by ea m ::27 , where m is the number of address bits in the tag field. the cache information is read into the icdbdr; from there it can subsequently be moved, using a mfspr instruction, into a gpr. register 25-2 illustrates the icdbdr bits. if cdbcr[cis] = 0, the data is an lword of icu data from the addressed line, specified by ea 28:29 . if cdbc[cws] = 0, the data is from the a-way; otherwise; the data from the b-way. if cdbcr[cis] = 1, the cache information is the cache tag. if cdbcr[cws] = 0, the tag is from the a-way; otherwise, the tag is from the b-way. icu tag information is placed into the icdbdr as shown. : register 25-2. instruction cache debug data register (icdbdr) 0:31 instruction cache information from icread 0: m ? 1 tag cache tag see table 25-1 for information on the size of this variable- length field. m :24 reserved the size of this field depends on the size of the tag field. 25 lk cache line lock 0 unlocked 1 locked 26 reserved 27 v cache line valid 0not valid 1 valid 28:30 reserved 31 lru least recently used (lru) 0a-way lru 1b-way lru section 25 iop 480 cpu cache operations cache control and debugging features iop 480 data book r2.0 25-10 ? 2000 plx technology, inc. all rights reserved. the instruction pipeline does not wait for data from an icread instruction to arrive before attempting to use the contents the icdbcr. the following code sequence ensures proper results: icread r5,r6# read cache information isync# ensure completion of icread mficdbdr r7# move information to gpr 25.4.2 dcu debugging the dcread instruction provides a debugging tool for reading the data cache entries for the congruence class specified by ea m :27 , where m is the number of address bits in the tag field. the cache information is read into a gpr. if cdbcr[cis] = 0, the data is an lword of dcu data from the addressed line, specified by ea 28:29 . if cdbc[cws] = 0, the data is from the a-way; otherwise; the data is from the b-way. if cdbcr[cis] = 1, the cache information is the cache tag. if cdbc[cws] = 0, the tag is from the a-way; otherwise the tag is from the b-way. dcu tag information is placed into the gpr as shown: note: a ? dirty ? cache line is one which has been accessed by a store instruction after it was established, and can be inconsistent with external memory. 0: m ? 1 tag cache tag tag size is determined by cdbcr[dsd]. see section 25.7, ? icu and dcu performance modeling, ? on page 25-14, for more information. m :24 reserved the size of this field depends on the size of the tag field. 25 lk cache line locked 0 unlocked 1 locked 26 d cache line dirty 0 not dirty 1 dirty 27 v cache line valid 0not valid 1 valid 28:30 reserved 31 lru least recently used (lru) 0a-way lru 1b-way lru section 25 cache line locking iop 480 cpu cache operations iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 25-11 section 25 ? cpu cache ops 25.5 cache line locking lines in the icu and dcu can be locked. locked lines remain in the cache arrays until they are explicitly unlocked. locking frequently used instructions and data in the respective cache units can ensure that the instructions and data are available as quickly as possible. if a line is locked in a congruence class in the icu or dcu, that line does not participate in the lru replacement for that congruence class. typically, on a cache miss, the lru unlocked line is replaced. except for the dcba , dcbt , dcbtst , dcbz , and icbt instructions, a load, store, or cache instruction that misses in the cache, and references a locked-out congruence class (a congruence class in which both lines are locked), behaves as if the instruction references non-cacheable storage. the dcbt , dcbtst , and icbt instructions do not update the cache in this case, but the plb appears to have performed a line fill. the dcba and dcbz instructions behave as described in section 25.5.2, ? unlocking lines in the icu and dcu, ? on page 25-11. 25.5.1 locking lines in the icu and dcu cache arrays line locking is controlled by the cdbcr[lke] bit (see figure 25-1). to lock lines in the cache units, an instruction sequence, executing in privileged mode, sets cdbcr[lke] = 1 to enable locking, and establishes cache lines as needed, using a dcba , dcbt , dcbtst , dcbz , or icbt instruction as appropriate to establish and lock each line. locked lines are marked as locked in the appropriate cache tag array. the instruction sequence can then set cdbcr[lke] = 0, disabling line locking, and return the processor to user mode, making the locked lines available to application code. some instructions that establish cache lines in the dcu are non-privileged. however, the enabling and disabling of cache line locking requires the use of the privileged mtcdbcr instruction (actually, mtcdbcr is an extended mnemonic for the mtspr instruction). note that cache line locking should be performed thoughtfully; limiting the cache line locking window in a privileged code sequence as described is recommended. note: the mtcdbcr extended mnemonic is not context- or execution-synchronizing. software must place appropriate synchronization instructions before and after an mtcdbcr to ensure that the locking instructions execute in the proper context. 25.5.2 unlocking lines in the icu and dcu several instructions unlock locked cache lines: the privileged instructions dccci , dcbi , and iccci ; and the non-privileged instructions dcba , dcbf , dcbz , and icbi . in user mode , the behavior of the non-privileged unlocking cache instructions depends upon the settings of the cdbcr[dlxe], cdbcr[iuxe], and cdbcr[duxe] bits. the following bits are associated with data cache instructions: dcba the cdbcr[dlxe] field (dlxe stands for data- cache lock-out exception enable) controls whether an attempt to replace an locked data cache line causes dcba to be treated as a no-op. assume that the dcba instruction hits in the cache, that the w (write-through) and i (cacheability) storage attributes for the target line are 0, and that the target line is a valid cache line. assume further that the target line is locked. if the dlxe field is enabled (cdbcr[dlxe] = 1), dcba is treated as a no-op. if the dlxe field is disabled (cdbcr[dlxe] = 0), the target line is unlocked and removed. a new line is established. if cdbcr[lke] = 1, the newly established line is locked. dcbf the cdbcr[duxe] field (duxe stands for data- cache unlock exception enable) controls whether an attempt to flush a locked data cache line causes an exception. if the field is disabled (cdbcr[duxe] = 0), the target line is flushed and unlocked, and no exception is taken. if the field is enabled (cdbcr[duxe] = 1), dcbf causes a data storage exception. the exception occurs regardless of whether the target line is locked. dcbz the cdbcr[dlxe] field controls whether an attempt to replace an locked data cache line causes an exception. section 25 iop 480 cpu cache operations dcu performance iop 480 data book r2.0 25-12 ? 2000 plx technology, inc. all rights reserved. assume that the dcbz instruction hits in the cache, that the w and i storage attributes for the target are 0, and that the target is a valid cache line. assume further that the target line is locked. if the dlxe field is enabled (cdbcr[dlxe] = 1), a data storage exception occurs if the target is not in the cache.the exception occurs regardless of whether the target congruence class is locked-out. if the dlxe field is disabled (cdbcr[dlxe] = 0), the target line is unlocked and removed. a new line is established. if cdbcr[lke] = 1, the newly established line is locked. no exception is taken. if dcbz references a non-cacheable address (alignment exception), and cdbcr[dlxe] = 1 (data storage exception), the alignment exception takes priority. if dcbz references a cacheable address, write- through required (alignment exception), and cdbcr[dlxe] = 1 (data storage exception), the data storage exception takes priority. icbi the cdbcr[iuxe] field (iuxe stands for instruction-cache unlock exception enable) controls whether an attempt to invalidate a locked instruction cache line causes an exception. if the field is disabled (cdbcr[iuxe] = 0), the target line is invalidated and unlocked, and no exception is taken. if the filed is enabled (cdbcr[iuxe] = 1), a data storage exception occurs. the exception occurs regardless of whether the target line is locked. in privileged mode , no data storage exceptions occur when the privileged and non-privileged cache instructions execute, regardless of the setting of the locked-out and unlocked exception bits in the cdbcr. dcba dcba replaces the lru unlocked line in a congruence class, regardless of whether the congruence class is locked out. dcbz dcbz replaces the lru unlocked line in a congruence class, regardless of whether the congruence class is locked out. 25.6 dcu performance dcu performance depends upon the application and the design of the attached external bus controller, but, in general, cache hits complete in two cycles without stalling the cpu pipeline. under certain conditions and limitations of the dcu, the pipeline stalls (stops executing instructions) until the dcu completes current operations. several factors affect dcu performance, including: pipeline stalls dcu priority simultaneous cache operations sequential cache operations 25.6.1 pipeline stalls the cpu issues commands for cache operations to the dcu. if the dcu can immediately perform the requested cache operation, no pipeline stall occurs. in some cases, however, the dcu cannot immediately perform the requested cache operation, and the pipeline stalls until the dcu can perform the pending cache operation. a load miss or a load to a storage region marked as non-cacheable always stalls the pipeline until the load is aborted or the requested load data becomes available to the cpu, enabling it to resume instruction execution. other pipeline stalls occur when the cpu issues a command for a cache operation while one of the following cache operations, previously requested, is in progress: a line fill resulting from a store two pending line flushes a dcbt instruction a store to a region of memory marked as write-through on-chip memory (ocm) presenting the dsocm_dcustoreack_hold signal a store miss stalls the pipeline only when the cpu issues a request for a cache operation while the line fill resulting from the store miss is in progress. when the line fill finishes, instruction execution resumes. section 25 dcu performance iop 480 cpu cache operations iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 25-13 section 25 ? cpu cache ops multiple line flushes can stall the pipeline. the dcu can flush up to two lines to memory before stalling the pipeline when the cpu issues another command for a cache operation before the second line flush begins. when a dcbt instruction results in a cache miss and is followed by another cache operation, the pipeline stalls until the line fill resulting from the dcbt miss finishes. then, instruction execution resumes. when a storage region is marked as write-through, all stores, when followed immediately by another cache operation, stall the pipeline until the cycle after the plb acknowledges the store data. this results in at least a one-cycle delay to complete the write through. however, if a store to a storage region marked as write-through misses, and the device supplying the data for the resulting line fill has a store queue, the store queue holds the store data until the line fill finishes. in this case, the write-through appears to complete before the line fill. the pipeline stalls when ocm (if implemented in the processor core) asserts dsocm_dcustoreack_hold for loads/stores. for loads that are held, the pipeline stalls until the load is completed or aborted. if a store is held and an immediately subsequent cache operation is requested, the pipeline stalls until the store finishes and ocm deasserts dsocm_dcustoreack_hold. 25.6.2 cache operation priorities the dcu uses a priority signal, dcu_plbpriority, to improve performance when pipeline stalls occur. when the pipeline is stalled because of a data cache operation, the dcu asserts the priority signal to the external bus. dcu_plbpriority tells the external bus that the dcu requires immediate service, and is valid only when the data cache is requesting access to the plb interface. dcu_plbpriority is asserted for all loads that require external data, or when the data cache is requesting the external bus and stalling an operation that is being presented to the data cache. table 25-4 on page 25-14 provides examples of when priority is asserted and de-asserted. 25.6.3 simultaneous cache operations some cache operations can occur simultaneously to improve dcu performance. for example, when a line must be allocated in the data cache and another line flushed to memory, the operations can be performed simultaneously. a line fill caused by a store miss to a storage region marked as write-through, and a load to a non-cacheable storage region marked followed by a line flush, can also be performed simultaneously. support for simultaneous operations depends upon the configuration of the external bus. 25.6.4 sequential cache operations some common cache operations, when performed sequentially, can limit dcu performance: sequential loads/stores to non-cacheable storage regions, sequential line fills, and sequential line flushes. in the case of sequential cache hits, the most commonly occurring operations, the dcu loads or stores data every two cycles. in such cases, the dcu does not affect performance. however, when a load from a non-cacheable storage region is accepted by the plb in the same cycle as the load request, and the load data is presented in the next cycle, three cycles are required to complete the load. the following equation determines the number of cycles required to complete a series of sequential loads from non-cacheable storage regions: total cycles = (2 + ( car + cgd )) number of loads where car is the number of cycles required to accept the load request (if the request is accepted in the same cycle, car = 0) and cgd is the number of cycles required to get the load data after the request is accepted. similarly, when a store to a non-cacheable storage region is accepted and the store data is presented in the same cycle, at least three cycles are required to complete the store. section 25 iop 480 cpu cache operations icu and dcu performance modeling iop 480 data book r2.0 25-14 ? 2000 plx technology, inc. all rights reserved. the following equation determines the number of cycles required to complete a series of sequential stores to storage regions marked as non-cacheable: total cycles = (3 + ( car + cad )) number of stores where car is the number of cycles required to accept the store request (if the request is accepted in the same cycle, car = 0) and cad is the number of cycles required to acknowledge the store data after the request is accepted. sequential line fills can limit dcu performance. line fills occur when a load/store or dcbt instruction misses in the cache. sequential line flushes from the dcu to main memory also limit dcu performance. flushes occur when a line fill replaces a valid line that is marked dirty (modified), or when a dcbf instruction flushes a specific line. if two flushes are pending, the dcu stalls any new data cache operations until the first flush finishes and the second begins. 25.6.5 core clock frequency and write data acknowledge to sustain performance at the maximum core clock frequency for some bus interface designs, cdbcr[dwda] must be set to 1, which delays write data acknowledge by one core clock cycle. this, in turn, causes line flushes and non-cacheable stores to take an additional core clock cycle. setting cdbcr[dwda] = 1 relaxes the timing requirements for the plb_dcuwrdack signal, enabling system designs to sustain the maximum core clock frequency at the expense of slower line flushes and non-cacheable stores even when a bus interface design cannot meet the timing requirements for plb_dcuwrdack. when cdbcr[dwda] = 1, plb_dcuwrdack is latched before being used by the dcu control logic. 25.7 icu and dcu performance modeling the effective size of the icu and dcu can be changed to model how various cache sizes affect performance, depending on the settings of the cdbcr[isd] and cdbcr[dsd] fields. to model smaller cache sizes, the size of the tag field (specified by m ) is increased; one or more bits that were formerly part of the index are treated as bits in the tag field. the number of bits treated differently depends upon the desired cache size. note that if the effective cache size and the real cache size are the same, tag and index bits are not treated differently. table 25-5 shows how the cdbcr[isd] and cdbcr[dsd] fields determine effective icu and dcu sizes, respectively. an ? x ? in the table indicates a don ? t care. table 25-4. priority changes with different data cache operations instruction priority next instruction priority any load 1 n/a n/a any store 0 any other cache operation when the line fill was not accepted on the plb interface 1 dcbf 0 any cache hit 0 dcbf / dcbst 0 load non-cache when requesting access to the plb interface 1 dcbf / dcbst 0 any line fill when dcbf / dcbst requests access to the plb interface 1 dcbf / dcbst 0 dcbf / dcbst when the first dcbf / dcbst requests access to the plb interface 1 dcbt 0 any cache hit 0 dcbt 0 any other cache operation when a line fill was not accepted on the plb interface 1 dcbi / dccci / dcbz 0 n/a n/a section 25 icu and dcu performance modeling iop 480 cpu cache operations iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 25-15 section 25 ? cpu cache ops table 25-5. cdbcr[dsd], cdbcr[isd], and effective cache size real cache size cdbcr[dsd] cdbcr[isd] effective cache size tag field index m 16 kb 00 00 16 kb 0:18 19:27 19 01 01 8 kb 0:19 20:27 20 10 10 4 kb 0:20 21:27 21 11 11 2 kb 0:21 22:27 22 8 kb 00 00 8 kb 0:19 20:27 20 01 01 4 kb 0:20 21:27 21 1x 1x 2 kb 0:21 22:27 22 4 kb 00 00 4 kb 0:20 21:27 21 x1, 1x x1, 1x 2 kb 0:21 22:27 22 2 kb xx xx 2 kb 0:21 22:27 22 iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 26-1 section 26 ? debug & jtag 26 iop 480 cpu debugging and jtag facilities the debug facilities of the iop 480 cpu include support for: debug modes for debugging during hardware and software development debug events that allow developers to control the debug process debug registers control the debug modes and debug events. the debug registers are accessed through software running on the processor or through a jtag debug port. the debug interface is the jtag debug port. the jtag debug port can also be used for board test. the debug modes, events, controls, and interface provide a powerful combination of debug facilities for a wide range of hardware and software development tools. 26.1 development tool support the os open real-time operating system debugger product from ibm is an example of an operating system-aware debugger, implemented using software traps. the riscwatch product from ibm is an example of a development tool that uses the external debug mode, debug events, and the jtag debug port to implement a hardware and software development tool. 26.2 debug modes there are two debug modes in the iop 480 cpu; each supports a type of debug tool commonly used in embedded systems development: internal debug mode, which supports rom monitors external debug mode, which supports emulators both modes can be enabled simultaneously; the debug control register (dbcr) controls the internal and external debug modes. 26.2.1 internal debug mode internal debug mode supports access to all architected processor resources, setting hardware and software breakpoints, and monitoring processor status. in this mode, debug events generate debug exceptions, which can interrupt normal program flow so that monitor software can collect processor status and alter processor resources. internal debug mode relies on exception handling software at a dedicated interrupt vector and an external communications path to debug software problems. this mode, used while the processor executes instructions, enables debugging of operating system or application programs. in this mode, debugger software is accessed through a communications port, such as a serial port, external to the processor core. 26.2.2 external debug mode external debug mode provides access to all architected processor resources and supports stopping, starting, and stepping the processor, setting hardware and software breakpoints, and monitoring processor status. in this mode, debug events cause the processor to become architecturally frozen. while the processor is frozen, normal instruction execution stops and all architected processor resources can be accessed and altered. external bus activity continues in external debug mode. the jtag mechanism can also pass instructions to the processor for execution, allowing a jtag debug tool to display and alter processor resources, including memory. the jtag mechanism prevents the occurrence of a privileged exception when a privileged instruction is executed while the processor is in user mode. storage access control by a memory management unit (mmu) remains in effect while in external debug mode; the debugger may need to modify msr or tlb values to access protected memory. external debug mode relies only on internal processor resources, so it can be used to debug both system hardware and software problems. this mode can also be used for software development on systems without a control program, or to debug control program problems. access to the processor, while in external debug mode, is through the jtag debug port. section 26 iop 480 cpu debugging and jtag facilities processor control iop 480 data book r2.0 26-2 ? 2000 plx technology, inc. all rights reserved. 26.3 processor control the iop 480 cpu provides the following debug facilities for processor control. not all facilities are available in all debug modes. 26.4 processor status the processor execution status, exception status, and most recent reset can be monitored. 26.5 debug events debug events, enabled by the dbcr and recorded in the dbsr, trigger debug operations. a debug event occurs when an event listed in table 26-1 on page 26-3 is detected. the debug operation is performed after the debug event. in internal debug mode, the processor generates a debug exception when a debug event occurs. in external debug mode, the processor stops when a debug event occurs. when internal and external debug mode are both enabled, the processor also stops on any debug event. when external and internal debug mode are both disabled, debug events are recorded in the dbsr, but no action is taken. 26.6 debug registers several debug registers, available to debug tools running on the processor, are not intended for use by application code. debug tools control debug resources such as debug events. application code that uses debug resources can cause the debug tools to fail, as well as other unexpected results, such as program hangs and processor resets. application code should not use the debug resources, including the debug registers. instruction step processor is stepped one instruction at a time, while stopped, using jtag debug port. instruction stuff while the processor is stopped, instructions can be stuffed into the processor and executed using jtag debug port. halt processor can be stopped by activating an external halt signal on an external event, such as a logic analyzer trigger. this signal freezes the processor architecturally. while frozen, normal instruction execution stops and all architected processor resources can be accessed and altered using jtag debug port. normal execution resumes when the halt signal is deactivated. stop processor can be stopped using jtag debug port. activating a stop causes the processor to become architecturally frozen. while frozen, normal instruction execution stops and architected processor resources can be accessed and altered using jtag debug port. normal execution resumes when this bit is reset. reset external reset signal, jtag debug port, or debug control register (dbcr) can request a reset of the processor. jtag debug port can request core, chip, and system resets. debug events a debug event triggers a debug operation. the operation depends on the debug mode. for more information and a list of debug events, see section 26.5, ? debug events, ? on page 26-2. freeze timers jtag debug port or the dbcr can control timer resources. the timers can be enabled to run, freeze always, or freeze on a debug event. trap instructions the trap instructions tw and twi can be used, with debug events, to implement software breakpoints. execution status jtag debug port can monitor processor execution status to determine whether the processor is stopped, waiting, or running. exception status jtag debug port can monitor the status of pending synchronous exceptions. most recent reset jtag debug port can read the debug status register (dbsr) to determine the type of the most recent reset. section 26 debug registers iop 480 cpu debugging and jtag facilities iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 26-3 section 26 ? debug & jtag 26.6.1 debug control register (dbcr) dbcr can enable debug events, reset the processor, control timer operation during debug events, enable jtag interrupts, and set the processor debug mode. application code should not use dbcr. table 26-1lists debug events. register 26-1 illustrates the dbcr bits. table 26-1. debug events event description exception this debug event occurs after an exception. exception debug events always include the non-critical class of exceptions unless in internal debug mode. when only internal debug mode is enabled, the critical class of exceptions are not included. this debug event is disabled if the machine state register (msr) field msr[de] = 0 and the dbcr field dbcr[idm] = 1. branch taken this debug event occurs before the execution of a branch instruction that is determined to be taken. this debug event is disabled if msr[de] = 0 and dbcr[idm] = 1. data address compare (dac) this debug event occurs before the execution of an instruction that accesses a data address that matches the contents of the data address compare register (dac1). the dbcr can set the dac to occur on reads/writes from byte addresses, or from any byte within word, lword, or qword addresses. instruction address compare (iac) this debug event occurs before the execution of an instruction at an address that matches the contents of the instruction address compare register (iac1). instruction completion this debug event occurs after the completion of any instruction. this debug event is disabled if msr[de] = 0 and dbcr[idm] = 1. tr a p this debug event occurs before the execution of a trap instruction where the conditions are such that the trap occurs. unconditional this debug event occurs immediately upon being set by the jtag debug port or the xxx_cpuunconddebugevent signal. this signal supports user-defined debug events, using asic logic external to the iop 480 cpu. section 26 iop 480 cpu debugging and jtag facilities debug registers iop 480 data book r2.0 26-4 ? 2000 plx technology, inc. all rights reserved. register 26-1. debug control register (dbcr) 0 edm external debug mode 0 disable 1 enable 1 idm internal debug mode 0 disable 1 enable 2:3 rst reset 00 no action 01 core reset 10 chip reset 11 system reset note: writing 01, 10, or 11 to this field causes a processor reset request. 4 ic instruction completion debug event 0 disable 1 enable instruction completion does not cause a debug event if msr[de] = 0 in internal debug mode 5 bt branch taken debug event 0 disable 1 enable branch taken does not cause a debug event if msr[de] = 0 in internal debug mode 6 ede exception debug event 0 disable 1 enable critical exceptions do not cause debug events if msr[de] = 0 in internal debug mode 7 tde trap debug event 0 disable 1 enable 8:12 reserved 13 ft freeze timers on debug event 0 free-run timers 1 freeze timers 14 ia1 instruction address compare 1 enable 0 disable 1 enable 15 reserved 16 d1r dac read enable 0 disable 1 enable 17 d1w dac write enable 0 disable 1 enable 18:19 d1s dac size 00 compare all bits 01 ignore the least significant bit (lsb) 10 ignore the two lsbs 11 ignore the four lsbs exact address compare byte within word address compare byte within lword address compare qword address compare 20:31 reserved 0 1 2 3 4 5 6 7 13 14 812 edm rst bt tde ia1 ede ic idm ft 16 17 18 19 20 d1w d1r d1s 15 31 section 26 debug registers iop 480 cpu debugging and jtag facilities iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 26-5 section 26 ? debug & jtag 26.6.1.1 dac compare size field (dbcr[d1s]) note the data address compare (dac) debug event can be set to react to any byte in a larger block of memory, in addition to reacting to an exact address match. the dac compare size field (dbcr[d1s]) allows dac debug events to react to any byte in a word, lword, or line of four words (qword). the address for a dac is the effective address (ea) of a storage reference instruction. as an example, suppose that a dac debug event should react to byte 3 of an lword-aligned target. a dac set for exact compare would not recognize a reference to that byte by load/store lword or load/ store word instructions, because the byte address is not the ea of such instructions. in such a case, the d1s field must be set for a wider capture range (for example, to ignore the two least significant bits (lsbs) if lword operations to the misaligned byte are to be detected). the wider capture range results in excess debug events (events that are within the specified capture range, but reflect byte operations in addition to the desired byte). such excess debug events must be handled by software. 26.6.2 debug status register (dbsr) the dbsr contains status on debug events and the most recent reset; the status is obtained by reading the dbsr. the status bits are normally set by debug events or by any of the three reset types. clearing the dbsr fields is performed by writing an lword to the dbsr, using the mtdbsr extended mnemonic, having a 1 in all bit positions to be cleared and a 0 in the all other bit positions. the data written to the dbsr is not direct data, but a mask. a 1 clears the bit and a 0 has no effect. application code should not use the dbsr. register 26-2 illustrates the dbsr bits. section 26 iop 480 cpu debugging and jtag facilities debug registers iop 480 data book r2.0 26-6 ? 2000 plx technology, inc. all rights reserved. register 26-2. debug status register (dbsr) 0 ic instruction completion debug event 0 event didn ? t occur 1 event occurred 1 bt branch taken debug event 0 event didn ? t occur 1 event occurred 2 ede exception debug event 0 event didn ? t occur 1 event occurred 3 tie trap instruction debug event 0 event didn ? t occur 1 event occurred 4 ude unconditional debug event 0 event didn ? t occur 1 event occurred 5 ia1 iac1 debug event 0 event didn ? t occur 1 event occurred 6 reserved 7 dr1 dac read debug event 0 event didn ? t occur 1 event occurred 8 dw1 dac write debug event 0 event didn ? t occur 1 event occurred 9:10 reserved 11 ide imprecise debug event 0 event didn ? t occur 1 event occurred 12:21 reserved 22:23 mrr most recent reset 00 no reset has occurred since last cleared by software. 01 core reset 10 chip reset 11 system reset this field is set to a value, indicating the type of reset, when a reset occurs. 24:31 reserved 012345 78 2223 ic ede ude dw1 bt tie ia1 dr1 mrr 11 21 24 12 ide 6910 31 section 26 debug registers iop 480 cpu debugging and jtag facilities iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 26-7 section 26 ? debug & jtag 26.6.3 data address compare register (dac1) the iop 480 cpu can take a debug event upon storage or cache references to an address specified in the dac register. the address in the dac is the address of an operand (effective address, or ea) of a storage reference or cache instruction.the fields dbcr[d1r] and dbcr[d1w] control the dac read and dac write debug events, respectively. the address in dac specifies an exact byte ea for a dac debug event. however, one may want to take a debug event on any byte within a word ( that is , ignore the least significant bit (lsb) of the dac); on any byte within an lword (that is, ignore the two lsbs of dac), or on any byte within a line of four lwords ( that is , ignore four lsbs of dac). the dbcr[d1s] field controls the addressing options. register 26-4 illustrates the dac1 bits. 26.6.3.1 data address compare (dac) applied to cache instructions some cache instructions may cause dac debug events. there are several special cases. table 26-2 summarizes possible dac debug events by cache instruction. architecturally, the dcbi and dcbz instructions are ? stores. ? these instructions can change data, or cause the loss of data by invalidating a dirty line. therefore, they can cause dac-write debug events. the dccci instruction also could be considered a ? store ? because it can change data by invalidating a dirty line. however, dccci is not address-specific; it affects an entire congruence class regardless of the operand address of the instruction. because it is not address-specific, dccci does not cause dac-write debug events. architecturally, the dcbt , dcbtst , dcbf, and dcbst instructions are ? loads. ? these instructions do not change data. flushing or storing a cache line from the cache is not architecturally a ? store ? because a store had already updated the cache; the dcbf or dcbst instruction only updates the copy in main memory. the dcbt and dcbtst instructions can cause dac-read debug events independent of cacheability. if data translation is enabled and the effective address (ea) of either dcbt or dcbtst encounters a data storage exception due to a tlb miss or a zone fault, the instruction becomes a no-op. under this condition, these instructions still can cause dac-read debug events. although dcbf and dcbst are architecturally ? loads, ? these instructions can create dac-write (but not dac-read) debug events. in a debug environment, the fact that external memory is being written is the event of interest. although dcread and dccci are not address-specific (they affect a congruence class regardless of the instruction operand address), and are considered ? loads, ? on the iop 480 cpu they do not cause dac debug events. register 26-3. data address compare register (dac1) 0:31 data address compare (dac) byte address dbcr[d1s] determines byte, word, or lword usage. table 26-2. dac applied to cache instructions instruction possible dac debug event dac-read dac-write icbi yes no icbt yes no iccci no no icread no no dcba no yes dcbf no yes dcbi no yes dcbst no yes dcbt yes (if cacheable) no dcbtst yes (if cacheable) no dcbz no yes dccci no no dcread no no section 26 iop 480 cpu debugging and jtag facilities debug interface iop 480 data book r2.0 26-8 ? 2000 plx technology, inc. all rights reserved. all icu operations ( icbi , icbt , iccci , and icread ) are architecturally treated as ? loads. ? icbi and icbt cause dac debug events. iccci and icread do not cause dac debug events on the iop 480 cpu. 26.6.3.2 dac applied to string instructions an stswx instruction with a string length of 0 is a no- op. the lswx instruction with the string length equal to 0 does not alter the rt contents with undefined data, as allowed by the powerpc architecture. neither stswx nor lswx with zero length causes a dac debug event because storage is not accessed by these instructions. 26.6.4 instruction address compare register (iac1) the iop 480 cpu can take a debug event upon an attempt to execute an instruction from an address. the address, which must be lword-aligned, is defined in the iac register. the dbcr[ia1] field of the dbcr controls the instruction address compare (iac) debug event. register 26-4 illustrates the iac1 bits. 26.7 debug interface the iop 480 cpu processor provides a jtag interface to support hardware and software test and debug. typically, the interface connects to a debug port external to the iop 480 cpu; the debug port is typically connected to a jtag connector on a processor board. 26.7.1 ieee 1149.1 test access port (jtag debug port) the ieee 1149.1 test access port (tap), commonly called the jtag (joint test action group) debug port, is an architectural standard described in ieee standard 1149.1 ? 1990, ieee standard test access port and boundary scan architecture . the standard describes a method for accessing internal chip facilities using a four- or five-signal interface. the jtag debug port, originally designed to support scan-based board testing, is enhanced to support the attachment of debug tools. the enhancements, which comply with the ieee 1149.1 specifications for vendor- specific extensions, are compatible with standard jtag hardware for boundary-scan system testing. 26.7.1.1 jtag connector a 16-pin male 2x8 header connector is suggested as the jtag debug port connector for chips that incorporate the iop 480 cpu. this connector definition matches the requirements of the riscwatch debugger from ibm. the connector is shown in figure 26-1 on page 26-9 and the signals are shown in table 26-3 on page 26-9. the connector should be placed as close as possible to the chip containing the iop 480 cpu to ensure signal integrity. position 14 does not contain a pin. jtag signals jtag debug port implements the four required jtag signals, tclk, tms, tdi, and tdo, and the optional trst signal. jtag clock requirements the frequency of the tclk signal can range from dc to one-half of the internal chip clock frequency. jtag reset requirements jtag debug port logic is reset at the same time as a system reset. upon receiving trst , the jtag tap controller returns to the test-logic reset state. register 26-4. instruction address compare register (iac1) 0:29 instruction address compare lword address omit two low-order bits of complete address. 30:31 reserved 0 29 30 31 section 26 debug interface iop 480 cpu debugging and jtag facilities iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 26-9 section 26 ? debug & jtag 1. a 10k ohm pull-up resistor can be connected to this signal to reduce chip power consumption. the pull-up resistor is not required. 2. the +power signal, sourced from the target development board, indicates whether the processor is operating. this signal does not supply power to the riscwatch hardware or to the processor. the active level on this signal can be +5v or +3.3v (the iop 480 cpu may have +5v or +3.3v i/o, but the processor must be powered by +3.3 v). a series resistor (1k ohm or less) should be used to provide short circuit current-limiting protection. 3. a 10k ohm pull-up resistor must be connected to these signals to ensure proper chip operation when these inputs are not used. 26.7.1.2 jtag instructions the jtag debug port provides the standard extest, sample/preload, and bypass instructions. invalid instructions behave as the bypass instruction. there are three private instructions. 1 0.1" 0.1" 2 key 15 16 figure 26-1. jtag connector physical layout (top view) table 26-3. jtag connector signals pin i/o signal description 1o tdo jtag test data out 2 no connect (nc) reserved 3i tdi 1 jtag test data in 4 trst jtag reset 5 nc reserved 6 +power 2 processor power ok 7i tck 3 jtag test clock 8 nc reserved 9i tms 1 jtag test mode select 10 nc reserved 11 i halt 3 processor halt 12 nc reserved 13 nc reserved 14 key the pin at this position should be removed 15 nc reserved 16 gnd ground table 26-4. jtag instructions instruction code comments extest 0000 ieee 1149.1 standard sample/preload 0001 ieee 1149.1 standard jtag 5 0101 private jtag 7 0111 private jtag b 1011 private bypass 1111 ieee 1149.1 standard section 26 iop 480 cpu debugging and jtag facilities debug interface iop 480 data book r2.0 26-10 ? 2000 plx technology, inc. all rights reserved. 26.7.1.3 jtag boundary scan boundary scan description language (bsdl), ieee 1149.1b-1994, is a supplement to ieee 1149.1-1990 and ieee 1149.1a-1993 standard test access port and boundary-scan architecture . bsdl, a subset of the ieee 1076-1993 standard vhsic hardware description language (vhdl), allows a rigorous description of testability features in components which comply with the standard. it is used by automated test pattern generation tools for package interconnect tests and by electronic design automation (eda) tools for synthesized test logic and verification. bsdl supports robust extensions that can be used for internal test generation and to write software for hardware debug and diagnostics. the primary components of bsdl include the logical port description, the physical pin map, the instruction set, and the boundary register description. the logical port description assigns symbolic names to the pins of a chip. each pin has a logical type of in, out, inout, buffer, or linkage that defines the logical direction of signal flow. the physical pin map correlates the logical ports of the chip to the physical pins of a specific package. a bsdl description can have several physical pin maps; each map is given a unique name. instruction set statements describe the bit patterns that must be shifted into the instruction register to place the chip in the various test modes defined by the standard. instruction set statements also support descriptions of instructions that are unique to the chip. the boundary register description lists each cell or shift stage of the boundary register. each cell has a unique number; the cell numbered 0 is the closest to the test data out (tdo) pin and the cell with the highest number is closest to the test data in (tdi) pin. each cell contains additional information, including: cell type, logical port associated with the cell, logical function of the cell, safe value, control cell number, disable value, and result value. iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 27-1 section 27 ? cpu mem mgmt 27 iop 480 cpu memory management the iop 480 cpu has a 4 gb address space, which is presented as a flat address space. the iop 480 cpu memory management unit (mmu) performs address translation and protection functions. with appropriate system software, the mmu supports: translation of the 4-gb logical address space into physical addresses independent enabling of instruction and data translation and protection page-level access control using the translation mechanism software control of page replacement strategy additional virtual-mode control of protection using zones real-mode write protection 27.1 overview the instruction and integer units generate effective addresses (eas) for instruction fetches and data accesses, respectively. (an ea is a 32-bit address formed by adding an index or displacement to a base address.) instruction eas are for sequential instruction fetches, and for fetches causing changes in program flow (branches and interrupts). data eas are for load/store and cache control instructions. the mmu translates eas into real addresses; the instruction cache unit (icu) and data cache unit (dcu) use real addresses to access memory. the iop 480 cpu mmu supports demand-paged virtual memory and other management schemes that depend on precise control of logical to physical address mapping and flexible memory protection. translation misses and protection faults cause precise exceptions. sufficient information is available to correct the fault and restart the faulting instruction. the mmu divides logical storage into pages. the page represents the granularity of logical address translation and protection control. eight page sizes (1 kb, 4 kb, 16 kb, 64 kb, 256 kb, 1 mb, 4 mb, and 16 mb) are simultaneously supported. for logical-to-physical address translation to be performed, a valid entry for the page containing the logical address must be in the translation lookaside buffer (tlb). addresses for which no tlb entry exists cause tlb-miss exceptions. 27.2 address translation bits in the machine state register (msr) control translation. the msr[ir] (instruction relocate) bit controls translation for instruction accesses. the msr[dr] (data relocate) bit controls the translation mechanism for data accesses. these bits, specified independently, can be changed at any time by a program in supervisor state. note that all exceptions clear msr[ir, dr] and place the processor in the supervisor state. subsequent discussion about translation and protection assumes that msr[ir, dr] are set appropriately. the processor references memory when it fetches an instruction, and when it executes load/store, branch, and cache control instructions. an ea references a memory location. when translation is enabled, the ea is translated into a real address, as illustrated in figure 27-1. the icu or dcu uses the real address for the access. (when translation is not enabled, the ea is already a real address.) in address translation, the ea is combined with an 8-bit process id (pid) to create a 40-bit virtual address. the virtual address is compared to all of the tlb entries. a matching entry, if found in the tlb, supplies the real address for the storage reference. figure 27-1 illustrates the process. section 27 iop 480 cpu memory management translation lookaside buffer (tlb) iop 480 data book r2.0 27-2 ? 2000 plx technology, inc. all rights reserved. 27.3 translation lookaside buffer (tlb) the tlb is hardware that controls translation, protection, and storage attributes. the instruction and data units share a unified 64-entry, fully associative tlb (a tlb in which any page entry (tlb entry) can be placed anywhere in the tlb). tlb entries are maintained under software control. system software determines the tlb entry replacement strategy and the format and use of page state information. a tlb entry contains the information required to identify the page, to specify translation and protection controls, and to specify the storage attributes. 27.3.1 unified tlb the unified tlb (utlb) contains 64 entries; each has a tlbhi (tag) portion and a tlblo (data) portion. tlbhi contains 36 bits; tlblo contains 32 bits. when translation is enabled, the utlb tag portion compares some or all of ea 0:21 with some or all of the effective page number epn 0:21 , based on the size bits size 0:2 . the 64 entries are simultaneously checked for a match. if an entry matches, the corresponding data portion of the utlb provides the real page number (rpn), access control bits (zsel, ex, wr), and storage attributes (w, i, m, g, e, k). a programming error occurs if multiple entries match during a tlb look-up. the results of such a look-up are undefined. figure 27-2 on page 27-3 illustrates the utlb. [0: n ? 1] [ n :31] offset effective page address [0:7] pid effective page address offset pid 32-bit ea unified tlb 64-entry fully-associative array offset real page number 32-bit real address [8: n + 7] [0: n ? 1] [ n :31] [ n + 8:39] [24:31] [0:23] 40-bit virtual address note: n is determined by page size. see table 27-1. pid register figure 27-1. effective to real address translation flow section 27 translation lookaside buffer (tlb) iop 480 cpu memory management iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 27-3 section 27 ? cpu mem mgmt the virtual address space is extended by adding an 8-bit translation id (tid) loaded from the process id (pid) register during a tlb access. the pid identifies one of 255 unique software entities (usually a process or thread). tbl_entry[tid] is compared to the pid during tlb look-up. tag and data entries are written by copying data from gprs and the pid, using the tlbwe instruction. tag and data entries are read by copying data to gprs and the pid, using the tlbre instruction. software can search for specific entries using the tlbsx instruction. 27.3.2 unified tlb fields each tlb entry describes a page that is eligible for translation and access controls. fields in the tlb entry fall into four categories: information required to identify the page to the hardware translation mechanism control information specifying the translation access control information storage attribute control information 27.3.3 page identification fields when an ea is presented to the mmu for processing, the mmu applies several selection criteria to each tlb entry to select the appropriate entry. although it is possible to place multiple entries into the tlb to match a specific ea and pid, this is considered a programming error and the results are undefined. the following fields in the tlb entry identify the page. except as noted, all comparisons must succeed to validate an entry for subsequent processing. epn (effective page number, 22 bits) compared to some number of the ea 0:21 bits presented to the mmu. the exact comparison depends on the page size, as specified in table 27-1. 0212224 zsel rpn tlbhi 0 size epn v 27 29 3 0 31 wi mg ex wr tid (tag entry) 21 25 22 35 28 24 23 28 pid 024 id 31 (process id) 23 figure 27-2. tlb entries tlblo (data entry) 26 27 ek table 27-1. tlb fields related to page size page size size field n bits compared epn to ea comparison rpn bits set to 0 1 kb 000 22 epn 0:21 ? ea 0:21 ? 4 kb 001 20 epn 0:19 ? ea 0:19 rpn 20:21 16 kb 010 18 epn 0:17 ? ea 0:17 rpn 18:21 64 kb 011 16 epn 0:15 ? ea 0:15 rpn 16:21 256 kb 100 14 epn 0:13 ? ea 0:13 rpn 14:21 1 mb 101 12 epn 0:11 ? ea 0:11 rpn 12:21 4 mb 110 10 epn 0:9 ? ea 0:9 rpn 10:21 16 mb 111 8 epn 0:7 ? ea 0:7 rpn 8:21 section 27 iop 480 cpu memory management translation lookaside buffer (tlb) iop 480 data book r2.0 27-4 ? 2000 plx technology, inc. all rights reserved. size (page size, 3 bits) selects one of the eight page sizes, 1 kb ? 16 mb, listed in table 27-1 on page 27-3. v (valid, 1 bit) indicates whether a tlb entry is valid and can be used for translation. a valid tlb entry implies read access, unless overridden by zone protection. tlb_entry[v] can be written using a tlbwe instruction. the tlbia instruction invalidates all tlb entries. tid (translation id, 8 bits) loaded from the pid register during a tlbwe operation. the tid value, which extends the ea, is compared with the pid value during a tlb access (see table 27-2 on page 27-9). the tid provides a convenient way to associate a translation with one of 255 unique software entities, typically a process or thread maintained by system software. setting tlb_entry[tid] = 0000 disables tid-pid comparison and identifies a tlb entry as valid for all processes; the value of the pid register is irrelevant. 27.3.3.1 translation field when a tlb entry is identified as matching an ea (and possibly the pid), tlb_entry[rpn] defines how the ea is translated. rpn (real page number, 22 bits) replaces some, or all, of ea 0:21 , depending on page size. for example, a 16 kb page uses ea 0:17 for comparison. the translation mechanism replaces ea 0:17 with tlb_entry[rpn] 0:17 to form the physical address, and ea 18:31 becomes the real page offset, as illustrated in figure 27-1 on page 27-2. note: software must set all unused bits of rpn (as determined by page size) to 0. see table 27-1 on page 27-3. 27.3.3.2 access control fields several access controls are available in the utlb entries. zsel (zone select, 4 bits) selects one of 16 zone fields (z0 ? z15) from the zone protection register (zpr). the zpr field bits can modify the access protection specified by the tlb_entry[v, ex, wr] bits of a tlb entry. zone protection is described in detail in section 27.7.1.4, ? zone protection, ? on page 27-10. ex (execute enable, 1 bit) when set (tlb_entry[ex] = 1), allows instruction execution at addresses within a page. zpr settings can override tlb_entry[ex]; see section 27.7.1.4, ? zone protection, ? on page 27-10, for more information. wr (write-enable 1 bit) when set (tlb_entry[wr] = 1), permits store operations to addresses in a page. zpr settings can override tlb_entry[wr]; see section 27.7.1.4, ? zone protection, ? on page 27-10. 27.3.3.3 storage attribute fields tlb entries contain bits that set and provide information about the storage control attributes. four of the attributes (w, i, m, and g) are defined in the powerpc architecture. the e storage attributes are defined in the ibm powerpc embedded environment. the k attribute is implementation-specific. w (write-through, 1 bit) when set (tlb_entry[w] = 1), stores are specified as write-through. if data in the referenced page is in the data cache, a store updates the cached copy of the data and the external memory location. contrast this with a write-back strategy, which updates memory only when a cache line is flushed. in real mode, the data cache write-thru register (dcwr) controls the setting of the w storage attribute. note that the powerpc architecture does not support memory models in which write-through is enabled and caching is inhibited. it is considered a programming error to use these memory models; the results are boundedly undefined. i (caching inhibited, 1 bit) when set (tlb_entry[i] = 1), a memory access is completed by referencing the location in main memory, bypassing the cache arrays. during the access, the accessed location is not put into the cache arrays. in real mode, the instruction cache cacheability register (iccr) and data cache cacheability register (dccr) control the setting of the i storage registers. in these registers, the polarity of the bit is section 27 translation lookaside buffer (tlb) iop 480 cpu memory management iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 27-5 section 27 ? cpu mem mgmt reversed; 1 indicates that a storage control region is cacheable, rather than caching inhibited). the powerpc architecture does not support memory models in which write-through is enabled and caching is inhibited. it is considered a programming error to use these memory models; the results are boundedly undefined. it is considered a programming error if the target location of a load/store, dcbz , or fetch access to caching inhibited storage is in the cache; the results are boundedly undefined. it is not considered a programming error for the target locations of other cache control instructions to be in the cache when caching is inhibited. m (memory coherent, 1 bit) for some implementations that support multiprocessing, the m storage attribute improves the performance of memory coherency management. the iop 480 cpu does not provide multi-processor support or hardware support for data coherency; the m bit is implemented, but has no effect. g (guarded, 1 bit) when set (tlb_entry[g] = 1), indicates that the hardware cannot speculatively access the location for pre-fetching or out-of-order load access. the g storage attribute is typically used to protect memory- mapped i/o from inadvertent access. attempted execution of an instruction from a guarded address, while instruction translation is enabled, results in an instruction storage exception. an instruction fetch to a guarded region does not occur until the execution pipeline is empty, guaranteeing that the access is necessary and therefore not speculative. for this reason, performance is degraded when executing out of guarded regions, and software should avoid unnecessarily marking regions of instruction storage as guarded. in real mode, the storage guarded register (sgr) controls the setting of the g storage attribute. k (compression, 1 bit) when set (tlb_entry[k] = 1), indicates that data in the associated page is stored in compressed mode. in real mode, the storage compression register (skr) controls the setting of the k storage attribute. e (endian, 1 bit) when set (tlb_entry[e] = 1), indicates that data in the associated page is stored in true little endian format. in real mode, the storage little-endian register (sler) controls the setting of the e storage attribute. 27.3.4 shadow instruction tlb to enhance performance, four instruction-side tlb entries are kept in a four-entry fully-associative shadow array. this array, called the instruction tlb (itlb), helps to avoid tlb contention between instruction accesses to the tlb and load/store operations. replacement and invalidation of the itlb entries is managed by hardware during routine execution (see section 27.3.4.2, ? itlb consistency, ? on page 27-6 for details). the itlb can be considered a level-1 instruction-side tlb; the utlb serves as the level-2 instruction-side tlb and the level-1 data-side tlb. the itlb is used only by instruction fetches for storing instruction address translations. each itlb entry contains the translation information for a page. the processor uses the itlb for address translation of instruction accesses when msr[ir] = 1. 27.3.4.1 itlb accesses the instruction unit accesses the itlb independently of the rest of the mmu. itlb accesses are transparent to the executing program, except that itlb hits contribute to higher overall instruction throughput by allowing data translations to occur in parallel. therefore, when instruction accesses hit in the itlb, the address translation mechanisms in the utlb are available for use by data accesses simultaneously. the itlb requests a new entry from the utlb when an itlb miss occurs. a two-cycle penalty occurs at each itlb miss that is also a utlb hit; the penalty is larger if it is also a utlb miss, or if there is contention for the utlb from the data side. a round-robin replacement algorithm replaces existing entries with new entries. figure 27-3 illustrates the relationship of the itlb and utlb in address translation. section 27 iop 480 cpu memory management translation lookaside buffer (tlb) iop 480 data book r2.0 27-6 ? 2000 plx technology, inc. all rights reserved. 27.3.4.2 itlb consistency the processor invalidates the entire itlb contents when the following context-synchronizing events occur, to help to maintain itlb integrity. isync instruction processor context switch (all interrupts, rfi , rfci ) if software updates a translation/protection mechanism (utlb, pid, zpr, or msr) and must synchronize these updates with the itlb, the software must perform the necessary context synchronization. a typical example is the manipulation of the tlb by an operating system within an interrupt handler for a tlb miss. upon entry to the interrupt handler, the itlb is invalidated and translation is disabled. if the operating system simply made the tlb updates and returned from the handler (using rfi ), no additional explicit software action would be required to synchronize the itlb. if, instead, the operating system re-enables translation within the handler, and then performs tlb updates within the handler, those updates would not be effective in the itlb until rfi is executed to return from the handler. for those tlb updates to be reflected in i-side ea generated extract real address from itlb no translation translation enabled (msr[dr]=1) translation disabled (msr[dr]=0) itlb hit continue i-cache access perform iltb lookup translation enabled (msr[ir]=1) translation disabled (msr[ir]=0) itlb miss i-side or d-side or perform utlb look-up utlb hit utlb miss extract real address from utlb tlb miss = arbitrates itlb misses a no translation a route address to itlb d-side access i-side access with d-side accesses figure 27-3. itlb/utlb address resolution continue i-cache access continue d-cache access d-side ea generated section 27 tlb-related exceptions iop 480 cpu memory management iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 27-7 section 27 ? cpu mem mgmt the itlb within the handler, an isync must be issued after tlb updates finish. failure to properly synchronize the itlb can cause unexpected behavior. note: as a rule, follow software manipulation of translation mechanism (if performed while translation is active) with a context-synchronizing operation (usually isync ). 27.4 tlb-related exceptions the processor relies on exception processing to implement paged virtual memory, and to enforce protection of specified memory pages. when an enabled exception (an interrupt) occurs, the processor clears msr[ir, dr]. therefore, at least at the beginning of all exception handlers, the processor operates in real mode for instruction accesses and data accesses. note that when address translation is disabled (msr[ir] = 0 and msr[dr] = 0) for an instruction fetch or load/store, the ea is treated as the real address and is passed directly to the memory subsystem (including cache units) as a direct address. such direct addresses bypass all memory protection checks performed by the mmu. mmu accesses can result in the following exceptions: data storage exception instruction storage exception data tlb miss exception instruction tlb miss exception program exception 27.4.1 data storage exception a data storage exception occurs when data translation is active, and the desired access to the ea is not permitted for one of the following reasons: 1. in the problem state icbi , load/store, dcbz , or dcbf having an ea having zpr[zn] = 00. (in this case, dcbt and dcbtst no-op, rather than cause an exception. privileged instructions cannot cause data storage exceptions.) stores, or dcbz , to an ea having tlb_entry[wr] = 0 and zpr[zn] 11. (the privileged instructions dcbi and dccci are treated as ? stores ? , but cause program exceptions, rather than data storage exceptions.) 2. in the supervisor state data store, dcbi , dcbz , or dccci to an ea having tlb_entry[wr] = 0 and zpr[zn] other than 11 or 10. section 27.7.1.4, ? zone protection, ? on page 27-10, describes zone protection in detail. see section 11.7.7, ? instruction storage exception, ? on page 11-22, for a detailed discussion of the data storage exception. 27.4.2 instruction storage exception an instruction access exception occurs when instruction translation is active, and the processor attempts to execute an instruction at an ea for which fetch access is not permitted, for any of the following reasons: 1. in the problem state instruction fetch from an ea with zpr[zn] = 00. instruction fetch from an ea having tlb_entry[ex] = 0 and zpr[zn] 11. instruction fetch from an ea having tlb_entry[g] = 1. 2. in the supervisor state instruction fetch from an ea having tlb_entry[ex] = 0 and zpr[zn] other than 11 or 10. instruction fetch from an ea having tlb_entry[g] = 1. see section 27.7.1.4, ? zone protection, ? on page 27-10, for a detailed discussion of zone protection. see section 11.7.7, ? instruction storage exception, ? on page 11-22, for a detailed discussion of the instruction storage exception. 27.4.3 data tlb miss exception a data tlb miss exception is generated if data translation is enabled and a valid tlb entry matching the ea and pid is not present. the exception applies to data access instructions and cache operations (excluding cache touch instructions). see section 11.7.15, ? data tlb miss exception, ? on page 11-27, for a detailed discussion. section 27 iop 480 cpu memory management tlb management iop 480 data book r2.0 27-8 ? 2000 plx technology, inc. all rights reserved. 27.4.4 instruction tlb miss exception the instruction tlb miss exception is generated if instruction translation is enabled and execution is attempted for an instruction for which a valid tlb entry matching the ea and pid for the instruction fetch is not present. see section 11.7.16, ? instruction tlb miss exception, ? on page 11-27, for a detailed discussion. 27.4.5 program exception when the tie_cpummuen signal is tied to 0, the tlb instructions ( tlbia , tlbre , tlbsx , tlbsync , and tlbwe ) are treated as illegal instructions. when execution of any of these instructions occurs under this circumstance, a program exception results. when tie_cpummuen is tied to 0, msr[ir, dr] = 0. note: when tie_cpummuen is tied to 0, msr[ir, dr] = 0 upon execution of an rfi or rfci instruction, even if an exception handler sets msr[ir] = 1 or msr[dr] = 1 in save/restore register 0 (srr0) or srr3. see section 11.7.16, ? instruction tlb miss exception, ? on page 11-27, for a detailed discussion. 27.5 tlb management the processor does not imply any format for the page tables or the page table entries. software has significant flexibility in implementing a custom replacement strategy. for example, software can ? lock ? tlb entries that correspond to frequently used storage, so that those entries are never cast out of the tlb, and tlb miss exceptions to those pages never occur. tlb management is performed in software with some hardware assist, consisting of: storage of the missed ea in the save/restore register 0 (srr0) register for an instruction-side miss, or in the data exception address register (dear) for a data-side miss. instructions for reading, writing, searching, and invalidating the tlb, as described briefly in the following subsections. see section 28, ? iop 480 cpu instruction set, ? for detailed instruction descriptions. 27.5.1 tlb search instructions (tlbsx/tlbsx.) tlbsx instruction locates entries in the tlb, to find the tlb entry associated with an exception, or to locate candidate entries to cast out. tlbsx searches the utlb array for a matching entry. the ea is the value to be matched; ea = (ra|0)+(rb). if the tlb entry is found, its index is placed in rt 26:31 . rt can then serve as the source register for a tlbre or tlbwe instruction to read or write the entry, respectively. if no match is found, the contents of rt are undefined. tlbsx. sets the condition register (cr) bit cr0 eq . the value of cr0 eq depends on whether an entry is found: cr0 eq = 1 if an entry is found; cr0 eq = 0 if no entry is found. 27.5.2 tlb read/write instructions (tlbre/tlbwe) tlb entries can be accessed for reading and writing by tlbre and tlbwe , respectively. separate extended mnemonics are available for the tlbhi (tag) and tlblo (data) portions of a tlb entry. 27.5.3 tlb invalidate instruction (tlbia) tlbia sets tlb_entry[v] = 0 to invalidate all tlb entries. all other tlb entry fields remain unchanged. using tlbwe to set tlb_entry[v] = 0 invalidates a specific tlb entry. 27.5.4 tlb sync instruction (tlbsync) tlbsync guarantees that all tlb operations have completed for all processors in a multi-processor system. the iop 480 cpu provides no multiprocessor support, so this instruction performs no function. the instruction is included to facilitate code portability. 27.6 recording page references and changes when system software manages virtual memory, the software views physical memory as a collection of pages. each page is associated with at least one tlb entry. to manage memory effectively, system software often must know whether a particular page has been referenced or modified. note that this involves more than knowing whether a particular section 27 access protection iop 480 cpu memory management iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 27-9 section 27 ? cpu mem mgmt tlb entry was used to reference or alter memory, because multiple tlb entries can translate to the same page. when system software manages a demand-paged environment, and the software needs to replace the contents of a page with other data, previously referenced pages (accessed for any purpose) are more likely to be maintained than pages that were never referenced. if the contents of a page must be replaced, and data contained in that page was modified, system software generally must write the contents of the modified page to the backing store before replacing its contents. system software must maintain records to control the environment. similarly, when system software manages tlb entries, the software often must know whether a particular tlb entry was referenced. when the system software must select a tlb entry to cast, previously referenced entries are more likely to be maintained than entries which were never referenced. system software must also maintain records for this purpose. the iop 480 cpu does not provide hardware reference or change bits, but tlb miss exceptions and data storage exceptions enable system software to maintain reference information for tlb entries and their associated pages, respectively. first, the tlb entries are built, with each tlb_entry[v, wr] = 0. system software retains the index and epn of each entry. the first attempt by application code to access a page causes a tlb miss exception, because its tlb entry is marked invalid. the tlb miss handler records the reference to the tlb entry (and to the associated page) in a table, then sets tlb_entry[v] = 1. (note that tlb_entry[v] can be considered a reference bit for the tlb entry.) subsequent read accesses to the page associated with the tlb entry proceed normally. in the example just given for recording tlb entry references, the first write access to the page using the tlb entry, after the entry is made valid, causes a data storage exception (write access was turned off.). the tlb miss handler records the write to the page in a table, then sets tlb_entry[wr] = 1. (note that tlb_entry[wr] can be considered a change bit for the page.) subsequent write accesses to the page proceed normally. 27.7 access protection the iop 480 cpu provides virtual-mode access protection. the tlb entry enables system software to control general access for programs in the problem state, and control write and execute permissions for all pages. the tlb entry can specify zone protection that can override the other access control mechanisms supported in the tlb entries. tlb entry and zone protection methods also support access controls for cache operation and string loads/ stores. 27.7.1 access protection mechanisms in the tlb for mmu access protection to be in effect, one or both of msr[ir] or msr[dr] must be active. msr[ir] enables protection on instruction fetches, which are inherently read-only. msr[dr] enables protection on data accesses (loads/stores). 27.7.1.1 general access protection the translation id (tlb_entry[tid]) provides the first level of mmu access protection. this 8-bit field, if non- zero, is compared to the contents of tlb_entry[pid] (see table 27-2 on page 27-9). these fields must match (after successful comparison of ea) in a valid tlb entry if any access is to be allowed. in typical use, it is assumed that a program in the supervisor state (such as a real-time operating system) sets the pid before enabling a program in the problem state program that is subject to access control. if tlb_entry[tid] = 0000, the associated memory page is accessible to all programs, regardless of their pid. this enables multiple processes to share common code and data. the common area is still subject to all other access protection mechanisms. table 27-2. process id (pid) 0:23 reserved 24:31 process id section 27 iop 480 cpu memory management access protection iop 480 data book r2.0 27-10 ? 2000 plx technology, inc. all rights reserved. 27.7.1.2 execute permissions if msr[ir] = 1, instruction fetches are subject to mmu translation and are afforded mmu access protection. fetches are inherently read-only, so write protection is not needed. instead, using tlb_entry[ex], a memory page is marked as executable (contains instructions) or not executable (contains data or memory-mapped control hardware). if an instruction is pre-fetched from a memory page for which tlb_entry[ex] = 0, the instruction is tagged as an error. if the processor subsequently attempts to execute this instruction, an instruction storage exception results. this exception is precise with respect to the attempted execution. if the fetcher discards the instruction without attempting to execute it, no exception results. zone protection can alter execution protection. 27.7.1.3 write permissions if msr[dr] = 1, data loads and stores are subject to mmu translation and are afforded mmu access protection. the existence of a tlb entry describing a memory page implies read access; write access is controlled by tlb_entry[wr]. if a store (including dcbz , dcbi , or dccci ) is made to an ea having tlb_entry[wr] = 0, a data storage exception results. this exception is precise. zone protection can alter write protection (see section 27.7.1.4, ? zone protection, ? on page 27-10). in addition, only zone protection can prevent read access of a page defined by a tlb entry. 27.7.1.4 zone protection each tlb entry contains a 4-bit zone select (zsel) field. a zone is an arbitrary identifier for grouping tlb entries (memory pages) for purposes of protection. as many as16 different zones may be defined. any zone can have any number of member pages. each zone is associated with a 2-bit field (z0 ? z15) in the zpr. the values of the field define how protection is applied to all pages that are member of that zone. changing the value of the zpr field can alters the protection attributes of all pages in the zone. without zpr, the change would require finding, reading, altering, and rewriting the tlb entry for each page in a zone, individually. the zpr provides a much faster means of altering the protection for groups of memory pages. the zsel values 0 ? 15 select zpr fields z0 ? z15, respectively. while it is common for tlb_entry[ex, wr] to be identical for all member pages in a group, this is not required. the zpr field alters the protection defined by tlb_entry[ex] and tlb_entry[wr], on a page-by- page basis, as shown in table 27-1 on page 27-11. an application program (presumed to be running in the problem state) can have execute and write permissions as defined by tlb_entry[ex] and tlb_entry[wr] for the individual pages, or no access (denies loads, as well as stores and execution), or complete access. setting zpr[z n ] = 00 for a zpr field is the only way to deny read access to a page defined by an otherwise valid tlb entry. tlb_entry[ex] and tlb_entry[wr] do not support read protection. note that the icbi instruction is considered a load with respect to access protection; executed in user-mode, it causes a data storage exception if msr[dr] = 1 and zpr[z n ] = 00 is associated with the ea. for a given zpr field value, a program in supervisor state always has equal or greater access than a program in the problem state. system software can never be denied read (load) access for a valid tlb entry. register 27-1 illustrates the zpr bits. section 27 access protection iop 480 cpu memory management iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 27-11 section 27 ? cpu mem mgmt 27.7.2 access protection for cache instructions architecturally the instructions dcba , dcbi , and dcbz are treated as ? stores ? since they can change data (or cause loss of data by invalidating a dirty line). if data translation is enabled, and tlb_entry[wr] = 0, dcbi and dcbz can cause data storage exceptions. dcbz can cause a data storage exception when executed in user mode and zpr[z n ] = 00; dcbi cannot, because it is a privileged instruction. the dcba instruction enables ? speculative ? line establishment in the cache arrays; the established lines do not cause a line fill. because the effects of dcba are speculative, exceptions that would otherwise result when zpr[z n ] = 00 or tlb_entry[wr] = 0 do not occur. in such cases, dcba is treated as a no-op. the dccci instruction can also be considered a ? store ? since it can change data by invalidating a dirty line; however, dccci is not address-specific (it affects an entire congruence class regardless of the operand address of the instruction). to restrict possible damage from an instruction which can change data and yet avoids the protection mechanism, the dccci instruction is privileged. if data translation is enabled, dccci can cause data storage exceptions when tlb_entry[wr] = 0; the operand is treated as if it were address-specific. dccci cannot cause a data storage exception when zpr[z n ] = 00, because it is a privileged instruction. because dccci can cause data storage and tlb-miss exceptions, use of dccci is not recommended when msr[dr] = 1; if it is used, take care that the specific operand address does not cause an exception. architecturally, dcbt and dcbtst are treated as ? loads ? because they do not change data; they cannot cause data storage exceptions when tlb_entry[wr] = 0. the cache block touch instructions are considered ? speculative ? loads; therefore, if a data storage exception would otherwise result from the execution of dcbt or dcbtst when zpr[z n ] = 00, the instruction register 27-1. zone protection register (zpr) : 0:1 z0 tlb page access control for all pages in this zone; the tlb bits ex and wr are bits that translate an effective address and pid. in problem state (msr[pr] = 1): 00 no access 01 access controlled by ex and wr 10 access controlled by ex and wr 11 accessed as if ex and wr are set in supervisor state (msr[pr] = 0): 00 access controlled by ex and wr 01 access controlled by ex and wr 10 access as if ex and wr are set 11 accessed as if ex and wr are set 2:3 z1 see the description of z0. 4:5 z2 see the description of z0. 6:7 z3 see the description of z0. 8:9 z4 see the description of z0. 10:11 z5 see the description of z0. 12:13 z6 see the description of z0. 14:15 z7 see the description of z0. 16:17 z8 see the description of z0. 18:19 z9 see the description of z0. 20:21 z10 see the description of z0. 22:23 z11 see the description of z0. 24:25 z12 see the description of z0. 26:27 z13 see the description of z0. 28:29 z14 see the description of z0. 30:31 z15 see the description of z0. z10 03478111213161720 31 z0 z12 z1 z11 z13 21 12 56 910 1415 1819 z2 z3 z5 z7 z9 z4 z6 z8 z14 z15 22 23 26 28 29 30 25 27 24 section 27 iop 480 cpu memory management access protection iop 480 data book r2.0 27-12 ? 2000 plx technology, inc. all rights reserved. is treated as a no-op and the exception does not occur. similarly, tlb miss exceptions do not occur for these instructions. architecturally, dcbf and dcbst are treated as ? loads ? . flushing or storing a line from the cache is not architecturally considered a ? store ? because a store was performed to update the cache, and dcbf or dcbst only update main memory. therefore, neither dcbf nor dcbst can cause data storage exceptions when tlb_entry[wr] = 0. because neither instruction is privileged, they can cause data storage exceptions when zpr[z n ] = 00 and data translation is enabled. dcread is a ? load ? from a non-specific address, and is privileged. therefore, it cannot cause data storage exceptions when zpr[z n ] = 00 or tlb_entry[wr] = 0. icbi and icbt are considered ? loads ? and cannot cause data storage exceptions when tlb_entry[wr] = 0. icbi can cause data storage exceptions when zpr[zn] = 00. because icbt is privileged, it cannot cause data storage exceptions when zpr[z n ] = 00. the iccci instruction cannot change data; an instruction cache line cannot be dirty. the iccci instruction is privileged and considered a load. it does not cause data storage exceptions when zpr[z n ] = 00 or tlb_entry[wr] = 0. because iccci can cause a tlb miss exception, use of iccci is not recommended when msr[dr] = 1; if it is used, take care that a specific operand address does not cause an exception. icread is considered a ? load ? from a non-specific address, and is privileged. therefore, it cannot cause data storage exceptions when zpr[z n ] = 00 or tlb_entry[wr] = 0. table 27-3 summarizes the conditions under which the cache control instructions can cause data storage exceptions. 27.7.3 access protection for string instructions the stswx instruction with string length equal to zero (xer[tbc] = 0) is a no-op. when data translation is enabled and xer[tbc] = 0, neither lswx nor stswx can cause tlb miss exceptions, or data storage exceptions when zpr[z n ] = 0 or tlb_entry[wr] = 0. table 27-3. protection applied to cache control instructions instruction possible data storage exception when zpr[zn] = 00 when tlb_entry[wr] = 0 dcba no (instruction no-ops) no (instruction no-ops) dcbf yes no dcbi no yes dcbst yes no dcbt no (instruction no-ops) no dcbtst no (instruction no-ops) no dcbz yes yes dccci no yes dcread no no icbi yes no icbt no no iccci no no icread no no section 27 real-mode storage attribute control iop 480 cpu memory management iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 27-13 section 27 ? cpu mem mgmt 27.8 real-mode storage attribute control the powerpc architecture and the powerpc embedded environment define several sprs to control the following storage attributes in real mode: w, i, m, g, k, and e. note that the k and e attributes are not defined in the powerpc architecture. the e attribute is defined in the ibm powerpc embedded environment. the k attribute is implementation specific. six sprs, called storage attribute control registers, control the various storage attributes when address translation is disabled. when address translation is enabled, these registers are ignored, and the storage attributes supplied by the tlb entry are used (see section 27.3.2, ? unified tlb fields, ? on page 27-3). these registers divide the 4 gb real address space into thirty-two 128 mb regions. in a storage attribute control register, bit 0 controls the lowest 128 mb region, bit 1 the next 128 mb region, and so on. for detailed information on the function of the storage attributes, see section 27.3.3.3, ? storage attribute fields, ? on page 27-4. the registers control storage attributes in real mode: the data cache write-thru register (dcwr) controls the w storage attribute. the dcwr controls write-through policy (the w storage attribute) in real mode (data translation disabled), for the data cache unit (dcu). write-through is not applicable to the instruction cache unit (icu). the powerpc architecture does not support memory models in which write-through is enabled and caching is inhibited. the data cache cacheability register (dccr) controls the i storage attribute for data accesses and cache management instructions. note that the polarity of the bits in this register is opposite to that of the i attribute (dccr[s n ] = 1 enables caching, while tlb_entry[i] = 1 inhibits caching). following any reset, all dccr bits are set to 0. no memory regions are cacheable. before memory regions can be designated as cacheable in the dccr, it is necessary to execute the dccci instruction once for each congruence class in the dcu cache array. this procedure invalidates all congruence classes. the dccr can then be reconfigured, and the dcu can begin normal operation. the powerpc architecture does not support memory models in which write-through is enabled and caching is inhibited. the instruction cache cacheability register (iccr) controls the i storage attribute for instruction fetches. note that the polarity of the bits in this register is opposite to that of the i attribute (iccr[s n ] = 1 enables caching, while tlb_entry[i] 1 inhibits caching). following any reset, all iccr bits are set to 0. no memory regions are cacheable. before memory regions can be designated as cacheable in the iccr, it is necessary to execute the dccci instruction once for each congruence class in the dcu cache array. this procedure invalidates all congruence classes. the iccr can then be reconfigured, and the icu can begin normal operation. the powerpc architecture does not support memory models in which write-through is enabled and caching is inhibited. the storage guarded register (sgr) controls the g storage attribute for instruction and data accesses. this attribute does not affect data accesses; the iop 480 cpu does not perform speculative loads or stores. after any reset, the sgr is set to 0xffff ffff, marking all of storage as guarded. for best performance, system software should clear the guarded attribute of appropriate regions as soon as possible. in instruction translate mode (msr[ir] = 1), the g attribute comes from the tlb entry, and attempting to execute from a guarded region in translate mode causes an instruction storage exception. see section 11.7.7, ? instruction storage exception, ? on page 11-22, for more information. the storage compression register (skr) controls the k storage attribute for instruction and data accesses. this attribute determines whether storage is compressed. after any reset, all skr bits are set to 0 (uncompressed). section 27 iop 480 cpu memory management real-mode storage attribute control iop 480 data book r2.0 27-14 ? 2000 plx technology, inc. all rights reserved. the storage little-endian register (sler) controls the e storage attribute for instruction and data accesses. this attribute determines the byte ordering of storage. section 24.4, ? byte ordering, ? on page 24-13, provides a detailed description of byte ordering in the ibm powerpc embedded environment. after any reset, all sler bits are set to 0 (big endian). table 27-4 shows a generic storage attribute control register. the actual storage attribute control registers have the same bit numbers and address ranges. ea 0:4 specify a storage control region. a bit from each storage attribute control register. for the dcwr, sgr, skr, and sler registers, the selected bits are directly used as the w, g, k, and e storage attributes, respectively. table 27-4. storage attribute control registers bit address range bit address range 0 0x0000 0000 ? 0x07ff ffff 16 0x8000 0000 ? 0x87ff ffff 1 0x0800 0000 ? 0x0fff ffff 17 0x8800 0000 ? 0x8fff ffff 2 0x1000 0000 ? 0x17ff ffff 18 0x9000 0000 ? 0x97ff ffff 3 0x1800 0000 ? 0x1fff ffff 19 0x9800 0000 ? 0x9fff ffff 4 0x2000 0000 ? 0x27ff ffff 20 0xa000 0000 ? 0xa7ff ffff 5 0x2800 0000 ? 0x2fff ffff 21 0xa800 0000 ? 0xafff ffff 6 0x3000 0000 ? 0x37ff ffff 22 0xb000 0000 ? 0xb7ff ffff 7 0x3800 0000 ? 0x3fff ffff 23 0xb800 0000 ? 0xbfff ffff 8 0x4000 0000 ? 0x47ff ffff 24 0xc000 0000 ? 0xc7ff ffff 9 0x4800 0000 ? 0x4fff ffff 25 0xc800 0000 ? 0xcfff ffff 10 0x5000 0000 ? 0x57ff ffff 26 0xd000 0000 ? 0xd7ff ffff 11 0x5800 0000 ? 0x5fff ffff 27 0xd800 0000 ? 0xdfff ffff 12 0x6000 0000 ? 0x67ff ffff 28 0xe000 0000 ? 0xe7ff ffff 13 0x6800 0000 ? 0x6fff ffff 29 0xe800 0000 ? 0xefff ffff 14 0x7000 0000 ? 0x77ff ffff 30 0xf000 0000 ? 0xf7ff ffff 15 0x7800 0000 ? 0x7fff ffff 31 0xf800 0000 ? 0xffff ffff 03478111213161720 31 21 12 56 910 1415 1819 2223 26 282930 25 27 24 iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-1 section 28 ? cpu instr set 28 iop 480 cpu instruction set descriptions of the iop 480 instructions follow. each description contains the following elements: instruction names (mnemonic and full) instruction syntax instruction format diagram pseudocode description prose description registers altered architecture notes identifying the associated powerpc architecture component where appropriate, instruction descriptions list invalid instruction forms and provide programming notes. for a quick reference, table 28-1 alphabetically lists instructions with concurrent page numbers. table 28-1. alphabetical instruction listing with page number cross-reference instruction page number add 28-7 addc 28-8 adde 28-9 addi 28-10 addic 28-11 addic. 28-12 addis 28-13 addme 28-14 addze 28-15 and 28-16 andc 28-17 andi. 28-18 andis. 28-19 b 28-20 bc 28-21 bcctr 28-26 bclr 28-29 cmp 28-33 cmpi 28-34 cmpl 28-35 cmpli 28-36 cntlzw 28-37 crand 28-38 crandc 28-39 creqv 28-40 crnand 28-41 crnor 28-42 cror 28-43 crorc 28-44 crxor 28-45 dcba 28-46 dcbf 28-48 dcbi 28-49 dcbst 28-50 dcbt 28-51 dcbtst 28-52 dcbz 28-53 dccci 28-55 dcread 28-56 table 28-1. alphabetical instruction listing with page number cross-reference (continued) instruction page number section 28 iop 480 cpu instruction set iop 480 cpu instruction set iop 480 data book r2.0 28-2 ? 2000 plx technology, inc. all rights reserved. divw 28-58 divwu 28-59 eieio 28-60 eqv 28-61 extsb 28-62 extsh 28-63 icbi 28-64 icbt 28-65 iccci 28-67 icread 28-69 isync 28-71 lbz 28-72 lbzu 28-73 lbzux 28-74 lbzx 28-75 lha 28-76 lhau 28-77 lhaux 28-78 lhax 28-79 lhbrx 28-80 lhz 28-81 lhzu 28-82 lhzux 28-83 lhzx 28-84 lmw 28-85 lswi 28-86 lswx 28-88 table 28-1. alphabetical instruction listing with page number cross-reference (continued) instruction page number lwarx 28-90 lwbrx 28-91 lwz 28-92 lwzu 28-93 lwzux 28-94 lwzx 28-95 mcrf 28-96 mcrxr 28-97 mfcr 28-98 mfdcr 28-99 mfmsr 28-100 mfspr 28-101 mtcrf 28-103 mtdcr 28-104 mtmsr 28-105 mtspr 28-106 mulhw 28-108 mulhwu 28-109 mulli 28-110 mullw 28-111 nand 28-112 neg 28-113 nor 28-114 or 28-115 orc 28-116 ori 28-117 oris 28-118 table 28-1. alphabetical instruction listing with page number cross-reference (continued) instruction page number section 28 iop 480 cpu instruction set iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-3 section 28 ? cpu instr set rfci 28-119 rfi 28-120 rlwimi 28-121 rlwinm 28-122 rlwnm 28-124 sc 28-125 slw 28-126 sraw 28-127 srawi 28-128 srw 28-129 stb 28-130 stbu 28-131 stbux 28-132 stbx 28-133 sth 28-134 sthbrx 28-135 sthu 28-136 sthux 28-137 sthx 28-138 stmw 28-139 stswi 28-140 stswx 28-141 stw 28-143 stwbrx 28-144 stwcx. 28-145 stwu 28-146 stwux 28-147 table 28-1. alphabetical instruction listing with page number cross-reference (continued) instruction page number stwx 28-148 subf 28-149 subfc 28-150 subfe 28-151 subfic 28-152 subfme 28-153 subfze 28-154 sync 28-155 tlbia 28-156 tlbre 28-157 tlbsx 28-159 tlbsync 28-160 tlbwe 28-161 tw 28-163 twi 28-166 wrtee 28-169 wrteei 28-170 xor 28-171 xori 28-172 xoris 28-173 table 28-1. alphabetical instruction listing with page number cross-reference (continued) instruction page number section 28 iop 480 cpu instruction set instruction set portability iop 480 data book r2.0 28-4 ? 2000 plx technology, inc. all rights reserved. 28.1 instruction set portability to support embedded real-time applications, the instruction sets of the iop 480 cpu and other ibm powerpc 400series embedded controllers implement the ibm powerpc embedded environment. this additional instruction set is not part of the powerpc architecture defined in the powerpc architecture: a specification for a new family of risc process ors. programs using these instructions are not portable to powerpc implementations that do not implement the ibm powerpc embedded environment. table 28-2 lists instructions in the ibm powerpc embedded environment that are implemented in the iop 480 cpu. 28.2 instruction formats for more detailed information about instruction formats, including a summary of instruction field usage and instruction format diagrams for the iop 480 cpu, see appendix a.3, ? instruction formats, ? on page a-36. instructions are four bytes long. instruction addresses are always lword-aligned. instruction bits 0 through 5 always contain the primary opcode. many instructions have an extended opcode in another field. the remaining instruction bits contain additional fields. all instruction fields belong to one of the following categories: defined these instructions contain values, such as opcodes, that cannot be altered. the instruction format diagrams specify the values of defined fields. variable these fields contain operands, such as general purpose register selectors and immediate values, that may vary from execution to execution. the instruction format diagrams specify the operands in variable fields. reserved bits in a reserved field should be set to 0. in the instruction format diagrams, reserved fields are shaded. if any bit in a defined field does not contain the expected value, the instruction is illegal and an illegal instruction exception occurs. if any bit in a reserved field does not contain 0, the instruction form is invalid and its result is architecturally undefined. unless otherwise noted, the iop 480 cpu execute all invalid instruction forms without causing an illegal instruction exception. 28.3 pseudocode the pseudocode that appears in the instruction descriptions provides a semi-formal language for describing instruction operations. the pseudocode uses the following notation: table 28-2. instructions in the ibm powerpc embedded environment dccci dcread iccci icbt icread mfdcr mtdcr rfci tlbre tlbsx tlbsx. tlbwe wrtee wrteei assignment. and logical operator. ? not logical operator. or logical operator. exclusive-or (xor) logical operator. + twos complement addition. ? twos complement subtraction, unary minus. multiplication. division yielding a quotient. section 28 pseudocode iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-5 section 28 ? cpu instr set % remainder of an integer division; (33% 32) = 1. || concatenation. =, equal, not equal relations. <, > signed comparison relations. , unsigned comparison relations. if...then...else... conditional execution; if condition then a else b , where a and b represent one or more pseudocode statements. indenting indicates the ranges of a and b . if b is null, the else does not appear. do do loop. ? to ? and ? by ? clauses specify incrementing an iteration variable; ? while ? and ? until ? clauses specify terminating conditions. indenting indicates the range of the loop. leave leave innermost do loop or do loop specified in a leave statement. n decimal number. 0xn hexadecimal number. 0bn binary number. fld instruction field. fld b bit in a named instruction field. fld b:b range of bits in a named instruction field. fld b,b, . . . list of bits, by number or name, in a named instruction field. reg b bit in a named register. < u > u reg b:b range of bits in a named register. reg b,b, . . . list of bits, by number or name, in a named register. reg[fld] field in a named register. reg[fld, fld . . . ] list of fields in a named register. reg[fld:fld] range of fields in a named register. gpr(r) general purpose register (gpr) r, where 0 r 31. (gpr(r)) contents of gpr r, where 0 r 31. dcr(dcrn) device control register (dcr) specified by the dcrf field in an mfdcr or mtdcr instruction. spr(sprn) spr specified by the sprf field in an mfspr or mtspr instruction. ra, rb, . . . gprs. (rx) contents of a gpr, where x is a, b, s, or t. (ra|0) contents of the register ra or 0, if the ra field is 0. c 0:3 four-bit object used to store condition results in compare instructions. n b bit or bit value b is replicated n times. xx bit positions which are don ? t cares. ceil(x) least integer x. section 28 iop 480 cpu instruction set register usage iop 480 data book r2.0 28-6 ? 2000 plx technology, inc. all rights reserved. the following table lists the pseudocode operators and their associativity in descending order of precedence: 28.4 register usage each instruction description lists the registers altered by the instruction. some register changes are explicitly detailed in the instruction description (for example, the target register of a load instruction). other registers are changed, with the details of the change not included in the instruction description. this category frequently includes the condition register (cr) and the fixed-point exception register (xer). for discussion of cr, see section 24.2.3, ? condition register (cr), ? on page 24-7. for discussion of xer, see section 24.2.2.3, ? fixed point exception register (xer), ? on page 24-5. 28.5 alphabetical instruction listing the following pages list the instructions available in the iop 480 cpu in alphabetical order. exts(x) the result of extending x on the left with sign bits. pc program counter. reserve reserve bit; indicates whether a process has reserved a block of storage. cia current instruction address; the 32-bit address of the instruction being described by a sequence of pseudocode. this address is used to set the next instruction address (nia). does not correspond to any architected register . nia next instruction address; the 32-bit address of the next instruction to be executed. in pseudo-code, a successful branch is indicated by assigning a value to nia. for instructions that do not branch, the nia is cia +4 . ms(addr, n) n umber of bytes represented by n at the location in main storage represented by addr. ea effective address; the 32-bit address, derived by applying indexing or indirect addressing rules to the specified operand, that specifies an location in main storage . rotl((rs),n) rotate left; the contents of rs are shifted left the number of bits specified by n . mask(mb,me) mask having 1s in positions mb through me (wrapping if mb > me) and 0 ? s elsewhere. instruction(ea) instruction operating on a data or instruction cache block associated with an ea. table 28-3. operator precedence operators associativity reg b , reg[fld] , function evaluation left to right n b right to left ? , ? (unary minus) right to left , left to right +, ? left to right || left to right =, , <, > , , left to right , left to right left to right none < u > u section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-7 section 28 ? cpu instr set add add (rt) (ra) + (rb) the sum of the contents of register ra and the contents of register rb is placed into register rt. registers altered rt cr[cr0] lt, gt, eq, so if rc contains 1 xer[so, ov] if oe contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. add rt, ra, rb oe=0, rc=0 add. rt, ra, rb oe=0, rc=1 addo rt, ra, rb oe=1, rc=0 addo. rt, ra, rb oe=1, rc=1 31 0 31 rt ra 266 16 11 6 rb rc 21 22 oe section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-8 ? 2000 plx technology, inc. all rights reserved. addc add carrying (rt) (ra) + (rb) if (ra) + (rb) 2 32 ? 1 then xer[ca] 1 else xer[ca] 0 the sum of the contents of register ra and register rb is placed into register rt. xer[ca] is set to a value determined by the unsigned magnitude of the result of the add operation. registers altered rt xer[ca] cr[cr0] lt, gt, eq, so if rc contains 1 xer[so, ov] if oe contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. addc rt, ra, rb oe=0, rc=0 addc. rt, ra, rb oe=0, rc=1 addco rt, ra, rb oe=1, rc=0 addco. rt, ra, rb oe=1, rc=1 31 0 31 rt ra 10 16 11 6 rb rc 21 22 oe > u section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-9 section 28 ? cpu instr set adde add extended (rt) (ra) + (rb) + xer[ca] if (ra) + (rb) + xer[ca] 2 32 ? 1 then xer[ca] 1 else xer[ca] 0 the sum of the contents of register ra, register rb, and xer[ca] is placed into register rt. xer[ca] is set to a value determined by the unsigned magnitude of the result of the add operation. registers altered rt xer[ca] cr[cr0] lt, gt, eq, so if rc contains 1 xer[so, ov] if oe contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. adde rt, ra, rb oe=0, rc=0 adde. rt, ra, rb oe=0, rc=1 addeo rt, ra, rb oe=1, rc=0 addeo. rt, ra, rb oe=1, rc=1 31 0 31 rt ra 138 16 11 6 rb rc 21 22 oe > u section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-10 ? 2000 plx technology, inc. all rights reserved. addi add immediate (rt) (ra|0) + exts(im) if the ra field is 0, the im field, sign-extended to 32 bits, is placed into register rt. if the ra field is nonzero, the sum of the contents of register ra and the contents of the im field, sign-extended to 32 bits, is placed into register rt. registers altered rt programming note to place an immediate, sign-extended value into the gpr specified by the rt field, set the ra field to 0. architecture note this instruction is part of the powerpc user instruction set architecture. addi rt, ra, im table 28-4. extended mnemonics for addi mnemonic operands function other registers changed lal rt, d(ra) load address (ra 0); d is an offset from a base address that is assumed to be (ra). (rt) (ra) + exts(d) extended mnemonic for addi rt,ra,d li rt, im load immediate. (rt) exts(im) extended mnemonic for addi rt,0,im subi rt, ra, im subtract exts(im) from (ra|0). place result in rt. extended mnemonic for addi rt,ra, ? im 14 0 31 rt ra im 16 11 6 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-11 section 28 ? cpu instr set addic add immediate carrying (rt) (ra) + exts(im) if (ra) + exts(im) 2 32 ? 1 then xer[ca] 1 else xer[ca] 0 the sum of the contents of register ra and the contents of the im field, sign-extended to 32 bits, is placed into register rt. xer[ca] is set to a value determined by the unsigned magnitude of the result of the add operation. registers altered rt xer[ca] architecture note this instruction is part of the powerpc user instruction set architecture. addic rt, ra, im table 28-5. extended mnemonics for addic mnemonic operands function other registers changed subic rt, ra, im subtract exts(im) from (ra) place result in rt; place carry-out in xer[ca]. extended mnemonic for addic rt,ra, ? im 12 0 31 rt ra im 16 11 6 > u section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-12 ? 2000 plx technology, inc. all rights reserved. addic. add immediate carrying and record (rt) (ra) + exts(im) if (ra) + exts(im) 2 32 ? 1 then xer[ca] 1 else xer[ca] 0 the sum of the contents of register ra and the contents of the im field, sign-extended to 32 bits, is placed into register rt. xer[ca] is set to a value determined by the unsigned magnitude of the result of the add operation. registers altered rt xer[ca] cr[cr0] lt, gt, eq, so programming note addic. is one of three instructions that implicitly update cr[cr0] without having an rc field. the other instructions are andi. and andis. architecture note this instruction is part of the powerpc user instruction set architecture. addic. rt, ra, im table 28-6. extended mnemonics for addic. mnemonic operands function other registers changed subic. rt, ra, im subtract exts(im) from (ra). place result in rt; place carry-out in xer[ca]. extended mnemonic for addic. rt,ra, ? im cr[cr0] 13 0 31 rt ra im 16 11 6 > u section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-13 section 28 ? cpu instr set addis add immediate shifted (rt) (ra|0) + (im || 16 0) if the ra field is 0, the im field is concatenated on its right with sixteen 0-bits and placed into register rt. if the ra field is nonzero, the contents of register ra are added to the contents of the extended im field. the sum is stored into register rt. registers altered rt programming note an addi instruction stores a sign-extended 16-bit value in a gpr. an addis instruction followed by an ori instruction stores an arbitrary 32-bit value in a gpr, as shown in the following example: addis rt, 0, high 16 bits of value ori rt, rt, low 16 bits of value architecture note this instruction is part of the powerpc user instruction set architecture. addis rt, ra, im table 28-7. extended mnemonics for addis mnemonic operands function other registers changed lis rt, im load immediate shifted. (rt) (im || 16 0) extended mnemonic for addis rt,0,im subis rt, ra, im subtract (im || 16 0) from (ra|0). place result in rt. extended mnemonic for addis rt,ra, ? im 15 0 31 rt ra im 16 11 6 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-14 ? 2000 plx technology, inc. all rights reserved. addme add to minus one extended (rt) (ra) + xer[ca] + ( ? 1) if (ra) + xer[ca] + 0xffff ffff 2 32 ? 1 then xer[ca] 1 else xer[ca] 0 the sum of the contents of register ra, xer[ca], and ? 1 is placed into register rt. xer[ca] is set to a value determined by the unsigned magnitude of the result of the add operation. registers altered rt xer[ca] cr[cr0] lt, gt, eq, so if rc contains 1 xer[so, ov] if oe contains 1 invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. addme rt, ra oe=0, rc=0 addme. rt, ra oe=0, rc=1 addmeo rt, ra oe=1, rc = 0 addmeo. rt, ra oe=1, rc=1 31 0 31 rt ra 234 16 11 6 rc 21 22 oe > u section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-15 section 28 ? cpu instr set addze add to zero extended (rt) (ra) + xer[ca] if (ra) + xer[ca] 2 32 ? 1 then xer[ca] 1 else xer[ca] 0 the sum of the contents of register ra and xer[ca] is placed into register rt. xer[ca] is set to a value determined by the unsigned magnitude of the result of the add operation. registers altered rt xer[ca] cr[cr0] lt, gt, eq, so if rc contains 1 xer[so, ov] if oe contains 1 invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. addze rt, ra oe=0, rc=0 addze. rt, ra oe=0, rc=1 addzeo rt, ra oe=1, rc=0 addzeo. rt, ra oe=1, rc=1 31 0 31 rt ra 202 16 11 6 rc 21 22 oe > u section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-16 ? 2000 plx technology, inc. all rights reserved. and and (ra) (rs) (rb) the contents of register rs is anded with the contents of register rb and the result is placed into register ra. registers altered ra cr[cr0] lt, gt, eq, so if rc contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. and ra, rs, rb rc=0 and. ra, rs, rb rc=1 31 0 31 rs ra 28 16 11 6 rb rc 21 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-17 section 28 ? cpu instr set andc and with complement (ra) (rs) ? (rb) the contents of register rs is anded with the ones complement of the contents of register rb; the result is placed into register ra. registers altered ra cr[cr0] lt, gt, eq, so if rc contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. andc ra,rs,rb rc=0 andc. ra,rs,rb rc=1 31 0 31 rs ra 60 16 11 6 rb rc 21 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-18 ? 2000 plx technology, inc. all rights reserved. andi. and immediate (ra) (rs) ( 16 0 || im) the im field is extended to 32 bits by concatenating 16 0-bits on its left. the contents of register rs is anded with the extended im field; the result is placed into register ra. registers altered ra cr[cr0] lt, gt, eq, so programming note the andi. instruction can test whether any of the 16 least-significant bits in a gpr are 1-bits. andi. is one of three instructions that implicitly update cr[cr0] without having an rc field. the other instructions are addic. and andis. . architecture note this instruction is part of the powerpc user instruction set architecture. andi. ra, rs, im 28 0 31 rs ra im 16 11 6 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-19 section 28 ? cpu instr set andis. and immediate shifted (ra) (rs) (im || 16 0) the im field is extended to 32 bits by concatenating 16 0-bits on its right. the contents of register rs are anded with the extended im field; the result is placed into register ra. registers altered ra cr[cr0] lt, gt, eq, so programming note the andis. instruction can test whether any of the 16 most-significant bits in a gpr are 1-bits. andis. is one of three instructions that implicitly update cr[cr0] without having an rc field. the other instructions are addic. and andi. . architecture note this instruction is part of the powerpc user instruction set architecture. andis. ra, rs, im 29 0 31 rs ra im 16 11 6 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-20 ? 2000 plx technology, inc. all rights reserved. b branch if aa = 1 then li target 6:29 nia exts(li || 2 0) else li (target ? cia) 6:29 nia cia + exts(li || 2 0) if lk = 1 then (lr) cia + 4 pc nia the next instruction address (nia) is the effective address of the branch. the nia is formed by adding a displacement to a base address. the displacement is obtained by concatenating two 0-bits to the right of the li field and sign-extending the result to 32 bits. if the aa field contains 0, the base address is the address of the branch instruction, which is also the current instruction address (cia). if the aa field contains 1, the base address is 0. program flow is transferred to the nia. if the lk field contains 1, then (cia + 4) is placed into the lr. registers altered lr if lk contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. btarget aa=0, lk=0 ba target aa=1, lk=0 bl target aa=0, lk=1 bla target aa=1, lk=1 18 0 31 6 30 li aa lk section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-21 section 28 ? cpu instr set bc branch conditional if bo 2 = 0 then ctr ctr ? 1 if (bo 2 = 1 ((ctr = 0) = bo 3 )) (bo 0 =1 (cr bi = bo 1 )) then if aa = 1 then bd target 16:29 nia exts(bd || 2 0) else bd (target ? cia) 16:29 nia cia + exts(bd || 2 0) else nia cia + 4 if lk = 1 then (lr) cia + 4 pc nia if bit 2 of the bo field contains 0, the ctr is decremented. the bi field specifies a bit in the cr to be used as the condition of the branch. the next instruction address (nia) is the effective address of the branch. the nia is formed by adding a displacement to a base address. the displacement is obtained by concatenating two 0-bits to the right of the bd field and sign-extending the result to 32 bits. if the aa field contains 0, the base address is the address of the branch instruction, which is also the current instruction address (cia). if the aa field contains 1, the base address is 0. the bo field controls options that determine when program flow is transferred to the nia. the bo field also controls branch prediction, a performance-improvement feature. see section 24.6.4, ? bo field on conditional branches, ? on page 24-22, and section 24.6.5, ? branch prediction, ? on page 24-23, for a complete discussion. if the lk field contains 1, then (cia + 4) is placed into the lr. registers altered ctr if bo 2 contains 0 lr if lk contains 1 bc bo, bi, target aa=0, lk= 0 bca bo, bi, target aa =1, lk= 0 bcl bo, bi, target aa= 0, lk=1 bcla bo, bi, target aa=1, lk=1 16 0 31 bo bi bd 16 11 6 30 aa lk section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-22 ? 2000 plx technology, inc. all rights reserved. architecture note this instruction is part of the powerpc user instruction set architecture. table 28-8. extended mnemonics for bc, bca, bcl, bcla mnemonic operands function other registers changed bdnz target decrement ctr; branch if ctr 0. extended mnemonic for bc 16,0,target bdnza extended mnemonic for bca 16,0,target bdnzl extended mnemonic for bcl 16,0,target (lr) cia + 4. bdnzla extended mnemonic for bcla 16,0,target (lr) cia + 4. bdnzf cr_bit, target decrement ctr; branch if ctr 0 and cr cr_bit = 0. extended mnemonic for bc 0,cr_bit,target bdnzfa extended mnemonic for bca 0,cr_bit,target bdnzfl extended mnemonic for bcl 0,cr_bit,target (lr) cia + 4. bdnzfla extended mnemonic for bcla 0,cr_bit,target (lr) cia + 4. bdnzt cr_bit, target decrement ctr; branch if ctr 0 and cr cr_bit = 1. extended mnemonic for bc 8,cr_bit,target bdnzta extended mnemonic for bca 8,cr_bit,target bdnztl extended mnemonic for bcl 8,cr_bit,target (lr) cia + 4. bdnztla extended mnemonic for bcla 8,cr_bit,target (lr) cia + 4. bdz target decrement ctr; branch if ctr = 0. extended mnemonic for bc 18,0,target bdza extended mnemonic for bca 18,0,target bdzl extended mnemonic for bcl 18,0,target (lr) cia + 4. bdzla extended mnemonic for bcla 18,0,target (lr) cia + 4. bdzf cr_bit, target decrement ctr; branch if ctr = 0 and cr cr_bit = 0. extended mnemonic for bc 2,cr_bit,target bdzfa extended mnemonic for bca 2,cr_bit,target bdzfl extended mnemonic for bcl 2,cr_bit,target (lr) cia + 4. bdzfla extended mnemonic for bcla 2,cr_bit,target (lr) cia + 4. section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-23 section 28 ? cpu instr set bdzt cr_bit, target decrement ctr; branch if ctr = 0 and cr cr_bit = 1. extended mnemonic for bc 10,cr_bit,target bdzta extended mnemonic for bca 10,cr_bit,target bdztl extended mnemonic for bcl 10,cr_bit,target (lr) cia + 4. bdztla extended mnemonic for bcla 10,cr_bit,target (lr) cia + 4. beq [cr_field,] target branch if equal; use cr0 if cr_field is omitted. extended mnemonic for bc 12,4 ? cr_field+2,target beqa extended mnemonic for bca 12,4 ? cr_field+2,target beql extended mnemonic for bcl 12,4 ? cr_field+2,target (lr) cia + 4. beqla extended mnemonic for bcla 12,4 ? cr_field+2,target (lr) cia + 4. bf cr_bit, target branch if cr cr_bit = 0. extended mnemonic for bc 4,cr_bit,target bfa extended mnemonic for bca 4,cr_bit,target bfl extended mnemonic for bcl 4,cr_bit,target lr bfla extended mnemonic for bcla 4,cr_bit,target lr bge [cr_field,] target branch if greater than or equal; use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+0,target bgea extended mnemonic for bca 4,4 ? cr_field+0,target bgel extended mnemonic for bcl 4,4 ? cr_field+0,target lr bgela extended mnemonic for bcla 4,4 ? cr_field+0,target lr bgt [cr_field,] target branch if greater than; use cr0 if cr_field is omitted. extended mnemonic for bc 12,4 ? cr_field+1,target bgta extended mnemonic for bca 12,4 ? cr_field+1,target bgtl extended mnemonic for bcl 12,4 ? cr_field+1,target lr bgtla extended mnemonic for bcla 12,4 ? cr_field+1,target lr table 28-8. extended mnemonics for bc, bca, bcl, bcla mnemonic operands function other registers changed section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-24 ? 2000 plx technology, inc. all rights reserved. ble [cr_field,] target branch if less than or equal; use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+1,target blea extended mnemonic for bca 4,4 ? cr_field+1,target blel extended mnemonic for bcl 4,4 ? cr_field+1,target lr blela extended mnemonic for bcla 4,4 ? cr_field+1,target lr blt [cr_field,] target branch if less than; use cr0 if cr_field is omitted. extended mnemonic for bc 12,4 ? cr_field+0,target blta extended mnemonic for bca 12,4 ? cr_field+0,target bltl extended mnemonic for bcl 12,4 ? cr_field+0,target (lr) cia + 4. bltla extended mnemonic for bcla 12,4 ? cr_field+0,target (lr) cia + 4. bne [cr_field,] target branch if not equal; use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+2,target bnea extended mnemonic for bca 4,4 ? cr_field+2,target bnel extended mnemonic for bcl 4,4 ? cr_field+2,target (lr) cia + 4. bnela extended mnemonic for bcla 4,4 ? cr_field+2,target (lr) cia + 4. bng [cr_field,] target branch if not greater than; use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+1,target bnga extended mnemonic for bca 4,4 ? cr_field+1,target bngl extended mnemonic for bcl 4,4 ? cr_field+1,target (lr) cia + 4. bngla extended mnemonic for bcla 4,4 ? cr_field+1,target (lr) cia + 4. bnl [cr_field,] target branch if not less than; use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+0,target bnla extended mnemonic for bca 4,4 ? cr_field+0,target bnll extended mnemonic for bcl 4,4 ? cr_field+0,target (lr) cia + 4. bnlla extended mnemonic for bcla 4,4 ? cr_field+0,target (lr) cia + 4. table 28-8. extended mnemonics for bc, bca, bcl, bcla mnemonic operands function other registers changed section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-25 section 28 ? cpu instr set bns [cr_field,] target branch if not summary overflow; use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+3,target bnsa extended mnemonic for bca 4,4 ? cr_field+3,target bnsl extended mnemonic for bcl 4,4 ? cr_field+3,target (lr) cia + 4. bnsla extended mnemonic for bcla 4,4 ? cr_field+3,target (lr) cia + 4. bnu [cr_field,] target branch if not unordered; use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+3,target bnua extended mnemonic for bca 4,4 ? cr_field+3,target bnul extended mnemonic for bcl 4,4 ? cr_field+3,target (lr) cia + 4. bnula extended mnemonic for bcla 4,4 ? cr_field+3,target (lr) cia + 4. bso [cr_field,] target branch if summary overflow; use cr0 if cr_field is omitted. extended mnemonic for bc 12,4 ? cr_field+3,target bsoa extended mnemonic for bca 12,4 ? cr_field+3,target bsol extended mnemonic for bcl 12,4 ? cr_field+3,target (lr) cia + 4. bsola extended mnemonic for bcla 12,4 ? cr_field+3,target (lr) cia + 4. bt cr_bit, target branch if cr cr_bit = 1. extended mnemonic for bc 12,cr_bit,target bta extended mnemonic for bca 12,cr_bit,target btl extended mnemonic for bcl 12,cr_bit,target (lr) cia + 4. btla extended mnemonic for bcla 12,cr_bit,target (lr) cia + 4. bun [cr_field], target branch if unordered; use cr0 if cr_field is omitted. extended mnemonic for bc 12,4 ? cr_field+3,target buna extended mnemonic for bca 12,4 ? cr_field+3,target bunl extended mnemonic for bcl 12,4 ? cr_field+3,target (lr) cia + 4. bunla extended mnemonic for bcla 12,4 ? cr_field+3,target (lr) cia + 4. table 28-8. extended mnemonics for bc, bca, bcl, bcla mnemonic operands function other registers changed section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-26 ? 2000 plx technology, inc. all rights reserved. bcctr branch conditional to count register if bo 2 = 0 then ctr ctr ? 1 if (bo 2 = 1 ((ctr = 0) = bo 3 )) (bo 0 =1 (cr bi =bo 1 )) then nia ctr 0:29 || 2 0 else nia cia + 4 if lk = 1 then (lr) cia + 4 pc nia the bi field specifies a bit in the cr to be used as the condition of the branch. the next instruction address (nia) is the target address of the branch. the nia is formed by concatenating the 30 most significant bits of the ctr with two 0-bits on the right. the bo field controls options that determine when program flow is transferred to the nia. the bo field also controls branch prediction, a performance-improvement feature. see section 24.6.4, ? bo field on conditional branches, ? on page 24-22, and section 24.6.5, ? branch prediction, ? on page 24-23, for a complete discussion. if the lk field contains 1, then (cia + 4) is placed into the lr. registers altered ctr if bo 2 contains 0 lr if lk contains 1 invalid instruction forms reserved fields if bit 2 of the bo field contains 0, the instruction form is invalid, but the pseudocode applies. if the branch condition is true, the branch is taken; the nia is the contents of the ctr after it is decremented. architecture note this instruction is part of the powerpc user instruction set architecture. bcctr bo, bi lk = 0 bcctrl bo, bi lk =1 19 0 31 bo bi 16 11 6 21 lk 528 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-27 section 28 ? cpu instr set table 28-9. extended mnemonics for bcctr, bcctrl mnemonic operands function other registers changed bctr branch unconditionally to address in ctr. extended mnemonic for bcctr 20,0 bctrl extended mnemonic for bcctrl 20,0 (lr) cia + 4. beqctr [cr_field] branch, if equal, to address in ctr; use cr0 if cr_field is omitted. extended mnemonic for bcctr 12,4 ? cr_field+2 beqctrl extended mnemonic for bcctrl 12,4 ? cr_field+2 (lr) cia + 4. bfctr cr_bit branch, if cr cr_bit = 0, to address in ctr. extended mnemonic for bcctr 4,cr_bit bfctrl extended mnemonic for bcctrl 4,cr_bit (lr) cia + 4. bgectr [cr_field] branch, if greater than or equal, to address in ctr; use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+0 bgectrl extended mnemonic for bcctrl 4,4 ? cr_field+0 (lr) cia + 4. bgtctr [cr_field] branch, if greater than, to address in ctr; use cr0 if cr_field is omitted. extended mnemonic for bcctr 12,4 ? cr_field+1 bgtctrl extended mnemonic for bcctrl 12,4 ? cr_field+1 (lr) cia + 4. blectr [cr_field] branch, if less than or equal, to address in ctr; use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+1 blectrl extended mnemonic for bcctrl 4,4 ? cr_field+1 (lr) cia + 4. bltctr [cr_field] branch, if less than, to address in ctr; use cr0 if cr_field is omitted. extended mnemonic for bcctr 12,4 ? cr_field+0 bltctrl extended mnemonic for bcctrl 12,4 ? cr_field+0 (lr) cia + 4. bnectr [cr_field] branch, if not equal, to address in ctr; use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+2 bnectrl extended mnemonic for bcctrl 4,4 ? cr_field+2 (lr) cia + 4. bngctr [cr_field] branch, if not greater than, to address in ctr; use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+1 bngctrl extended mnemonic for bcctrl 4,4 ? cr_field+1 (lr) cia + 4. section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-28 ? 2000 plx technology, inc. all rights reserved. bnlctr [cr_field] branch, if not less than, to address in ctr; use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+0 bnlctrl extended mnemonic for bcctrl 4,4 ? cr_field+0 (lr) cia + 4. bnsctr [cr_field] branch, if not summary overflow, to address in ctr; use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+3 bnsctrl extended mnemonic for bcctrl 4,4 ? cr_field+3 (lr) cia + 4. bnuctr [cr_field] branch, if not unordered, to address in ctr; use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+3 bnuctrl extended mnemonic for bcctrl 4,4 ? cr_field+3 (lr) cia + 4. bsoctr [cr_field] branch, if summary overflow, to address in ctr; use cr0 if cr_field is omitted. extended mnemonic for bcctr 12,4 ? cr_field+3 bsoctrl extended mnemonic for bcctrl 12,4 ? cr_field+3 (lr) cia + 4. btctr cr_bit branch if cr cr_bit = 1 to address in ctr. extended mnemonic for bcctr 12,cr_bit btctrl extended mnemonic for bcctrl 12,cr_bit (lr) cia + 4. bunctr [cr_field] branch if unordered to address in ctr; use cr0 if cr_field is omitted. extended mnemonic for bcctr 12,4 ? cr_field+3 bunctrl extended mnemonic for bcctrl 12,4 ? cr_field+3 (lr) cia + 4. table 28-9. extended mnemonics for bcctr, bcctrl mnemonic operands function other registers changed section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-29 section 28 ? cpu instr set bclr branch conditional to link register if bo 2 = 0 then ctr ctr ? 1 if (bo 2 = 1 ((ctr = 0) = bo 3 )) (bo 0 =1 (cr bi =bo 1 )) then nia lr 0:29 || 2 0 else nia cia + 4 if lk = 1 then (lr) cia + 4 pc nia if bit 2 of the bo field contains 0, the ctr is decremented. the bi field specifies a bit in the cr to be used as the condition of the branch. the next instruction address (nia) is the target address of the branch. the nia is formed by concatenating the 30 most significant bits of the lr with two 0-bits on the right. the bo field controls options that determine when program flow is transferred to the nia. the bo field also controls branch prediction, a performance-improvement feature. see section 24.6.4, ? bo field on conditional branches, ? on page 24-22, and section 24.6.5, ? branch prediction, ? on page 24-23, for a complete discussion. if the lk field contains 1, then (cia + 4) is placed into the lr. registers altered ctr if bo 2 contains 0 lr if lk contains 1 invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. bclr bo, bi lk = 0 bclrl bo, bi lk =1 19 0 31 bo bi 16 16 11 6 21 lk section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-30 ? 2000 plx technology, inc. all rights reserved. table 28-10. extended mnemonics for bclr, bclrl mnemonic operands function other registers changed blr branch unconditionally to address in lr. extended mnemonic for bclr 20,0 blrl extended mnemonic for bclrl 20,0 (lr) cia + 4. bdnzlr decrement ctr; branch if ctr 0, to address in lr. extended mnemonic for bclr 16,0 bdnzlrl extended mnemonic for bclrl 16,0 (lr) cia + 4. bdnzflr cr_bit decrement ctr; branch if ctr 0 and cr cr_bit = 0 to address in lr. extended mnemonic for bclr 0,cr_bit bdnzflrl extended mnemonic for bclrl 0,cr_bit (lr) cia + 4. bdnztlr cr_bit decrement ctr; branch if ctr 0 and cr cr_bit = 1 to address in lr. extended mnemonic for bclr 8,cr_bit bdnztlrl extended mnemonic for bclrl 8,cr_bit (lr) cia + 4. bdzlr decrement ctr; branch if ctr = 0 to address in lr. extended mnemonic for bclr 18,0 bdzlrl extended mnemonic for bclrl 18,0 (lr) cia + 4. bdzflr cr_bit decrement ctr; branch if ctr = 0 and cr cr_bit = 0 to address in lr. extended mnemonic for bclr 2,cr_bit bdzflrl extended mnemonic for bclrl 2,cr_bit (lr) cia + 4. bdztlr cr_bit decrement ctr; branch if ctr = 0 and cr cr_bit = 1 to address in lr. extended mnemonic for bclr 10,cr_bit bdztlrl extended mnemonic for bclrl 10,cr_bit (lr) cia + 4. beqlr [cr_field] branch if equal to address in lr; use cr0 if cr_field is omitted. extended mnemonic for bclr 12,4 ? cr_field+2 beqlrl extended mnemonic for bclrl 12,4 ? cr_field+2 (lr) cia + 4. bflr cr_bit branch if cr cr_bit = 0 to address in lr. extended mnemonic for bclr 4,cr_bit bflrl extended mnemonic for bclrl 4,cr_bit (lr) cia + 4. section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-31 section 28 ? cpu instr set bgelr [cr_field] branch, if greater than or equal, to address in lr; use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+0 bgelrl extended mnemonic for bclrl 4,4 ? cr_field+0 (lr) cia + 4. bgtlr [cr_field] branch, if greater than, to address in lr; use cr0 if cr_field is omitted. extended mnemonic for bclr 12,4 ? cr_field+1 bgtlrl extended mnemonic for bclrl 12,4 ? cr_field+1 (lr) cia + 4. blelr [cr_field] branch, if less than or equal, to address in lr; use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+1 blelrl extended mnemonic for bclrl 4,4 ? cr_field+1 (lr) cia + 4. bltlr [cr_field] branch, if less than, to address in lr; use cr0 if cr_field is omitted. extended mnemonic for bclr 12,4 ? cr_field+0 bltlrl extended mnemonic for bclrl 12,4 ? cr_field+0 (lr) cia + 4. bnelr [cr_field] branch, if not equal, to address in lr; use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+2 bnelrl extended mnemonic for bclrl 4,4 ? cr_field+2 (lr) cia + 4. bnglr [cr_field] branch, if not greater than, to address in lr; use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+1 bnglrl extended mnemonic for bclrl 4,4 ? cr_field+1 (lr) cia + 4. bnllr [cr_field] branch, if not less than, to address in lr; use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+0 bnllrl extended mnemonic for bclrl 4,4 ? cr_field+0 (lr) cia + 4. bnslr [cr_field] branch if not summary overflow to address in lr; use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+3 bnslrl extended mnemonic for bclrl 4,4 ? cr_field+3 (lr) cia + 4. bnulr [cr_field] branch if not unordered to address in lr; use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+3 bnulrl extended mnemonic for bclrl 4,4 ? cr_field+3 (lr) cia + 4. table 28-10. extended mnemonics for bclr, bclrl mnemonic operands function other registers changed section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-32 ? 2000 plx technology, inc. all rights reserved. bsolr [cr_field] branch if summary overflow to address in lr; use cr0 if cr_field is omitted. extended mnemonic for bclr 12,4 ? cr_field+3 bsolrl extended mnemonic for bclrl 12,4 ? cr_field+3 (lr) cia + 4. btlr cr_bit branch if cr cr_bit = 1 to address in lr. extended mnemonic for bclr 12,cr_bit btlrl extended mnemonic for bclrl 12,cr_bit (lr) cia + 4. bunlr [cr_field] branch if unordered to address in lr; use cr0 if cr_field is omitted. extended mnemonic for bclr 12,4 ? cr_field+3 bunlrl extended mnemonic for bclrl 12,4 ? cr_field+3 (lr) cia + 4. table 28-10. extended mnemonics for bclr, bclrl mnemonic operands function other registers changed section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-33 section 28 ? cpu instr set cmp compare c 0:3 4 0 if (ra) < (rb) then c 0 1 if (ra) > (rb) then c 1 1 if (ra) = (rb) then c 2 1 c 3 xer[so] n bf cr[crn] c 0:3 the contents of register ra are compared with the contents of register rb using a 32-bit signed compare. the cr field specified by the bf field is updated to reflect the results of the compare and the value of xer[so] is placed into the same cr field. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered cr[crn] where n is specified by the bf field invalid instruction forms reserved fields programming note the powerpc architecture defines this instruction as cmp bf,l,ra,rb , where l selects operand size for 64-bit powerpc implementations. for all 32-bit powerpc implementations, l = 0 is required (l = 1 is an invalid form); hence for the iop 480 cpu, use of the extended mnemonic cmpw bf,ra,rb is recommended. architecture note this instruction is part of the powerpc user instruction set architecture. cmp bf, 0, ra, rb table 28-11. extended mnemonics for cmp mnemonic operands function other registers changed cmpw [bf,] ra, rb compare lword; use cr0 if bf is omitted. extended mnemonic for cmp bf,0,ra,rb 31 0 ra 0 16 11 6 rb 21 bf 9 31 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-34 ? 2000 plx technology, inc. all rights reserved. cmpi compare immediate c 0:3 4 0 if (ra) < exts(im) then c 0 1 if (ra) > exts(im) then c 1 1 if (ra) = exts(im) then c 2 1 c 3 xer[so] n bf cr[crn] c 0:3 the im field is sign-extended to 32 bits. the contents of register ra are compared with the extended im field, using a 32-bit signed compare. the cr field specified by the bf field is updated to reflect the results of the compare and the value of xer[so] is placed into the same cr field. registers altered cr[crn] where n is specified by the bf field invalid instruction forms reserved fields programming note the powerpc architecture defines this instruction as cmpi bf,l,ra,im , where l selects operand size for 64-bit powerpc implementations. for all 32-bit powerpc implementations, l = 0 is required (l = 1 is an invalid form); hence for iop 480 cpu, use of the extended mnemonic cmpwi bf,ra,im is recommended. architecture note this instruction is part of the powerpc user instruction set architecture. cmpi bf, 0, ra, im table 28-12. extended mnemonics for cmpi mnemonic operands function other registers changed cmpwi [bf,] ra, im compare lword immediate; use cr0 if bf is omitted. extended mnemonic for cmpi bf,0,ra,im 11 0 31 bf ra im 16 11 6 9 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-35 section 28 ? cpu instr set cmpl compare logical c 0:3 4 0 if (ra) (rb) then c 0 1 if (ra) (rb) then c 1 1 if (ra) (rb) then c 2 1 c 3 xer[so] n bf cr[crn] c 0:3 the contents of register ra are compared with the contents of register rb, using a 32-bit unsigned compare. the cr field specified by the bf field is updated to reflect the results of the compare and the value of xer[so] is placed into the same cr field. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered cr[crn] where n is specified by the bf field invalid instruction forms reserved fields programming notes the powerpc architecture defines this instruction as cmpl bf,l,ra,rb , where l selects operand size for 64-bit powerpc implementations. for all 32-bit powerpc implementations, l = 0 is required (l = 1 is an invalid form); hence for the iop 480 cpu, use of the extended mnemonic cmplw bf,ra,rb is recommended. architecture note this instruction is part of the powerpc user instruction set architecture. cmpl bf, 0, ra, rb table 28-13. extended mnemonics for cmpl mnemonic operands function other registers changed cmplw [bf,] ra, rb compare logical lword; use cr0 if bf is omitted. extended mnemonic for cmpl bf,0,ra,rb 31 0 ra 32 16 11 6 rb 21 bf 9 31 < u > u = section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-36 ? 2000 plx technology, inc. all rights reserved. cmpli compare logical immediate c 0:3 4 0 if (ra) ( 16 0 || im) then c 0 1 if (ra) ( 16 0 || im) then c 1 1 if (ra) ( 16 0 || im) then c 2 1 c 3 xer[so] n bf cr[crn] c 0:3 the im field is extended to 32 bits by concatenating 16 0-bits to its left. the contents of register ra are compared with im using a 32-bit unsigned compare. the cr field specified by the bf field is updated to reflect the results of the compare and the value of xer[so] is placed into the same cr field. registers altered cr[crn] where n is specified by the bf field invalid instruction forms reserved fields programming note the powerpc architecture defines this instruction as cmpli bf,l,ra,im , where l selects operand size for 64-bit powerpc implementations. for all 32-bit powerpc implementations, l = 0 is required (l = 1 is an invalid form); hence for the iop 480 cpu, use of the extended mnemonic cmplwi bf,ra,im is recommended. architecture note this instruction is part of the powerpc user instruction set architecture. cmpli bf, 0, ra, im table 28-14. extended mnemonics for cmpli mnemonic operands function other registers changed cmplwi [bf,] ra, im compare logical lword immediate; use cr0 if bf is omitted. extended mnemonic for cmpli bf,0,ra,im 10 0 31 bf ra im 16 11 6 9 < u > u = section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-37 section 28 ? cpu instr set cntlzw count leading zeros lword n 0 do while n < 32 if (rs) n = 1 then leave n n+1 (ra) n the consecutive leading 0 bits in register rs are counted; the count is placed into register ra. the count ranges from 0 through 32, inclusive. registers altered ra cr[cr0] lt, gt, eq, so if rc contains 1 invalid instruction forms reserved fields cntlzw ra, rs rc=0 cntlzw. ra, rs rc=1 31 0 31 rs ra 26 16 11 6 21 rc section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-38 ? 2000 plx technology, inc. all rights reserved. crand condition register and cr bt cr ba cr bb the cr bit specified by the ba field is anded with the cr bit specified by the bb field; the result is placed into the cr bit specified by the bt field. registers altered cr invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. crand bt, ba, bb 19 0 31 bt ba 257 16 11 6 21 bb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-39 section 28 ? cpu instr set crandc condition register and with complement cr bt cr ba ? cr bb the cr bit specified by the ba field is anded with the ones complement of the cr bit specified by the bb field; the result is placed into the cr bit specified by the bt field. registers altered cr invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. crandc bt, ba, bb 19 0 31 bt ba 129 16 11 6 21 bb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-40 ? 2000 plx technology, inc. all rights reserved. creqv condition register equivalent cr bt ? (cr ba cr bb ) the cr bit specified by the ba field is xored with the cr bit specified by the bb field; the ones complement of the result is placed into the cr bit specified by the bt field. registers altered cr invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. creqv bt, ba, bb table 28-15. extended mnemonics for creqv mnemonic operands function other registers changed crset bx condition register set. extended mnemonic for creqv bx,bx,bx 19 0 31 bt ba 289 16 11 6 21 bb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-41 section 28 ? cpu instr set crnand condition register nand cr bt ? (cr ba cr bb ) the cr bit specified by the ba field is anded with the cr bit specified by the bb field; the ones complement of the result is placed into the cr bit specified by the bt field. registers altered cr invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. crnand bt, ba, bb 19 0 31 bt ba 225 16 11 6 21 bb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-42 ? 2000 plx technology, inc. all rights reserved. crnor condition register nor cr bt ? (cr ba cr bb ) the cr bit specified by the ba field is ored with the cr bit specified by the bb field; the ones complement of the result is placed into the cr bit specified by the bt field. registers altered cr invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. crnor bt, ba, bb table 28-16. extended mnemonics for crnor mnemonic operands function other registers changed crnot bx, by condition register not. extended mnemonic for crnor bx,by,by 19 0 31 bt ba 33 16 11 6 21 bb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-43 section 28 ? cpu instr set cror condition register or cr bt cr ba cr bb the cr bit specified by the ba field is ored with the cr bit specified by the bb field; the result is placed into the cr bit specified by the bt field. registers altered cr invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. cror bt, ba, bb table 28-17. extended mnemonics for cror mnemonic operands function other registers changed crmove bx, by condition register move. extended mnemonic for cror bx,by,by 19 0 31 bt ba 449 16 11 6 21 bb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-44 ? 2000 plx technology, inc. all rights reserved. crorc condition register or with complement cr bt cr ba ? cr bb the condition register (cr) bit specified by the ba field is ored with the ones complement of the cr bit specified by the bb field; the result is placed into the cr bit specified by the bt field. registers altered cr invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. crorc bt, ba, bb 19 0 31 bt ba 417 16 11 6 21 bb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-45 section 28 ? cpu instr set crxor condition register xor cr bt cr ba cr bb the cr bit specified by the ba field is xored with the cr bit specified by the bb field; the result is placed into the cr bit specified by the bt field. registers altered cr invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. crxor bt, ba, bb table 28-18. extended mnemonics for crxor mnemonic operands function other registers changed crclr bx condition register clear. extended mnemonic for crxor bx,bx,bx 19 0 31 bt ba 193 16 11 6 21 bb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-46 ? 2000 plx technology, inc. all rights reserved. dcba data cache block allocate ea (ra|0) + (rb) dcba(ea) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. if the data block at the ea is in the data cache and the ea is marked as cacheable and non-write-through, the data in the cache block is architecturally undefined. for the iop 480 cpu, the cache data block is set to 0. if the data block at the ea is not in the data cache and the ea is marked as cacheable and not marked as write- through, a cache block is established and set to an architecturally-undefined value. note that no data is read from main storage, as described in the programming note. if the data block at the ea is marked as non-cacheable, a no-op occurs. if the data block at the ea is in the data cache and marked as write-through, architecturally the data in the cache block can remain unmodified. alternatively, the data block at the ea can be undefined in the data cache and in main storage. for the iop 480 cpu, a no-op occurs. if the data block at the ea is not in the data cache and marked as write-through, architecturally the instruction can establish a cache block and set the block to 0, or a no-op can occur. for the iop 480 cpu, a no-op occurs. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields programming notes because the dcba instruction can establish an address in the data cache without copying the contents of that address from main storage, the address established can be invalid with respect to main storage. a subsequent operation may cause the address to be copied back to main storage, for example, to make room for a new cache block; a machine check exception could occur under these circumstances. dcba provides a hint that a block of storage is soon to be stored or no longer needed; there is no need to retain the data in the block. establishing the line in the cache, without reading from main storage, improves performance. dcba ra, rb 31 0 31 ra 758 16 11 6 21 rb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-47 section 28 ? cpu instr set exceptions this instruction does not cause data storage exceptions (cache line locking or protection) or data tlb-miss exceptions. if conditions occur that would otherwise cause such an exception, dcba is treated as a no-op. this instruction is considered a ? store ? with respect to data address compare (dac) debug exceptions. see section 26.6.3.1, ? data address compare (dac) applied to cache instructions, ? on page 26-7, for more information. architecture note this instruction is part of the powerpc virtual environment architecture. section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-48 ? 2000 plx technology, inc. all rights reserved. dcbf data cache block flush ea (ra|0) + (rb) dcbf(ea) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. if the data block corresponding to the ea is in the data cache and marked as modified (stored into), the data block is copied back to main storage and then marked invalid in the data cache. if the data block is not marked as modified, it is simply marked invalid in the data cache. the operation is performed whether or not the ea is marked as cacheable. if the data block at the ea is not in the data cache, no operation is performed. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields exceptions this instruction is considered a ? load ? with respect to data storage exceptions (for the iop 480 cpu, these are cache line locking exceptions). see section 11.7.6, ? data storage exceptions, ? on page 11-21, for more information. this instruction is considered a ? store ? with respect to data address compare (dac) debug exceptions. see section 26.6.3.1, ? data address compare (dac) applied to cache instructions, ? on page 26-7, for more information. architecture note this instruction is part of the powerpc virtual environment architecture. dcbf ra, rb 31 0 31 ra 86 16 11 6 21 rb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-49 section 28 ? cpu instr set dcbi data cache block invalidate ea (ra|0) + (rb) dcbi(ea) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. if the data block at the ea is in the data cache, the data block is marked invalid, regardless of whether or not the ea is marked as cacheable. if modified data existed in the data block prior to the operation of this instruction, that data is lost. if the data block at the ea is not in the data cache, no operation is performed. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields programming notes execution of this instruction is privileged. exceptions this instruction is considered a ? store ? with respect to data storage exceptions. see section 11.7.6, ? data storage exceptions, ? on page 11-21, for more information. this instruction is considered a ? store ? with respect to data address compare (dac) debug exceptions. see section 26.6.3.1, ? data address compare (dac) applied to cache instructions, ? on page 26-7, for more information. architecture note this instruction is part of the powerpc operating environment architecture. dcbi ra, rb 31 0 31 ra 470 16 11 6 21 rb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-50 ? 2000 plx technology, inc. all rights reserved. dcbst data cache block store ea (ra|0) + (rb) dcbst(ea) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0, and is the contents of register ra otherwise. if the data block at the ea is in the data cache and marked as modified, the data block is copied back to main storage and marked as unmodified in the data cache. if the data block at the ea is in the data cache, and is not marked as modified, or if the data block at the ea is not in the data cache, no operation is performed. the operation specified by this instruction is performed whether or not the ea is marked as cacheable. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields exceptions this instruction is considered a ? load ? with respect to data storage exceptions. see section 11.7.6, ? data storage exceptions, ? on page 11-21, for more information. this instruction is considered a ? store ? with respect to data address compare (dac) debug exceptions. see section 26.6.3.1, ? data address compare (dac) applied to cache instructions, ? on page 26-7, for more information. architecture note this instruction is part of the powerpc virtual environment architecture. dcbst ra, rb 31 0 31 ra 54 16 11 6 21 rb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-51 section 28 ? cpu instr set dcbt data cache block touch ea (ra|0) + (rb) dcbt(ea) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 when the ra field is 0, and is the contents of register ra otherwise. if the data block at the ea is not in the data cache and the ea is marked as cacheable, the block is read from main storage into the data cache. if the data block at the ea is in the data cache, or if the ea is marked as non-cacheable, no operation is performed. this instruction is not allowed to cause data storage exceptions or data tlb miss exceptions. if execution of the instruction would cause such an exception, then no operation is performed, and no exception occurs. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields programming notes the dcbt instruction allows a program to begin a cache block fetch from main storage before the program needs the data. the program can later load data from the cache into registers without incurring the latency of a cache miss. exceptions this instruction is considered a ? load ? with respect to data storage exceptions. see section 11.7.6, ? data storage exceptions, ? on page 11-21, for more information. this instruction is considered a ? load ? with respect to data address compare (dac) debug exceptions. see section 26.6.3.1, ? data address compare (dac) applied to cache instructions, ? on page 26-7, for more information. architecture note this instruction is part of the powerpc virtual environment architecture. dcbt ra, rb 31 0 31 ra 278 16 11 6 21 rb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-52 ? 2000 plx technology, inc. all rights reserved. dcbtst data cache block touch for store ea (ra|0) + (rb) dcbtst(ea) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. if the data block at the ea is not in the data cache and the ea address is marked as cacheable, the data block is loaded into the data cache. if the ea is marked as non-cacheable, or if the data block at the ea is in the data cache, no operation is performed. this instruction is not allowed to cause data storage exceptions or data tlb miss exceptions. if execution of the instruction would cause such an exception, then no operation is performed, and no exception occurs. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields programming notes the dcbtst instruction allows a program to begin a cache block fetch from main storage before the program needs the data. the program can later store data from gprs into the cache block, without incurring the latency of a cache miss. architecturally, dcbtst brings data into the cache in ? exclusive ? mode, which allows the program to alter the cached data. ? exclusive ? mode is part of the mesi protocol for multi-processor systems, and is not implemented. the implementation of the dcbtst instruction is identical to the implementation of the dcbt instruction. exceptions this instruction is considered a ? load ? with respect to data storage exceptions. see section 11.7.6, ? data storage exceptions, ? on page 11-21, for more information. this instruction is considered a ? load ? with respect to data address compare (dac) debug exceptions. see section 26.6.3.1, ? data address compare (dac) applied to cache instructions, ? on page 26-7, for more information. architecture note this instruction is part of the powerpc virtual environment architecture. dcbtst ra, rb 31 0 31 ra 246 16 11 6 21 rb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-53 section 28 ? cpu instr set dcbz data cache block set to zero ea (ra|0) + (rb) dcbz(ea) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. if the data block at the ea is in the data cache and the ea is marked as cacheable and non-write-through, the data in the cache block is set to 0. if the data block at the ea is not in the data cache and the ea is marked as cacheable and non-write-through, a cache block is established and set to 0. note that nothing is read from main storage, as described in the programming note. if the data block at the ea is marked as either write-through or as non-cacheable, an alignment exception occurs. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields programming notes because the dcbz instruction can establish an address in the data cache without copying the contents of that address from main storage, the address established may be invalid with respect to the storage subsystem. a subsequent operation may cause the address to be copied back to main storage, for example, to make room for a new cache block; a machine check exception could occur under these circumstances. if dcbz is attempted to an ea which is marked as non-cacheable, the software alignment exception handler should emulate the instruction by storing zeros to the block in main storage. if a data block corresponding to the ea exists in the cache, but the ea is non-cacheable, stores (including dcbz ) to that address are considered programming errors (the cache block should previously have been flushed). dcbz ra, rb 31 0 31 ra 1014 16 11 6 21 rb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-54 ? 2000 plx technology, inc. all rights reserved. if the ea is marked as write-through, the software alignment exception handler should emulate the instruction by storing zeros to the block in main storage. an ea that is marked as write-through required should also be marked as cacheable; when dcbz is attempted to such an address, the alignment exception handler should maintain coherency of cache and memory. exceptions an alignment exception occurs if the ea is marked as non-cacheable or as write-through. this instruction is considered a ? store ? with respect to data storage exceptions (for the iop 480 cpu, these are cache line locking exceptions). see section 11.7.6, ? data storage exceptions, ? on page 11-21, for more information. this instruction is considered a ? store ? with respect to data address compare (dac) debug exceptions. see section 26.6.3.1, ? data address compare (dac) applied to cache instructions, ? on page 26-7, for more information. architecture note this instruction is part of the powerpc virtual environment architecture. section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-55 section 28 ? cpu instr set dccci data cache congruence class invalidate ea (ra|0) + (rb) dccci(ea) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. both cache lines in the congruence class specified by ea m :27 (where m is the number of bits in the cache array tag field) are invalidated, whether or not they match the ea. if modified data existed in the cache congruence class before the operation of this instruction, that data is lost. the operation specified by this instruction is performed whether or not the ea is marked as cacheable. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields programming note execution of this instruction is privileged. this instruction is intended for use in the power-on reset routine to invalidate the entire data cache tag array before enabling the data cache. a series of dccci instruction should be executed, one for each congruence class. cacheability can then be enabled. exceptions this instruction is considered a ? store ? with respect to data storage exceptions. see section 11.7.6, ? data storage exceptions, ? on page 11-21, for more information. the execution of a dccci instruction can cause a data tlb miss exception, at the specified ea, regardless of the non-specific intent of that ea. this instruction does not cause data address compare (dac) debug exceptions. see section 26.6.3.1, ? data address compare (dac) applied to cache instructions, ? on page 26-7, for more information. architecture note programs using this instruction are not portable to powerpc implementations that do not implement the ibm powerpc embedded environment. dccci ra, rb 31 0 31 ra 454 16 11 6 21 rb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-56 ? 2000 plx technology, inc. all rights reserved. dcread data cache read ea (ra|0) + (rb) if ((cdbcr[cis] = 0) (cdbcr[cws] = 0)) then (rt) (d-cache data, way a) if ((cdbcr[cis] = 0) (cdbcr[cws] = 1)) then (rt) (d-cache data, way b) if ((cdbcr[cis] = 1) (cdbcr[cws] = 0)) then (rt) (d-cache tag, way a) if ((cdbcr[cis] = 1) (cdbcr[cws] = 1)) then (rt) (d-cache tag, way b) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. this instruction is a debugging tool for reading the data cache entries for the congruence class specified by ea m :27 (where m is the number of bits in the cache array tag field). the cache information is read into register rt. if (cdbcr[cis] = 0), the information is an lword of data cache data from the addressed congruence class. the lword is specified by ea 28:29 ; ea 0: m ? 1 are ignored. if ea 30:31 are not 00, an alignment exception occurs. if (cdbcr[cws] = 0), the data is from the a-way, otherwise the data are from the b-way. if (cdbcr[cis] = 1), the information is a cache tag from the addressed congruence class; ea 0: m ? 1 and ea 28:31 are ignored. if (cdbcr[cws] = 0), the tag is from the a-way, otherwise the tag is from the b-way. data cache tag information is placed into register rt as follows: if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. dcread rt, ra, rb table 28-19. data cache array tag information 0: m ? 1 tag cache tag tag size is determined by cdbcr[dsd]. see section 25.7, ? icu and dcu performance modeling, ? on page 25-14, for more information. m :24 reserved the size of this field depends on the size of the tag field. 25 lk cache line lock 0 unlocked 1 locked 26 d cache line dirty 0 not dirty 1 dirty 27 v cache line valid 0not valid 1valid 28:30 reserved 31 lru least recently used (lru) 0 a-way lru 1 b-way lru 31 0 31 rt ra 486 16 11 6 21 rb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-57 section 28 ? cpu instr set registers altered rt invalid instruction forms reserved fields programming note execution of this instruction is privileged. exceptions if ea is not lword-aligned, an alignment exception occurs. this instruction is considered a ? load ? with respect to data storage exceptions. see section 11.7.6, ? data storage exceptions, ? on page 11-21, for more information. the execution of a dcread instruction can cause a data tlb miss exception, at the specified ea, regardless of the non-specific intent of that effective address. this instruction is considered a ? load ? with respect to data address compare (dac) debug exceptions. see section 26.6.3.1, ? data address compare (dac) applied to cache instructions, ? on page 26-7, for more information. architecture note programs using this instruction are not portable to powerpc implementations that do not implement the ibm powerpc embedded environment. section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-58 ? 2000 plx technology, inc. all rights reserved. divw divide lword (rt) (ra) (rb) the contents of register ra are divided by the contents of register rb. the quotient is placed into register rt. both the dividend and the divisor are interpreted as signed integers. the quotient is the unique signed integer that satisfies: dividend = (quotient divisor) + remainder where the remainder has the same sign as the dividend and its magnitude is less than that of the divisor. if an attempt is made to perform (0x8000 0000 ? 1) or ( n 0), the contents of register rt are undefined; if the rc field also contains 1, the contents of cr[cr0] lt, gt, eq are undefined. either invalid division operation sets xer[ov, so] to 1 if the oe field contains 1. registers altered rt cr[cr0] lt, gt, eq, so if rc contains 1 xer[ov, so] if oe contains 1 programming note the 32-bit remainder can be calculated using the following sequence of instructions: divw rt,ra,rb # rt = quotient mullw rt,rt,rb # rt = quotient divisor subf rt,rt,ra # rt = remainder the sequence does not calculate correct results for the invalid divide operations. architecture note this instruction is part of the powerpc user instruction set architecture. divw rt, ra, rb oe=0, rc=0 divw. rt, ra, rb oe=0, rc=1 divwo rt, ra, rb oe=1, rc=0 divwo. rt, ra, rb oe=1, rc=1 31 0 31 rt ra 491 16 11 6 rc 21 22 oe rb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-59 section 28 ? cpu instr set divwu divide lword unsigned (rt) (ra) (rb) the contents of register ra are divided by the contents of register rb. the quotient is placed into register rt. the dividend and the divisor are interpreted as unsigned integers. the quotient is the unique unsigned integer that satisfies dividend = (quotient divisor) + remainder if an attempt is made to perform ( n 0), the contents of register rt are undefined; if the rc also contains 1, the contents of cr[cr0] lt, gt, eq are also undefined. the invalid division operation also sets xer[ov, so] to 1 if the oe field contains 1. registers altered rt cr[cr0] lt, gt, eq, so if rc contains 1 xer[ov, so] if oe contains 1 programming note the 32-bit remainder can be calculated using the following sequence of instructions divwu rt,ra,rb # rt = quotient mullw rt,rt,rb # rt = quotient divisor subf rt,rt,ra # rt = remainder this sequence does not calculate the correct result if the divisor is zero. architecture note this instruction is part of the powerpc user instruction set architecture. divwu rt, ra, rb oe=0, rc=0 divwu. rt, ra, rb oe=0, rc=1 divwuo rt, ra, rb oe=1, rc=0 divwuo. rt, ra, rb oe=1, rc=1 31 0 31 rt ra 459 16 11 6 rc 21 22 oe rb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-60 ? 2000 plx technology, inc. all rights reserved. eieio enforce in order execution of i/o the eieio instruction ensures that all loads and stores preceding an eieio instruction complete with respect to main storage before any loads and stores following the eieio instruction access main storage. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields programming note architecturally, eieio orders storage access, not instruction completion. therefore, non-storage operations after eieio could complete before storage operations that were before eieio . the sync instruction guarantees ordering of both instruction completion and storage access. for the iop 480 cpu, the eieio instruction is implemented to behave as a sync instruction. to write code which is portable between various powerpc implementations, programmers should use the mnemonic which corresponds to the desired behavior. architecture note this instruction is part of the powerpc virtual environment architecture. eieio 31 0 31 854 6 21 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-61 section 28 ? cpu instr set eqv equivalent (ra) ? ((rs) (rb)) the contents of register rs are xored with the contents of register rb; the ones complement of the result is placed into register ra. registers altered ra cr[cr0] lt, gt, eq, so if rc contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. eqv ra, rs, rb rc=0 eqv. ra, rs, rb rc=1 31 0 31 rs ra 284 16 11 6 rb rc 21 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-62 ? 2000 plx technology, inc. all rights reserved. extsb extend sign byte (ra) exts(rs) 24:31 the least significant byte of register rs is sign-extended to 32 bits by replicating bit 24 of the register into bits 0 through 23 of the result. the result is placed into register ra. registers altered ra cr[cr0] lt, gt, eq, so if rc contains 1 invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. extsb ra, rs rc=0 extsb. ra, rs rc=1 31 0 31 rs ra 954 16 11 6 rc 21 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-63 section 28 ? cpu instr set extsh extend sign word (ra) exts(rs) 16:31 the least significant word of register rs is sign-extended to 32 bits by replicating bit 16 of the register into bits 0 through 15 of the result. the result is placed into register ra. registers altered ra cr[cr0] lt, gt, eq, so if rc contains 1 invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. extsh ra, rs rc=0 extsh. ra, rs rc=1 31 0 31 rs ra 922 16 11 6 rc 21 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-64 ? 2000 plx technology, inc. all rights reserved. icbi instruction cache block invalidate ea (ra|0) + (rb) icbi(ea) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. if the instruction block at the ea is in the instruction cache, the cache block is marked invalid. if the instruction block at the ea is not in the instruction cache, no additional operation is performed. the operation specified by this instruction is performed whether or not the ea is marked as cacheable in the iccr. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields programming note instruction cache operations use msr[dr], not msr[ir], to determine translation of their operands. when data translation is disabled, cacheability for the ea of the operand of instruction cache operations is determined by the iccr, not the dccr. exceptions instruction storage exceptions and instruction-side tlb miss exceptions are associated with instruction fetching , not with instruction execution. exceptions that occur during the execution of instruction cache operations cause data-side exceptions (data storage exceptions and data tlb miss exceptions). this instruction is considered a ? load ? with respect to data storage exceptions (for the iop 480 cpu, these are cache line locking exceptions). see section 11.7.6, ? data storage exceptions, ? on page 11-21, for more information. this instruction is considered a ? load ? with respect to data address compare (dac) debug exceptions, but does not cause dac debug events. architecture note this instruction is part of the powerpc virtual environment architecture. icbi ra, rb 31 0 31 ra 982 16 11 6 21 rb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-65 section 28 ? cpu instr set icbt instruction cache block touch ea (ra|0) + (rb) icbt(ea) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. if the instruction block at the ea is not in the instruction cache, and is marked as cacheable, the instruction block is loaded into the instruction cache. if the instruction block at the ea is in the instruction cache, or if the ea is marked as non-cacheable, no operation is performed. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields programming notes execution of this instruction is privileged. this instruction allows a program to begin a cache block fetch from main storage before the program needs the instruction. the program can later branch to the instruction address and fetch the instruction from the cache without incurring the latency of a cache miss. instruction cache operations use msr[dr], not msr[ir], to determine translation of their operands. when data translation is disabled, cacheability for the effective address of the operand of instruction cache operations is determined by the iccr, not the dccr. exceptions instruction storage exceptions and instruction-side tlb miss exceptions are associated with instruction fetching , not with instruction execution. exceptions that occur during the execution of instruction cache operations cause data-side exceptions (data storage exceptions and data tlb miss exceptions). if the execution of an icbt instruction would cause a data tlb miss exception, no operation is performed and no exception occurs. icbt ra, rb 31 0 31 ra 262 16 11 6 21 rb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-66 ? 2000 plx technology, inc. all rights reserved. this instruction is considered a ? load ? with respect to protection exceptions, but cannot cause a data storage exception. this instruction is considered a ? load ? with respect to data address compare (dac) debug exceptions, but does not cause dac debug events. architecture note programs using this instruction are not portable to powerpc implementations that do not implement the ibm powerpc embedded environment. section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-67 section 28 ? cpu instr set iccci instruction cache congruence class invalidate ea (ra|0) + (rb) iccci(ea) an effective address is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. both cache lines in the congruence class specified by ea m ? 1:27 are invalidated, whether or not they match the effective address. the operation specified by this instruction is performed whether or not the effective address is marked cacheable. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields programming notes execution of this instruction is privileged. this instruction is intended for use in the power-on reset routine to invalidate the entire cache tag array before enabling the cache. a series of iccci instructions should be executed, one for each congruence class. cacheability can then be enabled. instruction cache operations use msr[dr], not msr[ir], to determine translation of their operands. when data translation is disabled, cacheability for the effective address of the operand of instruction cache operations is determined by the iccr, not the dccr. exceptions instruction storage exceptions and instruction-side tlb miss exceptions are associated with instruction fetching , not with instruction execution. exceptions that occur during the execution of instruction cache operations cause data-side exceptions (data storage exceptions and data tlb miss exceptions). the execution of an iccci instruction can cause a data tlb miss exception, at the specified effective address, regardless of the non-specific intent of that effective address. iccci ra, rb 31 0 31 ra 966 16 11 6 21 rb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-68 ? 2000 plx technology, inc. all rights reserved. this instruction is considered a ? load ? with respect to protection exceptions, but cannot cause a data storage exception. this instruction is considered a ? load ? with respect to data address compare (dac) debug exceptions, but does not cause dac debug events. architecture note programs using this instruction are not portable to powerpc implementations that do not implement the ibm powerpc embedded environment. section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-69 section 28 ? cpu instr set icread instruction cache read ea (ra|0) + (rb) if ((cdbcr[cis] = 0) (cdbcr[cws] = 0)) then (icdbdr) (i-cache data, way a) if ((cdbcr[cis] = 0) (cdbcr[cws] = 1)) then (icdbdr) (i-cache data, way b) if ((cdbcr[cis] = 1) (cdbcr[cws] = 0)) then (icdbdr) (i-cache tag, way a) if ((cdbcr[cis] = 1) (cdbcr[cws] = 1)) then (icdbdr) (i-cache tag, way b) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. this instruction is a debugging tool for reading the instruction cache entries for the congruence class specified by ea m ? 1:27 (where m is the number of bits in the cache array tag field). the cache information is read into the instruction cache debug data register (icdbdr), from where it can be read into a gpr using the extended mnemonic mficdbdr . if cdbcr[cis] = 0, the information is an lword of instruction cache data from the addressed line. the lword is specified by ea 28:29 (ea 0: m and ea 30:31 are ignored). if cdbcr[cws] = 0, the data is from the a-way, otherwise from the b-way. if (cdbcr[cis] = 1), the information is a cache tag from the addressed congruence class (ea 0: m and ea 28:31 are ignored). if (cdbcr[cws] = 0), the tag is from the a-way, otherwise from the b-way. instruction cache tag information is placed in the icdbdr as follows. icread ra, rb table 28-20. instruction cache array tag information 0: m ? 1 tag cache tag see table 25-1, ? cache array size by core, ? on page 25-1 for information on the size of this variable-length field. m :24 reserved the size of this field depends on the size of the tag field. 25 lk cache line lock 0 unlocked 1 locked 26 reserved 27 v cache line valid 0not valid 1valid 28:30 reserved 31 lru least recently used (lru) 0 a-way lru 1 b-way lru 31 0 31 ra 998 16 11 6 21 rb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-70 ? 2000 plx technology, inc. all rights reserved. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered icdbdr invalid instruction forms reserved fields programming note execution of this instruction is privileged. the instruction pipeline does not automatically wait for data from icread to arrive at the icdbdr before attempting to use the contents of the icdbdr. therefore, insert an isync instruction between icread and mficdbdr . icread r5,r6# read cache information isync # ensure completion of icread mficdbdr r7# move information to gpr instruction cache operations use msr[dr], not msr[ir], to determine translation of their operands. when data translation is disabled, cacheability for the ea of the operand of instruction cache operations is determined by the iccr, not the dccr. exceptions instruction storage exceptions and instruction-side tlb miss exceptions are associated with instruction fetching , not with instruction execution. exceptions that occur during the execution of instruction cache operations cause data-side exceptions (data storage exceptions and data tlb miss exceptions). the execution of an icread instruction can cause a data tlb miss exception, at the specified ea, regardless of the non-specific intent of that ea. this instruction is considered a ? load ? with respect to protection exceptions, but cannot cause a data storage exception. this instruction is considered a ? load ? with respect to data address compare (dac) debug exceptions, but does not cause dac debug events. architecture note programs using this instruction are not portable to powerpc implementations that do not implement the ibm powerpc embedded environment. section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-71 section 28 ? cpu instr set isync instruction synchronize the isync instruction is a context synchronizing instruction. the isync instruction provides an ordering function for the effects of all instructions executed by the processor. executing isync insures that all instructions preceding the isync instruction have completed before the isync instruction completes, except that storage accesses caused by those instructions need not have completed. no subsequent instructions are initiated by the processor until after the isync instruction completes. finally, execution of isync causes the processor to discard any prefetched instructions, with the effect that subsequent instructions are fetched and executed in the context established by the instructions preceding the isync instruction. the isync instruction has no effect on caches. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields programming note see the discussion of context synchronizing instructions in section 24.9.1, ? context synchronization, ? on page 24-29. the following code example illustrates the necessary steps for self-modifying code. this example assumes that addr1 is both data and instruction cacheable. stw regn, addr1 # the data in regn is to become an instruction at addr1 dcbst addr1 # forces data from the data cache to memory sync # wait until the data actually reaches the memory icbi addr1 # the previous value at addr1 might already be in the instruction cache; invalidate in the cache isync # the previous value at addr1 might already have been pre-fetched into the queue; invalidate the queue so that the instruction must be re-fetched architecture note this instruction is part of the powerpc virtual environment architecture. isync 19 0 31 150 6 21 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-72 ? 2000 plx technology, inc. all rights reserved. lbz load byte and zero ea (ra|0) + exts(d) (rt) 24 0|| ms(ea,1) an effective address (ea) is formed by adding a displacement to a base address. the displacement is obtained by sign-extending the 16-bit d field to 32 bits. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the byte at the ea is extended to 32 bits by concatenating 24 0-bits to its left. the result is placed into register rt. registers altered rt architecture note this instruction is part of the powerpc user instruction set architecture. lbz rt, d(ra) 34 0 31 rt ra d 16 11 6 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-73 section 28 ? cpu instr set lbzu load byte and zero with update ea (ra|0) + exts(d) (ra) ea (rt) 24 0|| ms(ea,1) an effective address (ea) is formed by adding a displacement to a base address. the displacement is obtained by sign-extending the 16-bit d field to 32 bits. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the ea is placed into register ra. the byte at the ea is extended to 32 bits by concatenating 24 0-bits to its left. the result is placed into register rt. registers altered ra rt invalid instruction forms ra=rt ra=0 architecture note this instruction is part of the powerpc user instruction set architecture. lbzu rt, d(ra) 35 0 31 rt ra d 16 11 6 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-74 ? 2000 plx technology, inc. all rights reserved. lbzux load byte and zero with update indexed ea (ra|0) + (rb) (ra) ea (rt) 24 0 || ms(ea,1) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the ea is placed into register ra. the byte at the ea is extended to 32 bits by concatenating 24 0-bits to its left. the result is placed into register rt. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered ra rt invalid instruction forms reserved fields ra=rt ra=0 architecture note this instruction is part of the powerpc user instruction set architecture. lbzux rt, ra, rb 31 0 31 rt ra 119 16 11 6 21 rb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-75 section 28 ? cpu instr set lbzx load byte and zero indexed ea (ra|0) + (rb) (rt) 24 0 || ms(ea,1) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the byte at the ea is extended to 32 bits by concatenating 24 0-bits to its left. the result is placed into register rt. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered rt invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. lbzx rt,ra, rb 31 0 31 rt ra 87 16 11 6 21 rb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-76 ? 2000 plx technology, inc. all rights reserved. lha load word algebraic ea (ra|0) + exts(d) (rt) exts(ms(ea,2)) an effective address (ea) is formed by adding a displacement to a base address. the displacement is obtained by sign-extending the 16-bit d field to 32 bits. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the word at the ea is sign-extended to 32 bits and placed into register rt. registers altered rt exceptions an alignment exception occurs if msr[le] = 1 and the ea is not word-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. lha rt, d(ra) 42 0 31 rt ra d 16 11 6 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-77 section 28 ? cpu instr set lhau load word algebraic with update ea (ra|0) + exts(d) (ra) ea (rt) exts(ms(ea,2)) an effective address (ea) is formed by adding a displacement to a base address. the displacement is obtained by sign-extending the 16-bit d field to 32 bits. the base address is 0 when the ra field is 0 and is the contents of register ra otherwise. the ea is placed into register ra. the word at the ea is sign-extended to 32 bits and placed into register rt. registers altered ra rt invalid instruction forms ra = rt ra = 0 exceptions an alignment exception occurs if msr[le] = 1 and the ea is not word-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. lhau rt, d(ra) 43 0 31 rt ra d 16 11 6 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-78 ? 2000 plx technology, inc. all rights reserved. lhaux load word algebraic with update indexed ea (ra|0) + (rb) (ra) ea (rt) exts(ms(ea,2)) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the ea is placed into register ra. the word at the ea is sign-extended to 32 bits and placed into register rt. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered ra rt invalid instruction forms reserved fields ra = rt ra = 0 exceptions an alignment exception occurs if msr[le] = 1 and the ea is not word-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. lhaux rt, ra, rb 31 0 31 rt ra 375 16 11 6 21 rb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-79 section 28 ? cpu instr set lhax load word algebraic indexed ea (ra|0) + (rb) (rt) exts(ms(ea,2)) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the word at the ea is sign-extended to 32 bits and placed into register rt. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered rt invalid instruction forms reserved fields exceptions an alignment exception occurs if msr[le] = 1 and the ea is not word-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. lhax rt, ra, rb 31 0 31 rt ra 343 16 11 6 21 rb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-80 ? 2000 plx technology, inc. all rights reserved. lhbrx load word byte-reverse indexed ea (ra|0) + (rb) (rt) 16 0 || ms(ea +1,1) || ms(ea,1) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the word at the ea is byte-reversed. the resulting word is extended to 32 bits by concatenating 16 0-bits to its left. the result is placed into register rt. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered rt invalid instruction forms reserved fields exceptions an alignment exception occurs if msr[le] = 1 and the ea is not word-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. lhbrx rt, ra, rb 31 0 31 rt ra 790 16 11 6 21 rb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-81 section 28 ? cpu instr set lhz load word and zero ea (ra|0) + exts(d) (rt) 16 0|| ms(ea,2) an effective address (ea) is formed by adding a displacement to a base address. the displacement is obtained by sign-extending the 16-bit d field to 32 bits. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the word at the ea is extended to 32 bits by concatenating 16 0-bits to its left. the result is placed into register rt. registers altered rt exceptions an alignment exception occurs if msr[le] = 1 and the ea is not word-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. lhz rt, d(ra) 40 0 31 rt ra d 16 11 6 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-82 ? 2000 plx technology, inc. all rights reserved. lhzu load word and zero with update ea (ra|0) + exts(d) (ra) ea (rt) 16 0 || ms(ea,2) an effective address (ea) is formed by adding a displacement to a base address. the displacement is obtained by sign-extending the 16-bit d field to 32 bits. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the ea is placed into register ra. the word at the ea is extended to 32 bits by concatenating 16 0-bits to its left. the result is placed into register rt. registers altered ra rt invalid instruction forms ra = rt ra = 0 exceptions an alignment exception occurs if msr[le] = 1 and the ea is not word-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. lhzu rt, d(ra) 41 0 31 rt ra d 16 11 6 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-83 section 28 ? cpu instr set lhzux load word and zero with update indexed ea (ra|0) + (rb) (ra) ea (rt) 16 0 || ms(ea,2) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the ea is placed into register ra. the word at the ea is extended to 32 bits by concatenating 16 0-bits to its left. the result is placed into register rt. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered ra rt invalid instruction forms reserved fields ra = rt ra = 0 exceptions an alignment exception occurs if msr[le] = 1 and the ea is not word-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. lhzux rt, ra, rb 31 0 31 rt ra 311 16 11 6 21 rb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-84 ? 2000 plx technology, inc. all rights reserved. lhzx load word and zero indexed ea (ra|0) + (rb) (rt) 16 0 || ms(ea,2) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the word at the ea is extended to 32 bits by concatenating 16 0-bits to its left. the result is placed into register rt. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered rt invalid instruction forms reserved fields exceptions an alignment exception occurs if msr[le] = 1 and the ea is not word-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. lhzx rt, ra, rb 31 0 31 rt ra 279 16 11 6 21 rb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-85 section 28 ? cpu instr set lmw load multiple lword ea (ra|0) + exts(d) r rt do while r 31 if ((r ra) (r = 31)) then (gpr(r)) ms(ea,4) r r+1 ea ea + 4 an effective address (ea) is formed by adding a displacement to a base address. the displacement is obtained by sign-extending the 16-bit d field in the instruction to 32 bits. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. a series of consecutive words starting at the ea are loaded into a set of consecutive gprs, starting with register rt and continuing to and including gpr(31). register ra is not altered by this instruction (unless ra is gpr(31), which is an invalid form of this instruction). the lword which would have been placed into register ra is discarded. registers altered rt through gpr(31). invalid instruction forms ra is in the range of registers to be loaded, including the case ra = rt = 0. exceptions if msr[le] = 1, an alignment exception occurs. architecture note this instruction is part of the powerpc user instruction set architecture. lmw rt, d(ra) 46 0 31 rt ra d 16 11 6 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-86 ? 2000 plx technology, inc. all rights reserved. lswi load string lword immediate ea (ra|0) if nb = 0 then cnt 32 else cnt nb n cnt r final ((rt + ceil(cnt/4) ? 1) % 32) r rt ? 1 i 0 do while n > 0 if i = 0 then r r+1 if r = 32 then r 0 if ((r ra) (r = r final )) then (gpr(r)) 0 if ((r ra) (r = r final )) then (gpr(r) i:i+7 ) ms(ea,1) i i+8 if i = 32 then i 0 ea ea + 1 n n ? 1 an effective address (ea) is determined by the ra field. if the ra field contains 0, the ea is 0. otherwise, the ea is the contents of register ra. the nb field specifies the byte count cnt. if the nb field contains 0, the byte count is cnt = 32. otherwise, the byte count is cnt = nb. a series of cnt consecutive bytes in main storage, starting at the ea, are loaded into ceil(cnt/4) consecutive gprs, four bytes per gpr, until the byte count is exhausted. bytes are loaded into gprs; the byte at the lowest address is loaded into the most significant byte. bits to the right of the last byte loaded into the last gpr are set to 0. the set of loaded gprs starts at register rt, continues consecutively through gpr(31), wraps to register 0, loading until the byte count is exhausted, which occurs in register r final . register ra is not altered (unless ra = r final , an invalid form of this instruction). bytes which would have been loaded into register ra are discarded. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. lswi rt, ra, nb 31 0 31 rt ra 597 16 11 6 21 nb this instruction is not part of the powerpc architecture section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-87 section 28 ? cpu instr set registers altered rt and subsequent gprs as described above. invalid instruction forms reserved fields ra is in the range of registers to be loaded ra = rt = 0 exceptions if msr[le] = 1, an alignment exception occurs. architecture note this instruction is part of the powerpc user instruction set architecture. this instruction is not part of the powerpc architecture section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-88 ? 2000 plx technology, inc. all rights reserved. lswx load string lword indexed ea (ra|0) + (rb) cnt xer[tbc] n cnt r final ((rt + ceil(cnt/4) ? 1) % 32) r rt ? 1 i 0 do while n > 0 if i = 0 then r r+1 if r = 32 then r 0 if (((r ra) (r rb)) (r = r final )) then (gpr(r)) 0 if (((r ra) (r rb)) (r = r final )) then (gpr(r) i:i+7 ) ms(ea,1) i i+8 if i = 32 then i 0 ea ea + 1 n n ? 1 an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. a byte count cnt is obtained from xer[tbc]. a series of cnt consecutive bytes in main storage, starting at the ea, are loaded into ceil(cnt/4) consecutive gprs, four bytes per gpr, until the byte count is exhausted. bytes are loaded into gprs; the byte having the lowest address is loaded into the most significant byte. bits to the right of the last byte loaded in the last gpr used are set to 0. the set of consecutive gprs loaded starts at register rt, continues through gpr(31), and wraps to register 0, loading until the byte count is exhausted, which occurs in register r final . register ra is not altered (unless ra = r final , which is an invalid form of this instruction). register rb is not altered (unless rb = r final , which is an invalid form of this instruction). bytes which would have been loaded into registers ra or rb are discarded. if xer[tbc] is 0, the byte count is 0 and the contents of register rt are undefined. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. lswx rt, ra, rb 31 0 31 rt ra 533 16 11 6 21 rb this instruction is not part of the powerpc architecture section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-89 section 28 ? cpu instr set registers altered rt and subsequent gprs as described above. invalid instruction forms reserved fields ra or rb is in the range of registers to be loaded. ra = rt = 0 programming note if xer[tbc] = 0, the contents of register rt are unchanged and lswx is treated as a no-op. the powerpc architecture states that, if xer[tbc] = 0 and if the ea is such that a precise data exception would normally occur (if not for the zero length), lswx is treated as a no-op and the precise exception does not occur. data storage exceptions and alignment exceptions are examples of precise data exceptions. however, the powerpc architecture makes no statement regarding imprecise exceptions related to lswx with xer[tbc] = 0. the iop 480 cpu generates an imprecise exception (machine check) on this instruction when all of the following conditions are true: the instruction passes all protection bounds checking the address is cacheable the address is passed to the data cache the address misses in the data cache (resulting in a line fill request) the address encounters some form of bus error exceptions if msr[le] = 1, an alignment exception occurs. architecture note this instruction is part of the powerpc user instruction set architecture. this instruction is not part of the powerpc architecture section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-90 ? 2000 plx technology, inc. all rights reserved. lwarx load lword and reserve indexed ea (ra|0) + (rb) reserve 1 (rt) ms(ea,4) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the lword at the ea is placed into register rt. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. execution of the lwarx instruction sets the reservation bit. registers altered rt invalid instruction forms reserved fields programming note lwarx and the stwcx. instruction should paired in a loop, as shown in the following example, to create the effect of an atomic operation to a memory area used as a semaphore between asynchronous processes. only lwarx can set the reservation bit to 1. stwcx. sets the reservation bit to 0 upon its completion, whether or not stwcx. sent (rs) to memory. cr[cr0] eq must be examined to determine whether (rs) was sent to memory. loop: lwarx # read the semaphore from memory; set reservation ? alter ? # change the semaphore bits in register as required stwcx. # attempt to store semaphore; reset reservation bne loop# an asynchronous process has intervened; try again if the asynchronous process in the code example had paired lwarx with a store other than stwcx. , the reservation bit would not have been cleared in the asynchronous process, and the code example would have overwritten the semaphore. exceptions an alignment exception occurs if the ea is not lword-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. lwarx rt, ra, rb 31 0 31 rt ra 20 16 11 6 21 rb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-91 section 28 ? cpu instr set lwbrx load lword byte-reverse indexed ea (ra|0) + (rb) (rt) ms(ea+3,1) || ms(ea+2,1) || ms(ea+1,1) || ms(ea,1) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the lword at the ea is byte-reversed: the least significant byte becomes the most significant byte, the next least significant byte becomes the next most significant byte, and so on. the resulting lword is placed into register rt. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered rt invalid instruction forms reserved fields exceptions an alignment exception occurs if msr[le] = 1 and the ea is not lword-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. lwbrx rt, ra, rb 31 0 31 rt ra 534 16 11 6 21 rb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-92 ? 2000 plx technology, inc. all rights reserved. lwz load lword and zero ea (ra|0) + exts(d) (rt) ms(ea,4) an effective address (ea) is formed by adding a displacement to a base address. the displacement is obtained by sign-extending the 16-bit d field to 32 bits. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the lword at the ea is placed into register rt. registers altered rt exceptions an alignment exception occurs if msr[le] = 1 and the ea is not lword-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. lwz rt, d(ra) 32 0 31 rt ra d 16 11 6 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-93 section 28 ? cpu instr set lwzu load lword and zero with update ea (ra|0) + exts(d) (ra) ea (rt) ms(ea,4) an effective address (ea) is formed by adding a displacement to a base address. the displacement is obtained by sign-extending the 16-bit d field to 32 bits. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the ea is placed into register ra. the lword at the ea is placed into register rt. registers altered ra rt invalid instruction forms ra = rt ra = 0 exceptions an alignment exception occurs if msr[le] = 1 and the ea is not lword-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. lwzu rt, d(ra) 33 0 31 rt ra d 16 11 6 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-94 ? 2000 plx technology, inc. all rights reserved. lwzux load lword and zero with update indexed ea (ra|0) + (rb) (ra) ea (rt) ms(ea,4) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the ea is placed into register ra. the lword at the ea is placed into register rt. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered ra rt invalid instruction forms reserved fields ra = rt ra = 0 exceptions an alignment exception occurs if msr[le] = 1 and the ea is not lword-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. lwzux rt, ra, rb 31 0 31 rt ra 55 16 11 6 21 rb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-95 section 28 ? cpu instr set lwzx load lword and zero indexed ea (ra|0) + (rb) (rt) ms(ea,4) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the lword at the ea is placed into register rt. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered rt invalid instruction forms reserved fields exceptions an alignment exception occurs if msr[le] = 1 and the ea is not lword-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. lwzx rt, ra, rb 31 0 31 rt ra 23 16 11 6 21 rb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-96 ? 2000 plx technology, inc. all rights reserved. mcrf move condition register field m bfa n bf (cr[crn]) (cr[crm]) the contents of the cr field specified by the bfa field are placed into the cr field specified by the bf field. registers altered cr[crn] where n is specified by the bf field. invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. mcrf bf, bfa 19 0 0 14 11 6 21 bf 9 31 bfa section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-97 section 28 ? cpu instr set mcrxr move to condition register from xer n bf (cr[crn]) xer 0:3 xer 0:3 4 0 the contents of xer 0:3 are placed into the cr field specified by the bf field. xer 0:3 are then set to 0. this transfer is positional, by bit number, so the mnemonics associated with each bit are changed. see the following table for clarification. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered cr[crn] where n is specified by the bf field. xer[so, ov, ca] invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. mcrxr bf bit xer usage cr usage 0solt 1ovgt 2caeq 3 reserved so 31 0 512 6 21 bf 9 31 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-98 ? 2000 plx technology, inc. all rights reserved. mfcr move from condition register (rt) (cr) the contents of the cr are placed into register rt. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered rt invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. mfcr rt 31 0 19 6 21 rt 11 31 this instruction is not part of the powerpc architecture section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-99 section 28 ? cpu instr set mfdcr move from device control register dcrn dcrf 5:9 || dcrf 0:4 (rt) (dcr(dcrn)) the contents of the dcr specified by the dcrf field are placed into register rt. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered rt invalid instruction forms reserved fields invalid dcrf values programming note execution of this instruction is privileged. the dcr number (dcrn) specified in the assembler language coding of the mfdcr instruction refers to a dcr number. the assembler handles the unusual register number encoding to generate the dcrf field. architecture note programs using this instruction are not portable to powerpc implementations that do not implement the ibm powerpc embedded environment. mfdcr rt, dcrn 31 0 31 rt 323 11 6 dcrf 21 this instruction is not part of the powerpc architecture section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-100 ? 2000 plx technology, inc. all rights reserved. mfmsr move from machine state register (rt) (msr) the contents of the msr are placed into register rt. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered rt invalid instruction forms reserved fields programming note execution of this instruction is privileged. architecture note this instruction is part of the powerpc operating environment architecture. mfmsr rt 31 0 31 rt 83 11 6 21 this instruction is not part of the powerpc architecture section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-101 section 28 ? cpu instr set mfspr move from special purpose register sprn sprf 5:9 || sprf 0:4 (rt) (spr(sprn)) the contents of the spr specified by the sprf field are placed into register rt. see table 29-2, ? special purpose registers, ? on page 29-2 for a listing of spr mnemonics and corresponding sprn and sprf values. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered rt invalid instruction forms reserved fields invalid sprf values programming note execution of this instruction is privileged if instruction bit 11 contains 1. see section 24.8.3, ? privileged sprs, ? on page 24-28, for more information. the spr number (sprn) specified in the assembler language coding of the mfspr instruction refers to an spr number (see table 29-2, ? special purpose registers, ? on page 29-2 for a list of sprn values). the assembler handles the unusual register number encoding to generate the sprf field. also, see section 24.8.3, ? privileged sprs, ? on page 24-28 for information about privileged sprs. architecture note this instruction is part of the powerpc user instruction set architecture. mfspr rt, sprn 31 0 31 rt 339 11 6 sprf 21 this instruction is not part of the powerpc architecture section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-102 ? 2000 plx technology, inc. all rights reserved. table 28-21. extended mnemonics for mfspr mnemonic operands function other registers changed mfcdbcr mfctr mfdac1 mfdbcr mfdbsr mfdbsrs mfdccr mfdcwr mfdear mfesr mfevpr mfiac1 mficcr mficdbdr mflr mfpit mfpvr mfsgr mfsler mfsprg0 mfsprg1 mfsprg2 mfsprg3 mfsrr0 mfsrr1 mfsrr2 mfsrr3 mftbhi mftbhu mftblo mftblu mftcr mftsr mfxer rt move from special purpose register sprn. extended mnemonic for mfspr rt,sprn see table 29-2, ? special purpose registers, ? on page 29-2 for a list of valid sprn values. this instruction is not part of the powerpc architecture section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-103 section 28 ? cpu instr set mtcrf move to condition register fields mask 4 (fxm 0 ) || 4 (fxm 1 ) || ... || 4 (fxm 6 ) || 4 (fxm 7 ) (cr) ((rs) mask) ((cr) ? mask) some or all of the contents of register rs are placed into the cr as specified by the fxm field. each bit in the fxm field controls the copying of 4 bits in register rs into the corresponding bits in the cr. the correspondence between the bits in the fxm field and the bit copying operation is shown in the following table: if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered cr invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. mtcrf fxm, rs fxm bit number bits controlled 00:3 14:7 28:11 3 12:15 4 16:19 5 20:23 6 24:27 7 28:31 table 28-22. extended mnemonics for mtcrf mnemonic operands function other registers changed mtcr rs move to condition register. extended mnemonic for mtcrf 0xff,rs 31 0 31 rs 144 20 11 6 21 12 fxm this instruction is not part of the powerpc architecture section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-104 ? 2000 plx technology, inc. all rights reserved. mtdcr move to device control register dcrn dcrf 5:9 || dcrf 0:4 (dcr(dcrn)) (rs) the contents of register rs are placed into the dcr specified by the dcrf field. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered dcr(dcrn) invalid instruction forms reserved fields invalid dcrf values programming note execution of this instruction is privileged. the dcr number (dcrn) specified in the assembler language coding of the mtdcr instruction refers to a dcr number. the assembler handles the unusual register number encoding to generate the dcrf field. architecture note programs using this instruction are not portable to powerpc implementations that do not implement the ibm powerpc embedded environment. mtdcr dcrn, rs 31 0 31 rs 451 11 6 dcrf 21 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-105 section 28 ? cpu instr set mtmsr move to machine state register (msr) (rs) the contents of register rs are placed into the msr. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered msr invalid instruction forms reserved fields programming note the mtmsr instruction is privileged and execution synchronizing. architecture note this instruction is part of the powerpc operating environment architecture. mtmsr rs 31 0 31 rs 146 11 6 21 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-106 ? 2000 plx technology, inc. all rights reserved. mtspr move to special purpose register sprn sprf 5:9 || sprf 0:4 (spr(sprn)) (rs) the contents of register rs are placed into register rt. see table 29-2, ? special purpose registers, ? on page 29-2 for a listing of spr mnemonics and corresponding sprn and sprf values. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered spr(sprn) invalid instruction forms reserved fields invalid sprf values programming note execution of this instruction is privileged if instruction bit 11 is set to 1. see section 24.8.3, ? privileged sprs, ? on page 24-28, for more information. the spr number (sprn) specified in the assembler language coding of the mtspr instruction refers to an spr number (see table 29-2, ? special purpose registers, ? on page 29-2 for a list of sprn values). the assembler handles the unusual register number encoding to generate the sprf field. also, see section 24.8.3, ? privileged sprs, ? on page 24-28 for information about privileged sprs. architecture note this instruction is part of the powerpc user instruction set architecture. mtspr sprn, rs 31 0 31 rs 467 11 6 sprf 21 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-107 section 28 ? cpu instr set table 28-23. extended mnemonics for mtspr mnemonic operands function other registers changed mtcdbcr mtctr mtdac1 mtdbcr mtdbsr mtdccr mtdcwr mtdear mtesr mtevpr mtiac1 mticcr mticdbdr mtlr mtpit mtpvr mtsgr mtsler mttsprg0 mtsprg1 mtsprg2 mtsprg3 mtsrr0 mtsrr1 mtsrr2 mtsrr3 mttbhi mttblo mttcr mttsr mtxer rs move to special purpose register sprn. extended mnemonic for mtspr sprn,rs see table 29-2, ? special purpose registers, ? on page 29-2 for a list of valid sprn values. section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-108 ? 2000 plx technology, inc. all rights reserved. mulhw multiply high lword prod 0:63 (ra) (rb) (signed) (rt) prod 0:31 the 64-bit signed product of registers ra and rb is formed. the most significant 32 bits of the result is placed into register rt. registers altered rt cr[cr0] lt, gt, eq, so if rc contains 1 programming note the most significant 32 bits of the product, unlike the least significant 32 bits, may differ depending on whether the registers ra and rb are interpreted as signed or unsigned quantities. the mulhw instruction generates the correct result when these operands are interpreted as signed quantities. the mulhwu instruction generates the correct result when these operands are interpreted as unsigned quantities. architecture note this instruction is part of the powerpc user instruction set architecture. mulhw rt, ra, rb rc=0 mulhw. rt, ra, rb rc=1 31 0 31 rt ra 75 16 11 6 rb rc 21 22 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-109 section 28 ? cpu instr set mulhwu multiply high lword unsigned prod 0:63 (ra) (rb) (unsigned) (rt) prod 0:31 the 64-bit unsigned product of registers ra and rb is formed. the most significant 32 bits of the result are placed into register rt. registers altered rt cr[cr0] lt, gt, eq, so if rc contains 1 programming note the most significant 32 bits of the product, unlike the least significant 32 bits, may differ depending on whether the registers ra and rb are interpreted as signed or unsigned quantities. the mulhw instruction generates the correct result when these operands are interpreted as signed quantities. the mulhwu instruction generates the correct result when these operands are interpreted as unsigned quantities. architecture note this instruction is part of the powerpc user instruction set architecture. mulhwu rt, ra, rb rc=0 mulhwu. rt, ra, rb rc=1 31 0 31 rt ra 11 16 11 6 rb rc 21 22 20 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-110 ? 2000 plx technology, inc. all rights reserved. mulli multiply low immediate prod 0:47 (ra) exts(im) (signed) (rt) prod 16:47 the 48-bit product of register ra and the sign-extended im field is formed. both register ra and the im field are interpreted as signed quantities. the least significant 32 bits of the product are placed into register rt. registers altered rt programming note the least significant 32 bits of the product are correct, regardless of whether register ra and field im are interpreted as signed or unsigned numbers. architecture note this instruction is part of the powerpc user instruction set architecture. mulli rt, ra, im 7 0 31 rt ra im 16 11 6 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-111 section 28 ? cpu instr set mullw multiply low lword prod 0:63 (ra) (rb) (signed) (rt) prod 32:63 the 64-bit signed product of register ra and register rb is formed. the least significant 32 bits of the result is placed into register rt. if the signed product cannot be represented in 32 bits and oe=1, xer[so, ov] are set to 1. registers altered rt cr[cr0] lt, gt, eq, so if rc contains 1 xer[so, ov] if oe=1 programming note the least significant 32 bits of the product are correct, regardless of whether register ra and register rb are interpreted as signed or unsigned numbers. the overflow indication is correct only if the operands are regarded as signed numbers. architecture note this instruction is part of the powerpc user instruction set architecture. mullw rt, ra, rb oe=0, rc=0 mullw. rt, ra, rb oe=0, rc=1 mullwo rt, ra, rb oe=1, rc=0 mullwo. rt, ra, rb oe=1, rc=1 31 0 31 rt ra 235 16 11 6 rb rc 21 22 oe section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-112 ? 2000 plx technology, inc. all rights reserved. nand nand (ra) ? ((rs) (rb)) the contents of register rs is anded with the contents of register rb; the ones complement of the result is placed into register ra. registers altered ra cr[cr0] lt, gt, eq, so if rc contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. nand ra, rs, rb rc=0 nand. ra, rs, rb rc=1 31 0 31 rs ra 476 16 11 6 rb rc 21 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-113 section 28 ? cpu instr set neg negate (rt) ? (ra) + 1 the twos complement of the contents of register ra are placed into register rt. registers altered rt cr[cr0] lt, gt, eq, so if rc contains 1 xer[ca, so, ov] if oe=1 invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. neg rt, ra oe=0, rc=0 neg. rt, ra oe=0, rc=1 nego rt, ra oe=1, rc=0 nego. rt, ra oe=1, rc=1 31 0 31 rt ra 104 16 11 6 rc 21 22 oe section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-114 ? 2000 plx technology, inc. all rights reserved. nor nor (ra) ? ((rs) (rb)) the contents of register rs is ored with the contents of register rb; the ones complement of the result is placed into register ra. registers altered ra cr[cr0] lt, gt, eq, so if rc contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. nor ra, rs, rb rc=0 nor. ra, rs, rb rc=1 table 28-24. extended mnemonics for nor, nor. mnemonic operands function other registers changed not ra, rs complement register. (ra) ? (rs) extended mnemonic for nor ra,rs,rs not. extended mnemonic for nor. ra,rs,rs cr[cr0] 31 0 31 rs ra 124 16 11 6 rc 21 rb section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-115 section 28 ? cpu instr set or or (ra) (rs) (rb) the contents of register rs is ored with the contents of register rb; the result is placed into register ra. registers altered ra cr[cr0] lt, gt, eq, so if rc contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. or ra, rs, rb rc=0 or. ra, rs, rb rc=1 table 28-25. extended mnemonics for or, or. mnemonic operands function other registers changed mr rt, rs move register. (rt) (rs) extended mnemonic for or rt,rs,rs mr. extended mnemonic for or. rt,rs,rs cr[cr0] 31 0 31 rs ra 444 16 11 6 rb rc 21 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-116 ? 2000 plx technology, inc. all rights reserved. orc or with complement (ra) (rs) ? (rb) the contents of register rs is ored with the ones complement of the contents of register rb; the result is placed into register ra. registers altered ra cr[cr0] lt, gt, eq, so if rc contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. orc ra, rs, rb rc=0 orc. ra, rs, rb rc=1 31 0 31 rs ra 412 16 11 6 rb rc 21 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-117 section 28 ? cpu instr set ori or immediate (ra) (rs) ( 16 0||im) the im field is extended to 32 bits by concatenating 16 0-bits on the left. register rs is ored with the extended im field; the result is placed into register ra. registers altered ra architecture note this instruction is part of the powerpc user instruction set architecture. ori ra, rs, im table 28-26. extended mnemonics for ori mnemonic operands function other registers changed nop preferred no-op; triggers optimizations based on no-ops. extended mnemonic for ori 0,0,0 24 0 31 rs ra im 16 11 6 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-118 ? 2000 plx technology, inc. all rights reserved. oris or immediate shifted (ra) (rs) (im || 16 0) the im field is extended to 32 bits by concatenating 16 0-bits on the right. register rs is ored with the extended im field and the result is placed into register ra. registers altered ra architecture note this instruction is part of the powerpc user instruction set architecture. oris ra, rs, im 25 0 31 rs ra im 16 11 6 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-119 section 28 ? cpu instr set rfci return from critical interrupt (pc) (srr2) (msr ) (srr3) the program counter (pc) is restored with the contents of srr2 and the msr is restored with the contents of srr3. instruction execution returns to the address contained in the pc. registers altered msr programming note execution of this instruction is privileged and context-synchronizing. architecture note programs using this instruction are not portable to powerpc implementations that do not implement the ibm powerpc embedded environment. rfci 19 0 31 51 6 21 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-120 ? 2000 plx technology, inc. all rights reserved. rfi return from interrupt (pc) (srr0) (msr) (srr1) the program counter (pc) is restored with the contents of srr0 and the msr is restored with the contents of srr1. instruction execution returns to the address contained in the pc. registers altered msr invalid instruction forms reserved fields programming note execution of this instruction is privileged and context-synchronizing. architecture note this instruction is part of the powerpc operating environment architecture. rfi 19 0 31 50 6 21 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-121 section 28 ? cpu instr set rlwimi rotate left lword immediate then mask insert r rotl((rs), sh) m mask(mb, me) (ra) (r m) ((ra) ? m) the contents of register rs are rotated left by the number of bit positions specified in the sh field. a mask is generated, having 1-bits starting at the bit position specified in the mb field and ending in the bit position specified by the me field, with 0-bits elsewhere. if the starting point of the mask is at a higher bit position than the ending point, the 1-bits portion of the mask wraps from the highest bit position back around to the lowest. the rotated data is inserted into register ra, in positions corresponding to the bit positions in the mask that contain a 1-bit. registers altered ra cr[cr0] lt, gt, eq, so if rc contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. rlwimi ra, rs, sh, mb, me rc=0 rlwimi. ra, rs, sh, mb, me rc=1 table 28-27. extended mnemonics for rlwimi, rlwimi. mnemonic operands function other registers changed inslwi ra, rs, n, b insert from left immediate. (n > 0) (ra) b:b+n ? 1 (rs) 0:n ? 1 extended mnemonic for rlwimi ra,rs,32 ? b,b,b+n ? 1 inslwi. extended mnemonic for rlwimi. ra,rs,32 ? b,b,b+n ? 1 cr[cr0] insrwi ra, rs, n, b insert from right immediate. (n > 0) (ra) b:b+n ? 1 (rs) 32 ? n:31 extended mnemonic for rlwimi ra,rs,32 ? b ? n,b,b+n ? 1 insrwi. extended mnemonic for rlwimi. ra,rs,32 ? b ? n,b,b+n ? 1 cr[cr0] 20 0 31 rs ra 16 11 6 sh 21 mb me 26 rc section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-122 ? 2000 plx technology, inc. all rights reserved. rlwinm rotate left lword immediate then and with mask r rotl((rs), sh) m mask(mb, me) (ra) r m the contents of register rs are rotated left by the number of bit positions specified in the sh field. a mask is generated, having 1-bits starting at the bit position specified in the mb field and ending in the bit position specified by the me field with 0-bits elsewhere. if the starting point of the mask is at a higher bit position than the ending point, the 1-bits portion of the mask wraps from the highest bit position back around to the lowest. the rotated data is anded with the generated mask; the result is placed into register ra. registers altered ra cr[cr0] lt, gt, eq, so if rc contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. rlwinm ra, rs, sh, mb, me rc=0 rlwinm. ra, rs, sh, mb, me rc=1 table 28-28. extended mnemonics for rlwinm, rlwinm. mnemonic operands function other registers changed clrlwi ra, rs, n clear left immediate. (n < 32) (ra) 0:n ? 1 n 0 extended mnemonic for rlwinm ra,rs,0,n,31 clrlwi. extended mnemonic for rlwinm. ra,rs,0,n,31 cr[cr0] clrlslwi ra, rs, b, n clear left and shift left immediate. (n b < 32) (ra) b ? n:31 ? n (rs) b:31 (ra) 32 ? n:31 n 0 (ra) 0:b ? n ? 1 b ? n 0 extended mnemonic for rlwinm ra,rs,n,b ? n,31 ? n clrlslwi. extended mnemonic for rlwinm. ra,rs,n,b ? n,31 ? n cr[cr0] clrrwi ra, rs, n clear right immediate. (n < 32) (ra) 32 ? n:31 n 0 extended mnemonic for rlwinm ra,rs,0,0,31 ? n clrrwi. extended mnemonic for rlwinm. ra,rs,0,0,31 ? n cr[cr0] 21 0 31 rs ra 16 11 6 sh 21 mb me 26 rc section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-123 section 28 ? cpu instr set extlwi ra, rs, n, b extract and left justify immediate. (n > 0) (ra) 0:n ? 1 (rs) b:b+n ? 1 (ra) n:31 32 ? n 0 extended mnemonic for rlwinm ra,rs,b,0,n ? 1 extlwi. extended mnemonic for rlwinm. ra,rs,b,0,n ? 1 cr[cr0] extrwi ra, rs, n, b extract and right justify immediate. (n > 0) (ra) 32 ? n:31 (rs) b:b+n ? 1 (ra) 0:31 ? n 32 ? n 0 extended mnemonic for rlwinm ra,rs,b+n,32 ? n,31 extrwi. extended mnemonic for rlwinm. ra,rs,b+n,32 ? n,31 cr[cr0] rotlwi ra, rs, n rotate left immediate. (ra) rotl((rs), n) extended mnemonic for rlwinm ra,rs,n,0,31 rotlwi. extended mnemonic for rlwinm. ra,rs,n,0,31 cr[cr0] rotrwi ra, rs, n rotate right immediate. (ra) rotl((rs), 32 ? n) extended mnemonic for rlwinm ra,rs,32 ? n,0,31 rotrwi. extended mnemonic for rlwinm. ra,rs,32 ? n,0,31 cr[cr0] slwi ra, rs, n shift left immediate. (n < 32) (ra) 0:31 ? n (rs) n:31 (ra) 32 ? n:31 n 0 extended mnemonic for rlwinm ra,rs,n,0,31 ? n slwi. extended mnemonic for rlwinm. ra,rs,n,0,31 ? n cr[cr0] srwi ra, rs, n shift right immediate. (n < 32) (ra) n:31 (rs) 0:31 ? n (ra) 0:n ? 1 n 0 extended mnemonic for rlwinm ra,rs,32 ? n,n,31 srwi. extended mnemonic for rlwinm. ra,rs,32 ? n,n,31 cr[cr0] table 28-28. extended mnemonics for rlwinm, rlwinm. mnemonic operands function other registers changed section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-124 ? 2000 plx technology, inc. all rights reserved. rlwnm rotate left lword then and with mask r rotl((rs), (rb) 27:31 ) m mask(mb, me) (ra) r m the contents of register rs are rotated left by the number of bit positions specified by the contents of register rb 27:31 . a mask is generated, having 1-bits starting at the bit position specified in the mb field and ending in the bit position specified by the me field with 0-bits elsewhere. if the starting point of the mask is at a higher bit position than the ending point, the ones portion of the mask wraps from the highest bit position back to the lowest. the rotated data is anded with the generated mask and the result is placed into register ra. registers altered ra cr[cr0] lt, gt, eq, so if rc contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. rlwnm ra, rs, rb, mb, me rc=0 rlwnm. ra, rs, rb, mb, me rc=1 table 28-29. extended mnemonics for rlwnm, rlwnm. mnemonic operands function other registers changed rotlw ra, rs, rb rotate left. (ra) rotl((rs), (rb) 27:31 ) extended mnemonic for rlwnm ra,rs,rb,0,31 rotlw. extended mnemonic for rlwnm. ra,rs,rb,0,31 cr[cr0] 23 0 31 rs ra 16 11 6 rb 21 mb me 26 rc section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-125 section 28 ? cpu instr set sc system call (srr1) (msr) (srr0) (pc) pc evpr 0:15 || 0x0c00 (msr[we, ee, pr, dr, ir]) 0 (msr[le]) (msr[ile]) a system call exception is generated. the contents of the msr are copied into srr1 and (4 + address of sc instruction) is placed into srr0. the program counter (pc) is then loaded with the exception vector address. the exception vector address is calculated by concatenating the high word of the exception vector prefix register (evpr) to the left of 0x0c00. the msr[we, ee, pr, dr, ir] bits are set to 0, and msr[ile] is copied to msr[le]. program execution continues at the new address in the pc. the sc instruction is context synchronizing. registers altered srr0 srr1 msr[we, ee, pr, dr, ir, le] invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. sc 17 0 30 1 6 31 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-126 ? 2000 plx technology, inc. all rights reserved. slw shift left lword n (rb) 27:31 r rotl((rs), n) if (rb) 26 =0 then m mask(0, 31 ? n) else m 32 0 (ra) r m the contents of register rs are shifted left by the number of bits specified by the contents of register rb 27:31 . bits shifted left out of the most significant bit are lost, and 0-bits fill vacated bit positions on the right. the result is placed into register ra. if bit 26 of register rb contains a one, register ra is set to zero. registers altered ra cr[cr0] lt, gt, eq, so if rc contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. slw ra, rs, rb rc=0 slw. ra, rs, rb rc=1 31 0 31 rs ra 16 11 6 rb 21 24 rc section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-127 section 28 ? cpu instr set sraw shift right algebraic lword n (rb) 27:31 r rotl((rs), 32 ? n) if (rb) 26 =0 then m mask(n, 31) else m 32 0 s (rs) 0 (ra) (r m) ( 32 s ? m) xer[ca] s ((r ? m) 0) the contents of register rs are shifted right by the number of bits specified the contents of register rb 27:31 . bits shifted out of the least significant bit are lost. register rs 0 is replicated to fill the vacated positions on the left. the result is placed into register ra. if register rs contains a negative number and any 1-bits were shifted out of the least significant bit position, xer[ca] is set to 1; otherwise, it is set to 0. if bit 26 of register rb contains 1, register ra and xer[ca] are set to bit 0 of register rs. registers altered ra xer[ca] cr[cr0] lt, gt, eq, so if rc contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. sraw ra, rs, rb rc=0 sraw. ra, rs, rb rc=1 31 0 31 rs ra 16 11 6 rb 21 792 rc section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-128 ? 2000 plx technology, inc. all rights reserved. srawi shift right algebraic lword immediate n sh r rotl((rs), 32 ? n) m mask(n, 31) s (rs) 0 (ra) (r m) ( 32 s ? m) xer[ca] s ((r ? m) 0) the contents of register rs are shifted right by the number of bits specified in the sh field. bits shifted out of the least significant bit are lost. bit rs 0 is replicated to fill the vacated positions on the left. the result is placed into register ra. if register rs contains a negative number and any 1-bits were shifted out of the least significant bit position, xer[ca] is set to 1; otherwise, it is set to 0. registers altered ra xer[ca] cr[cr0] lt, gt, eq, so if rc contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. srawi ra, rs, sh rc=0 srawi. ra, rs, sh rc=1 31 0 31 rs ra 16 11 6 sh 21 824 rc section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-129 section 28 ? cpu instr set srw shift right lword n (rb) 27:31 r rotl((rs), 32 ? n) if (rb) 26 =0 then m mask(n, 31) else m 32 0 (ra) r m the contents of register rs are shifted right by the number of bits specified the contents of register rb 27:31 . bits shifted right out of the least significant bit are lost, and 0-bits fill the vacated bit positions on the left. the result is placed into register ra. if bit 26 of register rb contains a one, register ra is set to 0. registers altered ra cr[cr0] lt, gt, eq, so if rc contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. srw ra, rs, rb rc=0 srw. ra, rs, rb rc=1 31 0 31 rs ra 16 11 6 rb 21 536 rc section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-130 ? 2000 plx technology, inc. all rights reserved. stb store byte ea (ra|0) + exts(d) ms(ea, 1) (rs) 24:31 an effective address (ea) is formed by adding a displacement to a base address. the displacement is obtained by sign-extending the 16-bit d field to 32 bits. the base address is 0 when the ra field is 0, and is the contents of register ra otherwise. the least significant byte of register rs is stored into the byte at the ea. registers altered none architecture note this instruction is part of the powerpc user instruction set architecture. stb rs, d(ra) 38 0 31 rs ra d 16 11 6 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-131 section 28 ? cpu instr set stbu store byte with update ea (ra|0) + exts(d) ms(ea, 1) (rs) 24:31 (ra) ea an effective address (ea) is formed by adding a displacement to a base address. the displacement is obtained by sign-extending the 16-bit d field to 32 bits. the base address is 0 when the ra field is 0, and is the contents of register ra otherwise. the least significant byte of register rs is stored into the byte at the ea. the ea is placed into register ra. registers altered ra invalid instruction forms ra = 0 architecture note this instruction is part of the powerpc user instruction set architecture. stbu rs, d(ra) 39 0 31 rs ra d 16 11 6 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-132 ? 2000 plx technology, inc. all rights reserved. stbux store byte with update indexed ea (ra|0) + (rb) ms(ea, 1) (rs) 24:31 (ra) ea an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 when the ra field is 0, and is the contents of register ra otherwise. the least significant byte of register rs is stored into the byte at the ea. the ea is placed into register ra. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered ra invalid instruction forms reserved fields ra = 0 architecture note this instruction is part of the powerpc user instruction set architecture. stbux rs, ra, rb 31 0 31 rs ra 16 11 6 rb 21 247 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-133 section 28 ? cpu instr set stbx store byte indexed ea (ra|0) + (rb) ms(ea, 1) (rs) 24:31 an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 when the ra field is 0, and is the contents of register ra otherwise. the least significant byte of register rs is stored into the byte at the ea. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. stbx rs, ra, rb 31 0 31 rs ra 16 11 6 rb 21 215 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-134 ? 2000 plx technology, inc. all rights reserved. sth store word ea (ra|0) + exts(d) ms(ea, 2) (rs) 16:31 an effective address (ea) is formed by adding a displacement to a base address. the displacement is obtained by sign-extending the 16-bit d field to 32 bits. the base address is 0 when the ra field is 0 and is the contents of register ra otherwise. the least significant word of register rs is stored into the word at the ea in main storage. registers altered none exceptions an alignment exception occurs if msr[le] = 1 and the ea is not word-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. sth rs, d(ra) 44 0 31 rs ra d 16 11 6 this instruction is not part of the powerpc architecture section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-135 section 28 ? cpu instr set sthbrx store word byte-reverse indexed ea (ra|0) + (rb) ms(ea, 2) (rs) 24:31 || (rs) 16:23 an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 when the ra field is 0, and is the contents of register ra otherwise. the least significant word of register rs is byte-reversed. the result is stored into the word at the ea. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields exceptions an alignment exception occurs if msr[le] = 1 and the ea is not word-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. sthbrx rs, ra, rb 31 0 31 rs ra 16 11 6 rb 21 918 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-136 ? 2000 plx technology, inc. all rights reserved. sthu store word with update ea (ra|0) + exts(d) ms(ea, 2) (rs) 16:31 (ra) ea an effective address (ea) is formed by adding a displacement to a base address. the displacement is obtained by sign-extending the 16-bit d field to 32 bits. the base address is 0 when the ra field is 0, and is the contents of register ra otherwise. the least significant word of register rs is stored into the word at the ea. the ea is placed into register ra. registers altered ra invalid instruction forms ra = 0 exceptions an alignment exception occurs if msr[le] = 1 and the ea is not word-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. sthu rs, d(ra) 45 0 31 rs ra d 16 11 6 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-137 section 28 ? cpu instr set sthux store word with update indexed ea (ra|0) + (rb) ms(ea, 2) (rs) 16:31 (ra) ea an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 when the ra field is 0, and is the contents of register ra otherwise. the least significant word of register rs is stored into the word at the ea. the ea is placed into register ra. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered ra invalid instruction forms reserved fields ra = 0 exceptions an alignment exception occurs if msr[le] = 1 and the ea is not word-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. sthux rs, ra, rb 31 0 31 rs ra 16 11 6 rb 21 439 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-138 ? 2000 plx technology, inc. all rights reserved. sthx store word indexed ea (ra|0) + (rb) ms(ea, 2) (rs) 16:31 an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 when the ra field is 0, and is the contents of register ra otherwise. the least significant word of register rs is stored into the word at the ea. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields exceptions an alignment exception occurs if msr[le] = 1 and the ea is not word-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. sthx rs, ra, rb 31 0 31 rs ra 16 11 6 rb 21 407 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-139 section 28 ? cpu instr set stmw store multiple lword ea (ra|0) + exts(d) r rs do while r 31 ms(ea, 4) (gpr(r)) r r+1 ea ea + 4 an effective address (ea) is formed by adding a displacement to a base address. the displacement is obtained by sign-extending the 16-bit d field to 32 bits. the base address is 0 when the ra field is 0, and is the contents of register ra otherwise. the contents of a series of consecutive registers, starting with register rs and continuing through gpr(31), are stored into consecutive words starting at the ea. registers altered none exceptions an alignment exception occurs if msr[le] = 1. architecture note this instruction is part of the powerpc user instruction set architecture. stmw rs, d(ra) 47 0 31 rs ra d 16 11 6 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-140 ? 2000 plx technology, inc. all rights reserved. stswi store string lword immediate ea (ra|0) if nb = 0 then n 32 else n nb r rs ? 1 i 0 do while n > 0 if i = 0 then r r+1 if r = 32 then r 0 ms(ea,1) (gpr(r) i:i+7 ) i i+8 if i = 32 then i 0 ea ea + 1 n n ? 1 an effective address (ea) is determined by the ra field. if the ra field contains 0, the ea is 0; otherwise, the ea is the contents of register ra. a byte count is determined by the nb field. if the nb field contains 0, the byte count is 32; otherwise, the byte count is the contents of the nb field. the contents of a series of consecutive gprs (starting with register rs, continuing through gpr(31), wrapping to gpr(0), and continuing to the final byte count) are stored, starting at the ea. the bytes in each gpr are accessed starting with the most significant byte. the byte count determines the number of transferred bytes. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none exceptions an alignment exception occurs if msr[le] = 1. architecture note this instruction is part of the powerpc user instruction set architecture. stswi rs, ra, nb 31 0 31 rs ra 16 11 6 nb 21 725 this instruction is not part of the powerpc architecture section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-141 section 28 ? cpu instr set stswx store string lword indexed ea (ra|0) + (rb) n xer[tbc] r rs ? 1 i 0 do while n > 0 if i = 0 then r r+1 if r = 32 then r 0 ms(ea, 1) (gpr(r) i:i+7 ) i i+8 if i = 32 then i 0 ea ea + 1 n n ? 1 an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 when the ra field is 0, and is the contents of register ra otherwise. a byte count is contained in xer[tbc]. the contents of a series of consecutive gprs (starting with register rs, continuing through gpr(31), wrapping to gpr(0), and continuing to the final byte count) are stored, starting at the ea. the bytes in each gpr are accessed starting with the most significant byte. the byte count determines the number of transferred bytes. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields programming note if xer[tbc] = 0, stswx is treated as a no-op. the powerpc architecture states that, if xer[tbc] = 0 and if the ea is such that a precise data exception would normally occur (if not for the zero length), stswx is treated as a no-op and the precise exception does not occur. data storage exceptions and alignment exceptions are examples of precise data exceptions. stswx rs, ra, rb 31 0 31 rs ra 16 11 6 rb 21 661 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-142 ? 2000 plx technology, inc. all rights reserved. however, the architecture makes no statement regarding imprecise exceptions related to stswx with xer[tbc] = 0. the iop 480 cpu generates an imprecise exception (machine check) on this instruction when all of the following conditions are true: the instruction passes all protection bounds checking the address is cacheable the address is passed to the data cache the address misses in the data cache (resulting in a line fill request) the address encounters some form of bus error (non-configured, for example). exceptions an alignment exception occurs if msr[le] = 1. architecture note this instruction is part of the powerpc user instruction set architecture. section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-143 section 28 ? cpu instr set stw store lword ea (ra|0) + exts(d) ms(ea, 4) (rs) an effective address (ea) is formed by adding a displacement to a base address. the displacement is obtained by sign-extending the 16-bit d field to 32 bits. the base address is 0 when the ra field is 0, and is the contents of register ra otherwise. the contents of register rs are stored at the ea. registers altered none exceptions an alignment exception occurs if msr[le] = 1 and the ea is not lword-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. stw rs, d(ra) 36 0 31 rs ra d 16 11 6 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-144 ? 2000 plx technology, inc. all rights reserved. stwbrx store lword byte-reverse indexed ea (ra|0) + (rb) ms(ea, 4) (rs) 24:31 || (rs) 16:23 || (rs) 8:15 || (rs) 0:7 an ea is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 when the ra field is 0, and is the contents of register ra otherwise. the contents of register rs are byte-reversed: the least significant byte becomes the most significant byte, the next least significant byte becomes the next most significant byte, and so on. the result is stored into the lword at the ea. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none exceptions an alignment exception occurs if msr[le] = 1 and the ea is not lword-aligned. invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. stwbrx rs, ra, rb 31 0 31 rs ra 16 11 6 rb 21 662 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-145 section 28 ? cpu instr set stwcx. store lword conditional indexed ea (ra|0) + (rb) if reserve = 1 then ms(ea, 4) (rs) reserve 0 (cr[cr0]) 2 0 || 1 || xer so else (cr[cr0]) 2 0 || 0 || xer so an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 when the ra field is 0, and is the contents of register ra otherwise. if the reservation bit contains 1 when the instruction is executed, the contents of register rs are stored into the lword at the ea and the reservation bit is cleared. if the reservation bit contains 0 when the instruction is executed, no store operation is performed. cr[cr0] is set as follows: cr[cr0] lt, gt are cleared cr[cr0] eq is set to the state of the reservation bit at the start of the instruction cr[cr0] so is set to the contents of the xer[so] bit registers altered cr[cr0] lt, gt, eq, so programming note lwarx and the stwcx. instruction should paired in a loop, as shown in the following example, to create the effect of an atomic operation to a memory area used as a semaphore between asynchronous processes. only lwarx can set the reservation bit to 1. stwcx. sets the reservation bit to 0 upon its completion, whether or not stwcx. sent (rs) to memory. cr[cr0] eq must be examined to determine whether (rs) was sent to memory. loop: lwarx # read the semaphore from memory; set reservation ? alter ? # change the semaphore bits in register as required stwcx. # attempt to store semaphore; reset reservation bne loop# an asynchronous process has intervened; try again if the asynchronous process in the code example had paired lwarx with a store other than stwcx. , the reservation bit would not have been cleared in the asynchronous process, and the code example would have overwritten the semaphore. exceptions an alignment exception occurs if the ea is not lword-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. stwcx. rs, ra, rb 31 0 31 rs ra 16 11 6 rb 21 150 1 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-146 ? 2000 plx technology, inc. all rights reserved. stwu store lword with update ea (ra|0) + exts(d) ms(ea, 4) (rs) (ra) ea an effective address (ea) is formed by adding a displacement to a base address. the displacement is obtained by sign-extending the 16-bit d field to 32 bits. the base address is 0 when the ra field is 0, and is the contents of register ra otherwise. the contents of register rs are stored into the lword at the ea. the ea is placed into register ra. registers altered ra invalid instruction forms ra = 0 exceptions an alignment exception occurs if msr[le] = 1 and the ea is not lword-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. stwu rs, d(ra) 37 0 31 rs ra d 16 11 6 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-147 section 28 ? cpu instr set stwux store lword with update indexed ea (ra|0) + (rb) ms(ea, 4) (rs) (ra) ea an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 when the ra field is 0, and is the contents of register ra otherwise. the contents of register rs are stored into the lword at the ea. the ea is placed into register ra. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered ra invalid instruction forms reserved fields ra = 0 exceptions an alignment exception occurs if msr[le] = 1 and the ea is not lword-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. stwux rs, ra, rb 31 0 31 rs ra 16 11 6 rb 21 183 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-148 ? 2000 plx technology, inc. all rights reserved. stwx store lword indexed ea (ra|0) + (rb) ms(ea,4) (rs) an effective address (ea) is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 when the ra field is 0, and is the contents of register ra otherwise. the contents of register rs are stored into the lword at the ea. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields exceptions an alignment exception occurs if msr[le] = 1 and the ea is not lword-aligned. architecture note this instruction is part of the powerpc user instruction set architecture. stwx rs, ra, rb 31 0 31 rs ra 16 11 6 rb 21 151 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-149 section 28 ? cpu instr set subf subtract from (rt) ? (ra) + (rb) + 1 the sum of the ones complement of register ra, register rb, and 1 is stored into register rt. registers altered rt cr[cr0] lt, gt, eq, so if rc contains 1 xer[so, ov] if oe contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. subf rt, ra, rb oe=0, rc=0 subf. rt, ra, rb oe=0, rc=1 subfo rt, ra, rb oe=1, rc=0 subfo. rt, ra, rb oe=1, rc=1 table 28-30. extended mnemonics for subf, subf., subfo, subfo. mnemonic operands function other registers changed sub rt, ra, rb subtract (rb) from (ra). (rt) ? (rb) + (ra) + 1. extended mnemonic for subf rt,rb,ra sub. extended mnemonic for subf. rt,rb,ra cr[cr0] subo extended mnemonic for subfo rt,rb,ra xer[so, ov] subo. extended mnemonic for subfo. rt,rb,ra cr[cr0] xer[so, ov] 31 0 31 rt ra 40 16 11 6 rb rc 21 22 oe section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-150 ? 2000 plx technology, inc. all rights reserved. subfc subtract from carrying (rt) ? (ra) + (rb) + 1 if ? (ra) + (rb) + 1 2 32 ? 1 then xer[ca] 1 else xer[ca] 0 the sum of the ones complement of register ra, register rb, and 1 is stored into register rt. xer[ca] is set to a value determined by the unsigned magnitude of the result of the subtract operation. registers altered rt xer[ca] cr[cr0] lt, gt, eq, so if rc contains 1 xer[so, ov] if oe contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. subfc rt, ra, rb oe=0, rc=0 subfc. rt, ra, rb oe=0, rc=1 subfco rt, ra, rb oe=1, rc=0 subfco. rt, ra, rb oe=1, rc=1 table 28-31. extended mnemonics for subfc, subfc., subfco, subfco. mnemonic operands function other registers changed subc rt, ra, rb subtract (rb) from (ra). (rt) ? (rb) + (ra) + 1. place carry-out in xer[ca]. extended mnemonic for subfc rt,rb,ra subc. extended mnemonic for subfc. rt,rb,ra cr[cr0] subco extended mnemonic for subfco rt,rb,ra xer[so, ov] subco. extended mnemonic for subfco. rt,rb,ra cr[cr0] xer[so, ov] 31 0 31 rt ra 8 16 11 6 rb rc 21 22 oe > u section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-151 section 28 ? cpu instr set subfe subtract from extended (rt) ? (ra) + (rb) + xer[ca] if ? (ra) + (rb) + xer[ca] 2 32 ? 1 then xer[ca] 1 else xer[ca] 0 the sum of the ones complement of register ra, register rb, and xer[ca] is placed into register rt. xer[ca] is set to a value determined by the unsigned magnitude of the result of the subtract operation. registers altered rt xer[ca] cr[cr0] lt, gt, eq, so if rc contains 1 xer[so, ov] if oe contains 1 architecture note this instruction is part of the powerpc user instruction set architecture. subfe rt, ra, rb oe=0, rc=0 subfe. rt, ra, rb oe=0, rc=1 subfeo rt, ra, rb oe=1, rc=0 subfeo. rt, ra, rb oe=1, rc=1 31 0 31 rt ra 136 16 11 6 rb rc 21 22 oe > u section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-152 ? 2000 plx technology, inc. all rights reserved. subfic subtract from immediate carrying (rt) ? (ra) + exts(im) + 1 if ? (ra) + exts(im) + 1 2 32 ? 1 then xer[ca] 1 else xer[ca] 0 the sum of the ones complement of ra, the im field sign-extended to 32 bits, and 1 is placed into register rt. xer[ca] is set to a value determined by the unsigned magnitude of the result of the subtract operation. registers altered rt xer[ca] architecture note this instruction is part of the powerpc user instruction set architecture. subfic rt, ra, im 8 0 31 rt ra im 16 11 6 > u section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-153 section 28 ? cpu instr set subfme subtract from minus one extended (rt) ? (ra) ? 1 + xer[ca] if ? (ra) + 0xffff ffff + xer[ca] 2 32 ? 1 then xer[ca] 1 else xer[ca] 0 the sum of the ones complement of register ra, ? 1, and xer[ca] is placed into register rt. xer[ca] is set to a value determined by the unsigned magnitude of the result of the subtract operation. registers altered rt cr[cr0] lt, gt, eq, so if rc contains 1 xer[so, ov] if oe contains 1 xer[ca] invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. subfme rt, ra oe=0, rc=0 subfme. rt, ra oe=0, rc=1 subfmeo rt, ra oe=1, rc=0 subfmeo. rt, ra oe=1, rc=1 31 0 31 rt ra 232 16 11 6 rc 21 22 oe > u section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-154 ? 2000 plx technology, inc. all rights reserved. subfze subtract from zero extended (rt) ? (ra) + xer[ca] if ? (ra) + xer[ca] 2 32 ? 1 then xer[ca] 1 else xer[ca] 0 the sum of the ones complement of register ra and xer[ca] is stored into register rt. xer[ca] is set to a value determined by the unsigned magnitude of the result of the subtract operation. registers altered rt xer[ca] cr[cr0] lt, gt, eq, so if rc contains 1 xer[so, ov] if oe contains 1 invalid instruction forms reserved fields architecture note this instruction is part of the powerpc user instruction set architecture. subfze rt, ra oe=0, rc=0 subfze. rt, ra oe=0, rc=1 subfzeo rt, ra oe=1, rc=0 subfzeo. rt, ra oe=1, rc=1 31 0 31 rt ra 200 16 11 6 rc 21 22 oe > u section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-155 section 28 ? cpu instr set sync synchronize synchronize system the sync instruction guarantees that all instructions initiated by the processor preceding the sync instruction complete before the sync instruction completes, and that no subsequent instructions are initiated by the processor until after sync completes. when sync completes, all storage accesses initiated by the processor prior to sync are completed with respect to all mechanisms that access storage. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none. invalid instruction forms reserved fields programming note architecturally, the eieio instruction orders storage access, not instruction completion. therefore, non-storage operations that follow eieio could complete before storage operations that precede eieio . the sync instruction guarantees ordering of instruction completion and storage access. for the iop 480 cpu, the eieio instruction is implemented to behave as a sync instruction. to write code that is portable between various powerpc implementations, programmers should use the mnemonic which corresponds to the desired behavior. architecture note this instruction is part of the powerpc user instruction set architecture. sync 31 0 31 598 6 21 this instruction is not part of the powerpc architecture section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-156 ? 2000 plx technology, inc. all rights reserved. tlbia tlb invalidate all all of the entries in the tlb are invalidated and become unavailable for translation by clearing the valid (v) bit in the tlbhi portion of each tlb entry. the rest of the fields in the tlb entries are unmodified. registers altered none. invalid instruction forms none. programming note this instruction is privileged. translation is not required to be active during the execution of this instruction. the effects of the invalidation are not guaranteed to be visible to the programming model until the completion of a context synchronizing operation. architecture note this instruction is part of the powerpc operating environment architecture. tlbia 31 0 31 6 21 370 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-157 section 28 ? cpu instr set tlbre tlb read entry if ws 4 = 1 (rt) tlblo[(ra 26:31 )] else (rt) tlbhi[(ra 26:31 )] (pid) tid from tlb[(ra 26:31 )] the contents of the selected tlb entry is placed into register rt (and possibly into pid). bits 26:31 of the contents of ra is used as an index into the tlb. if this index specifies a tlb entry that does not exist, the results are undefined. the ws field specifies which portion (tlbhi or tlblo) of the entry is loaded into rt. if tlbhi is being accessed, the pid spr is set to the value of the tid field in the tlb entry. if the ws field is not 0 or 1, the instruction form is invalid and the result is undefined. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered rt pid (if ws = 0) invalid instruction forms reserved fields invalid ws value programming notes this instruction is privileged. translation is not required to be active during the execution of this instruction. the contents of rt after the execution of this instruction are interpreted as follows: if ws = 0 (tlbhi): rt[0:21] epn[0:21] rt[22:24] size[0:2] rt[25] v rt[26] e rt[27] k rt[28:31] 0 pid[24:31] tid[0:7]; (note that the tid is copied to the pid, not to rt) tlbre rt, ra, ws 31 0 31 rt ra 16 11 6 ws 21 946 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-158 ? 2000 plx technology, inc. all rights reserved. if ws = 1 (tlblo): rt[0:21] rpn[0:21] rt[22:23] ex,wr rt[24:27] zsel[0:3] rt[28:31] wimg architecture note programs using this instruction are not portable to powerpc implementations that do not implement the ibm powerpc embedded environment. table 28-32. extended mnemonics for tlbre mnemonic operands function other registers changed tlbrehi rt, ra load tlbhi portion of the selected tlb entry into rt. load the pid register with the contents of the tid field of the selected tlb entry. (rt) tlbhi[(ra)] (pid) tlb[(ra)] tid extended mnemonic for tlbre rt,ra,0 tlbrelo rt, ra load tlblo portion of the selected tlb entry into rt. (rt) tlblo[(ra)] extended mnemonic for tlbre rt,ra,1 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-159 section 28 ? cpu instr set tlbsx tlb search indexed ea (ra|0) + (rb) if rc = 1 cr[cr0] lt 0 cr[cr0] gt 0 cr[cr0] so xer[so} if valid tlb entry matching ea and pid is in the tlb then (rt) index of matching tlb entry if rc = 1 cr[cr0] eq 1 else (rt) undefined if rc = 1 cr[cr0] eq 0 an effective address is formed by adding an index to a base address. the index is the contents of register rb. the base address is 0 if the ra field is 0 and is the contents of register ra otherwise. the tlb is searched for a valid entry which translates ea and pid. see section 27.3.3, ? page identification fields, ? on page 27-3, for details. the record bit (rc) specifies whether the results of the search affect cr[cr0] as shown above. the intention is that cr[cr0] eq can be tested after a tlbsx. instruction if there is a possibility that the search may fail. registers altered cr[cr0] lt, gt, eq, so if rc contains 1 invalid instruction forms none. programming note this instruction is privileged. translation is not required to be active during the execution of this instruction. architecture note programs using this instruction are not portable to powerpc implementations that do not implement the ibm powerpc embedded environment. tlbsx rt, ra, rb rc=0 tlbsx. rt, ra, rb rc=1 31 0 31 rt ra 914 16 11 6 rb rc 21 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-160 ? 2000 plx technology, inc. all rights reserved. tlbsync tlb synchronize the tlbsync instruction is provided in the powerpc architecture to support synchronization of tlb operations among the processors of a multi-processor system. this instruction performs no operation on the iop 480 cpu, and is provided to facilitate code portability. registers altered none. invalid instruction forms none. programming notes this instruction is privileged. translation is not required to be active during the execution of this instruction. because the iop 480 cpu does not support tightly-coupled multiprocessor systems, tlbsync performs no operation. architecture note this instruction is part of the powerpc operating environment architecture. tlbsync 31 0 31 6 21 566 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-161 section 28 ? cpu instr set tlbwe tlb write entry if ws 4 = 1 tlblo[(ra 26:31 )] (rs) else tlbhi[(ra 26:31 )] (rs) tid of tlb[(ra 26:31 )] (pid 24:31 ) the contents of the selected tlb entry is replaced with the contents of register rs (and possibly pid). bits 26:31 of the contents of ra are used as an index into the tlb. if this index specifies a tlb entry that does not exist, the results are undefined. the ws field specifies which portion (tlbhi or tlblo) of the entry is replaced from rs. for instructions that specify tlbhi, the tid field in the tlb entry is supplied from pid 24:31. if the ws field is not 0 or 1, the instruction form is invalid and the result is undefined. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none. invalid instruction forms reserved fields invalid ws value programming notes this instruction is privileged. translation is not required to be active during the execution of this instruction. the effects of this update are not guaranteed to be visible to the programming model until the completion of a context synchronizing operation. for example, updating a zone selection field within the tlb while in supervisor code should be followed by an isync instruction (or other context synchronizing operation) to guarantee that the desired translation and protection domains are used. tlbwe writes the tlb fields from rs and the pid as follows: if ws = 0 (tlbhi): epn[0:21] rs[0:21] size[0:2] rs[22:24] v rs[25] e rs[26] k rs[27] tid[0:7] pid[24:31]; (note that the tid is written from the pid, not rs) tlbwe rs, ra, ws 31 0 31 rs ra 16 11 6 ws 21 978 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-162 ? 2000 plx technology, inc. all rights reserved. if ws = 1 (tlblo): rpn[0:21] rs[0:21] ex,wr rs[22:23] zsel[0:3] rs[24:27] wimg rs[28:31] architecture note programs using this instruction are not portable to powerpc implementations that do not implement the ibm powerpc embedded environment. table 28-33. extended mnemonics for tlbwe mnemonic operands function other registers changed tlbwehi rs, ra write tlbhi portion of the selected tlb entry from rs. write the tid register of the selected tlb entry from the pid register. tlbhi[(ra)] (rs) tlb[(ra)] tid (pid 24:31 ) extended mnemonic for tlbwe rs,ra,0 tlbwelo rs, ra write tlblo portion of the selected tlb entry from rs. tlblo[(ra)] (rs) extended mnemonic for tlbwe rs,ra,1 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-163 section 28 ? cpu instr set tw trap lword if ( ((ra) (rb) to 0 =1) ((ra) (rb) to 1 =1) ((ra) (rb) to 2 =1) ((ra) (rb) to 3 =1) ((ra) (rb) to 4 = 1) ) then trap (see details below) register ra is compared with register rb. if any comparison condition selected by the to field is true, a trap occurs. the behavior of a trap depends upon the debug mode of the processor, as described below: if trap is not enabled as a debug event (dbcr[tde] = 0 or dbcr[edm,idm] = 0,0): trap causes a program interrupt. see section 11.7.6, ? data storage exceptions, ? on page 11-21, for more information. (srr0) address of tw instruction (srr1) (msr) (esr[ptr]) 1 (msr[we, ee, pr, dr, ir]) 0 (msr[le]) (msr[ile]) pc evpr 0:15 || 0x0700 if trap is enabled as an external debug event (dbcr[tde] = 1 and dbcr[edm] = 1): trap goes to the debug stop state, to be handled by an external debugger with hardware control. (dbsr[tie]) 1 in addition, if trap is also enabled as an internal debug event (dbcr[idm] = 1) and debug exceptions are disabled (msr[de] = 0), then report an imprecise event: (dbsr[ide]) 1 pc address of tw instruction if trap is enabled as an internal debug event and not an external debug event (dbcr[tde] = 1 and dbcr[edm,idm] = 0,1) and debug exceptions are enabled (msr[de] = 1): trap causes a debug interrupt. see section 11.7.17, ? debug exception handling, ? on page 11-28, for more information. (srr2) address of tw instruction (srr3) (msr) (dbsr[tie]) 1 (msr[we, ee, pr, ce, de, dr, ir]) 0 (msr[le]) (msr[ile]) pc evpr 0:15 || 0x2000 tw to, ra, rb 31 0 31 to ra 4 16 11 6 21 rb < > = < u > u section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-164 ? 2000 plx technology, inc. all rights reserved. if trap is enabled as an internal debug event and not an external debug event (dbcr[tde] = 1 and dbcr[edm,idm] = 0,1) and debug exceptions are disabled (msr[de] = 0): trap reports the debug event as an imprecise event and causes a program interrupt. see section 11.7.10, ? program exceptions, ? on page 11-24, for more information. (srr0) address of tw instruction (srr1) (msr) (esr[ptr]) 1 (dbsr[tie,ide]) 1,1 (msr[we, ee, pr, dr, ir]) 0 (msr[le]) (msr[ile]) pc evpr 0:15 || 0x0700 if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered none invalid instruction forms reserved fields programming note this instruction is inserted into the execution stream by a debugger to implement breakpoints, and is not typically used by application code. architecture note this instruction is part of the powerpc user instruction set architecture. section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-165 section 28 ? cpu instr set table 28-34. extended mnemonics for tw mnemonic operands function other registers changed trap trap unconditionally. extended mnemonic for tw 31,0,0 tweq ra, rb trap if (ra) equal to (rb). extended mnemonic for tw 4,ra,rb twge ra, rb trap if (ra) greater than or equal to (rb). extended mnemonic for tw 12,ra,rb twgt ra, rb trap if (ra) greater than (rb). extended mnemonic for tw 8,ra,rb twle ra, rb trap if (ra) less than or equal to (rb). extended mnemonic for tw 20,ra,rb twlge ra, rb trap if (ra) logically greater than or equal to (rb). extended mnemonic for tw 5,ra,rb twlgt ra, rb trap if (ra) logically greater than (rb). extended mnemonic for tw 1,ra,rb twlle ra, rb trap if (ra) logically less than or equal to (rb). extended mnemonic for tw 6,ra,rb twllt ra, rb trap if (ra) logically less than (rb). extended mnemonic for tw 2,ra,rb twlng ra, rb trap if (ra) logically not greater than (rb). extended mnemonic for tw 6,ra,rb twlnl ra, rb trap if (ra) logically not less than (rb). extended mnemonic for tw 5,ra,rb twlt ra, rb trap if (ra) less than (rb). extended mnemonic for tw 16,ra,rb twne ra, rb trap if (ra) not equal to (rb). extended mnemonic for tw 24,ra,rb twng ra, rb trap if (ra) not greater than (rb). extended mnemonic for tw 20,ra,rb twnl ra, rb trap if (ra) not less than (rb). extended mnemonic for tw 12,ra,rb section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-166 ? 2000 plx technology, inc. all rights reserved. twi trap lword immediate if ( ((ra) exts(im) to 0 =1) ((ra) exts(im) to 1 =1) ((ra) exts(im) to 2 =1) ((ra) exts(im) to 3 =1) ((ra) exts(im) to 4 = 1) ) then trap (see details below) register ra is compared with the im field, which has been sign-extended to 32 bits. if any comparison condition selected by the to field is true, a trap occurs. the behavior of a trap depends upon the debug mode of the processor, as described below: if trap is not enabled as a debug event (dbcr[tde] = 0 or dbcr[edm,idm] = 0,0): trap causes a program interrupt. see section 11.7.10, ? program exceptions, ? on page 11-24, for more information. (srr0) address of twi instruction (srr1) (msr) (esr[ptr]) 1 (msr[we, ee, pr, dr, ir]) 0 (msr[le]) (msr[ile]) pc evpr 0:15 || 0x0700 if trap is enabled as an external debug event (dbcr[tde] = 1 and dbcr[edm] = 1): trap goes to the debug stop state, to be handled by an external debugger with hardware control over the iop 480 cpu . (dbsr[tie]) 1 in addition, if trap is also enabled as an internal debug event (dbcr[idm] = 1) and debug exceptions are disabled (msr[de] = 0), then report an imprecise event: (dbsr[ide]) 1 pc address of twi instruction if trap is enabled as an internal debug event and not an external debug event (dbcr[tde] = 1 and dbcr[edm,idm] = 0,1) and debug exceptions are enabled (msr[de] = 1): trap causes a debug interrupt. see section 11.7.17, ? debug exception handling, ? on page 11-28, for further information. (srr2) address of twi instruction (srr3) (msr) (dbsr[tie]) 1 (msr[we, ee, pr, ce, de, dr, ir]) 0 (msr[le]) (msr[ile]) pc evpr 0:15 || 0x2000 twi to, ra, im 3 0 31 to ra im 16 11 6 < > = < u > u section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-167 section 28 ? cpu instr set if trap is enabled as an internal debug event and not an external debug event (dbcr[tde] = 1 and dbcr[edm,idm] = 0,1) and debug exceptions are disabled (msr[de] = 0): trap reports the debug event as an imprecise event and causes a program interrupt. see section 11.7.10, ? program exceptions, ? on page 11-24, for more information. (srr0) address of twi instruction (srr1) (msr) (esr[ptr]) 1 (dbsr[tie,ide]) 1,1 (msr[we, ee, pr, dr, ir]) 0 (msr[le]) (msr[ile]) pc evpr 0:15 || 0x0700 registers altered none programming note this instruction is inserted into the execution stream by a debugger to implement breakpoints, and is not typically used by application code. architecture note this instruction is part of the powerpc user instruction set architecture. section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-168 ? 2000 plx technology, inc. all rights reserved. table 28-35. extended mnemonics for twi mnemonic operands function other registers changed tweqi ra, im trap if (ra) equal to exts(im). extended mnemonic for twi 4,ra,im twgei ra, im trap if (ra) greater than or equal to exts(im). extended mnemonic for twi 12,ra,im twgti ra, im trap if (ra) greater than exts(im). extended mnemonic for twi 8,ra,im twlei ra, im trap if (ra) less than or equal to exts(im). extended mnemonic for twi 20,ra,im twlgei ra, im trap if (ra) logically greater than or equal to exts(im). extended mnemonic for twi 5,ra,im twlgti ra, im trap if (ra) logically greater than exts(im). extended mnemonic for twi 1,ra,im twllei ra, im trap if (ra) logically less than or equal to exts(im). extended mnemonic for twi 6,ra,im twllti ra, im trap if (ra) logically less than exts(im). extended mnemonic for twi 2,ra,im twlngi ra, im trap if (ra) logically not greater than exts(im). extended mnemonic for twi 6,ra,im twlnli ra, im trap if (ra) logically not less than exts(im). extended mnemonic for twi 5,ra,im twlti ra, im trap if (ra) less than exts(im). extended mnemonic for twi 16,ra,im twnei ra, im trap if (ra) not equal to exts(im). extended mnemonic for twi 24,ra,im twngi ra, im trap if (ra) not greater than exts(im). extended mnemonic for twi 20,ra,im twnli ra, im trap if (ra) not less than exts(im). extended mnemonic for twi 12,ra,im section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-169 section 28 ? cpu instr set wrtee write external enable msr[ee] (rs) 16 the msr[ee] is set to the value specified by bit 16 of register rs. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered msr[ee] invalid instruction forms reserved fields programming note execution of this instruction is privileged. this instruction is used to provide atomic update of msr[ee]. typical usage is: mfmsr rn #save ee in rn[16] wrteei 0 #turn off ee #code with ee disabled wrtee rn #restore ee without affecting other msr changes that may have occurred during the disabled code architecture note programs using this instruction are not portable to powerpc implementations that do not implement the ibm powerpc embedded environment. wrtee rs 31 0 131 6 21 rs 11 31 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-170 ? 2000 plx technology, inc. all rights reserved. wrteei write external enable immediate msr[ee] e the msr[ee] is set to the value specified by the e field. if instruction bit 31 contains 1, the contents of cr[cr0] are undefined. registers altered msr[ee] invalid instruction forms reserved fields programming note execution of this instruction is privileged. this instruction is used to provide atomic update of msr[ee]. typical usage is: mfmsr rn #save ee in rn[16] wrteei 0 #turn off ee #code with ee disabled wrtee rn #restore ee without affecting other msr changes that may have occurred during the disabled code architecture note programs using this instruction are not portable to powerpc implementations that do not implement the ibm powerpc embedded environment. wrteei e 31 0 163 21 31 6 e 17 16 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-171 section 28 ? cpu instr set xor xor (ra) (rs) (rb) the contents of register rs are xored with the contents of register rb; the result is placed into register ra. registers altered cr[cr0] lt, gt, eq, so if rc contains 1 ra architecture note this instruction is part of the powerpc user instruction set architecture. xor ra, rs, rb rc=0 xor. ra, rs, rb rc=1 31 0 31 rs ra 316 16 11 6 rb rc 21 section 28 iop 480 cpu instruction set alphabetical instruction listing iop 480 data book r2.0 28-172 ? 2000 plx technology, inc. all rights reserved. xori xor immediate (ra) (rs) ( 16 0||im) the im field is extended to 32 bits by concatenating 16 0-bits on the left. the contents of register rs are xored with the extended im field; the result is placed into register ra. registers altered ra architecture note this instruction is part of the powerpc user instruction set architecture. xori ra, rs, im 26 0 31 rs ra im 16 11 6 section 28 alphabetical instruction listing iop 480 cpu instruction set iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 28-173 section 28 ? cpu instr set xoris xor immediate shifted (ra) (rs) (im || 16 0) the im field is extended to 32 bits by concatenating 16 0-bits on the right. the contents of register rs are xored with the extended im field; the result is placed into register ra. registers altered ra architecture note this instruction is part of the powerpc user instruction set architecture. xoris ra, rs, im 27 0 31 rs ra im 16 11 6 iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-1 section 29 ? reg summary 29 iop 480 cpu register summary all registers contained in the iop 480 cpu are architected as 32 bits. register 29-1 and register 29-2 define required addressing to access the registers. the pages following these tables define the bit usage within each register. 29.1 reserved registers any register numbers not listed in these tables are reserved, and should be neither read nor written. these reserved register numbers may be used for additional functions on future powerpc embedded controllers. 29.2 reserved fields for all registers with fields marked as reserved , the reserved fields should be written as zero and read as undefined . that is, when writing to a reserved field, write a zero to that field. when reading from a reserved field, ignore that field. a good coding practice is to perform the initial write to a register with reserved fields as described in the preceding paragraph, and to perform all subsequent writes to the register using a read-modify-write strategy: read the register, alter desired fields with logical instructions, and then write the register. 29.3 general purpose registers the iop 480 cpu contains 32 general purpose registers (gprs). the contents of these registers can be loaded from memory using load instructions and stored to memory using store instructions. gprs are also addressed by all integer instructions. register 29-1 lists the iop 480 cpu general purpose registers. 29.4 machine state register and condition register because these registers are accessed using special instructions, they do not require addressing. 29.5 special purpose registers special purpose registers (sprs), which are part of the powerpc embedded architecture, are accessed using the mtspr and mfspr instructions. sprs control the use of the debug facilities, timers, interrupts, storage control attributes, and other architected processor resources. register 29-2 shows the mnemonics, names, and numbers of the sprs. the columns under ? sprn ? list the register numbers used as operands in assembler language coding of the mfspr and mtspr instructions. the column labeled ? sprf ? lists the corresponding fields contained in the machine code of mfspr and mtspr . the sprn field contains two five-bit subfields of the sprf field; the subfields are reversed in the machine code for the mfspr and mtspr instructions (sprn sprf 5:9 || sprf 0:4 ) for compatibility with the power architecture. note that the assembler handles the special coding transparently. the only sprs that are not privileged are the count register (ctr), the link register (lr), the time base high user-mode (tbhu), the time base low user- mode (tblu), and the fixed-point exception register (xer). see section 24.8.3, ? privileged sprs, ? on page 24-28. register 29-2 lists the sprs, their mnemonics and names, numbers (sprn) and corresponding sprf numbers, and access. all spr numbers not listed are reserved, and should be neither read nor written. register 29-1. iop 480 cpu general purpose registers mnemonic register name gpr number access decimal hex r0 ? r31 general purpose register 0 ? 31 0 ? 31 0x0 ? 0x1f read/write section 29 iop 480 cpu register summary special purpose registers iop 480 data book r2.0 29-2 ? 2000 plx technology, inc. all rights reserved. register 29-2. special purpose registers mnemonic register name sprn sprf access decimal hex cdbcr cache debug control register 983 0x3d7 0x2fe read/write ctr count register 9 0x009 0x120 read/write dac data address compare 1014 0x3f6 0x2df read/write dbcr debug control register 1010 0x3f2 0x25f read/write dbsr debug status register 1008 0x3f0 0x21f read/clear dccr data cache cacheability register 1018 0x3fa 0x35f read/write dcwr data cache write-through register 954 0x3ba 0x35d read/write dear data error address register 981 0x3d5 0x2be read/write esr exception syndrome register 980 0x3d4 0x29e read/write evpr exception vector prefix register 982 0x3d6 0x2de read/write iac instruction address compare 1012 0x3f4 0x29f read/write iccr instruction cache cacheability register 1019 0x3fb 0x37f read/write icdbdr instruction cache debug data register 979 0x3d3 0x27e read-only lr link register 8 0x008 0x100 read/write pid process id 945 0x3b1 0x23d read/write pit programmable interval timer 987 0x3db 0x37e read/write pvr processor version register 287 0x11f 0x3e8 read-only sgr storage guarded register 953 0x3b9 0x33d read/write skr storage compression register 956 0x3bc 0x39d read/write sler storage little endian register 955 0x3bb 0x37d read/write sprg0 spr general purpose register 0 272 0x110 0x208 read/write sprg1 spr general purpose register 1 273 0x111 0x228 read/write sprg2 spr general purpose register 2 274 0x112 0x248 read/write sprg3 spr general purpose register 3 275 0x113 0x268 read/write srr0 save/restore register 0 26 0x01a 0x340 read/write srr1 save/restore register 1 27 0x01b 0x360 read/write srr2 save/restore register 2 990 0x3de 0x3de read/write srr3 save/restore register 3 991 0x3df 0x3fe read/write tbhi time base high 988 0x3dc 0x39e read/write tbhu time base high user-mode 972 0x3cc 0x19e read only tblo time base low 989 0x3dd 0x3be read/write tblu time base low user-mode 973 0x3cd 0x1be read only tcr timer control register 986 0x3da 0x35e read/write tsr timer status register 984 0x3d8 0x31e read/clear xer fixed point exception register 1 0x001 0x020 read/write zpr zone protection register 944 0x3b0 0x21d privileged section 29 device control registers iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-3 section 29 ? reg summary 29.6 device control registers device control registers (dcrs), which are architecturally outside of the processor core, are accessed using the mtdcr and mfdcr instructions. dcrs are used to control, configure, and hold status for various functional units that are not part of the risc processor core. although the iop 480 cpu does not contain dcrs, the mtdcr and mfdcr instructions are provided. the mtdcr and mfdcr instructions are privileged, for all dcr numbers. therefore, all accesses to dcrs are privileged. see section 24.8, ? privileged mode operation, ? on page 24-27. all dcr numbers reserved, and should not be read nor written, unless they are part of a core+asic implementation. 29.7 alphabetical register listing the following pages list the registers available in the iop 480 cpu. for each register, the following information is supplied: register name and mnemonic register type (spr) register number (address) a diagram illustrating the register fields (all register fields have mnemonics, unless there is only one field) a table describing the register fields, giving field mnemonic, bit location, name, and function associated with various field values section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-4 ? 2000 plx technology, inc. all rights reserved. cdbcr spr 0x3d7 see also section 25.4, ? cache control and debugging features, ? on page 25-7. register 29-3. cache debug control register (cdbcr) 0:1 dsd dcu size disable 00 the connected cache size is the real cache size. 01 the connected cache size is the real cache size/2. 10 the connected cache size is the real cache size/4. 11 the connected cache size is the real cache size/8. see table 25-5, ? cdbcr[dsd], cdbcr[isd], and effective cache size, ? on page 25-15, for more information on bit settings for various real and effective cache sizes. 2:3 isd icu size disable 00 the connected cache size is the real cache size. 01 the connected cache size is the real cache size/2. 10 the connected cache size is the real cache size/4. 11 the connected cache size is the real cache size/8. see table 25-5, ? cdbcr[dsd], cdbcr[isd], and effective cache size, ? on page 25-15, for more information on bit settings for various real and effective cache sizes. 4:17 reserved 18 dwda delayed write data acknowledge 0 normal processor write data acknowledge. 1 write data acknowledge is delayed one processor clock cycle. 19 woa write-on-allocate 0 all store misses result in a line fill. 1 store misses do not cause a line fill, but result in a non- cacheable store. 20 ddk disable data-side compression 0 use k storage attribute to specify data compression 1 disable data-side compression, regardless of k attribute 21 ocm instruction-side ocm (iocm) mode 0 iocm is presented only with cacheable fetches 1 iocm is presented with cacheable and non-cacheable fetches 22 ldbe load debug enable 0 load data is invisible on data-side ocm 1 load data is visible on data-side ocm 23 dlxe dcu lock-out exception enable 0 dcu lock-out exception is disabled. 1 dcu lock-out exception is enabled. 24 iuxe icu unlock exception enable 0 icu unlock exception is disabled. 1 icu unlock exception is enabled. 25 duxe dcu unlock exception enable 0 dcu unlock exception is disabled. 1 dcu unlock exception is enabled. 26 27 28 30 31 cis 25 24 23 4 lke duxe dlxe iuxe 22 20 19 18 woa 21 ddk ocm 0 12 3 dsd isd 17 dwda ldbe cws section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-5 section 29 ? reg summary 26 lke lock enable 0 line locking is disabled. 1 line locking is enabled. 27 cis cache information select 0 information is cache data. 1 information is cache tag. 28:30 reserved 31 cws cache way select 0 cache way is a. 1 cache way is b. register 29-3. cache debug control register (cdbcr) (continued) section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-6 ? 2000 plx technology, inc. all rights reserved. cr see also section 24.2.3, ? condition register (cr), ? on page 24-7. register 29-4. condition register (cr) 0:3 cr0 condition register field 0 cr[cr n ] 0:3 indicate less than, greater than, equal to, and summary overflow, respectively. 4:7 cr1 condition register field 1 see the description of cr[cr0]. 8:11 cr2 condition register field 2 see the description of cr[cr0]. 12:15 cr3 condition register field 3 see the description of cr[cr0]. 16:19 cr4 condition register field 4 see the description of cr[cr0]. 20:23 cr5 condition register field 5 see the description of cr[cr0]. 24:27 cr6 condition register field 6 see the description of cr[cr0]. 28:31 cr7 condition register field 7 see the description of cr[cr0]. cr2 034781112 16 20 31 cr0 cr3 cr4 15 19 cr1 23 28 27 24 cr5 cr6 cr7 section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-7 section 29 ? reg summary ctr spr 0x009 see also section 24.2.2.1, ? count register (ctr), ? on page 24-4. register 29-5. count register (ctr) 0:31 count used as count for branch conditional with decrement instructions, or as address for branch-to-counter instructions. section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-8 ? 2000 plx technology, inc. all rights reserved. dac1 spr 0x3f6 see also section 26.6.3, ? data address compare register (dac1), ? on page 26-7. register 29-6. data address compare register (dac1) 0:31 data address compare (dac) byte address dbcr[d1s] determines byte, word, or lword usage. section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-9 section 29 ? reg summary dbcr spr 0x3f2 see also section 26.6.1, ? debug control register (dbcr), ? on page 26-3. register 29-7. debug control register (dbcr) 0 edm external debug mode 0 disable 1 enable 1 idm internal debug mode 0 disable 1 enable 2:3 rst reset 00 no action 01 core reset 10 chip reset 11 system reset note: writing 01, 10, or 11 to this field causes a processor reset request. 4 ic instruction completion debug event 0 disable 1 disable instruction completion does not cause a debug event if msr[de] = 0 in internal debug mode. 5 bt branch taken debug event 0 disable 1 enable branch taken does not cause a debug event if msr[de] = 0 in internal debug mode. 6 ede exception debug event 0 disable 1 enable critical exceptions do not cause debug events if msr[de] = 0 in internal debug mode. 7 tde trap debug event 0 disable 1 enable 8:12 reserved 13 ft freeze timers on debug event 0 free-run timers 1 freeze timers 14 ia1 instruction address compare 1 enable 0 disable 1 enable 15 reserved 16 d1r dac read enable 0 disable 1 enable 17 d1w dac write enable 0 disable 1 enable 0 1 2 3 4 5 6 7 13 14 812 edm rst bt tde ia1 ede ic idm ft 16 17 18 19 20 d1w d1r d1s 15 31 section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-10 ? 2000 plx technology, inc. all rights reserved. 18:19 d1s dac size 00 compare all bits 01 ignore the least significant bit (lsb) 10 ignore the two lsbs 11 ignore the four lsbs exact address compare byte within word address compare byte within lword address compare qword address compare 20:31 reserved register 29-7. debug control register (dbcr) (continued) section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-11 section 29 ? reg summary dbsr spr 0x3f0 read/clear see also section 26.6.2, ? debug status register (dbsr), ? on page 26-5. register 29-8. debug status register (dbsr) 0 ic instruction completion debug event 0 event didn ? t occur 1 event occurred 1 bt branch taken debug event 0 event didn ? t occur 1 event occurred 2 ede exception debug event 0 event didn ? t occur 1 event occurred 3 tie trap instruction debug event 0 event didn ? t occur 1 event occurred 4 ude unconditional debug event 0 event didn ? t occur 1 event occurred 5 ia1 iac1 debug event 0 event didn ? t occur 1 event occurred 6 reserved 7 dr1 dac read debug event 0 event didn ? t occur 1 event occurred 8 dw1 dac write debug event 0 event didn ? t occur 1 event occurred 9:10 reserved 11 ide imprecise debug event 0 event didn ? t occur 1 event occurred 12:21 reserved 22:23 mrr most recent reset 00 no reset has occurred since last cleared by software. 01 core reset 10 chip reset 11 system reset this field is set to a value, indicating the type of reset, when a reset occurs. 24:31 reserved 012 34 5 78 22 23 ic ede ude dw1 bt tie ia1 dr1 mrr 11 21 24 12 ide 6910 31 section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-12 ? 2000 plx technology, inc. all rights reserved. dccr spr 0x3fa see section 27.8, ? real-mode storage attribute control, ? on page 27-13. register 29-9. data cache cacheability register (dccr) 0 s0 0 noncacheable 1 cacheable 0x0000 0000 ? 0x07ff ffff 1 s1 0 noncacheable 1 cacheable 0x0800 0000 ? 0x0fff ffff 2 s2 0 noncacheable 1 cacheable 0x1000 0000 ? 0x17ff ffff 3 s3 0 noncacheable 1 cacheable 0x1800 0000 ? 0x1fff ffff 4 s4 0 noncacheable 1 cacheable 0x2000 0000 ? 0x27ff ffff 5 s5 0 noncacheable 1 cacheable 0x2800 0000 ? 0x2fff ffff 6 s6 0 noncacheable 1 cacheable 0x3000 0000 ? 0x37ff ffff 7 s7 0 noncacheable 1 cacheable 0x3800 0000 ? 0x3fff ffff 8 s8 0 noncacheable 1 cacheable 0x4000 0000 ? 0x47ff ffff 9 s9 0 noncacheable 1 cacheable 0x4800 0000 ? 0x4fff ffff 10 s10 0 noncacheable 1 cacheable 0x5000 0000 ? 0x57ff ffff 11 s11 0 noncacheable 1 cacheable 0x5800 0000 ? 0x5fff ffff 12 s12 0 noncacheable 1 cacheable 0x6000 0000 ? 0x67ff ffff 13 s13 0 noncacheable 1 cacheable 0x6800 0000 ? 0x6fff ffff 14 s14 0 noncacheable 1 cacheable 0x7000 0000 ? 0x77ff ffff 15 s15 0 noncacheable 1 cacheable 0x7800 0000 ? 0x7fff ffff 16 s16 0 noncacheable 1 cacheable 0x8000 0000 ? 0x87ff ffff 17 s17 0 noncacheable 1 cacheable 0x8800 0000 ? 0x8fff ffff s10 03478111213161720 31 s0 s12 s18 s1 s11 s13 21 12 56 910 1415 1819 s2 s3 s5 s7 s9 s4 s6 s8 s14 s15 s16 s17 s19 22 23 26 28 29 30 25 27 24 s20 s22 s24 s28 s26 s30 s21 s23 s25 s27 s29 s31 section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-13 section 29 ? reg summary 18 s18 0 noncacheable 1 cacheable 0x9000 0000 ? 0x97ff ffff 19 s19 0 noncacheable 1 cacheable 0x9800 0000 ? 0x9fff ffff 20 s20 0 noncacheable 1 cacheable 0xa000 0000 ? 0xa7ff ffff 21 s21 0 noncacheable 1 cacheable 0xa800 0000 ? 0xafff ffff 22 s22 0 noncacheable 1 cacheable 0xb000 0000 ? 0xb7ff ffff 23 s23 0 noncacheable 1 cacheable 0xb800 0000 ? 0xbfff ffff 24 s24 0 noncacheable 1 cacheable 0xc000 0000 ? 0xc7ff ffff 25 s25 0 noncacheable 1 cacheable 0xc800 0000 ? 0xcfff ffff 26 s26 0 noncacheable 1 cacheable 0xd000 0000 ? 0xd7ff ffff 27 s27 0 noncacheable 1 cacheable 0xd800 0000 ? 0xdfff ffff 28 s28 0 noncacheable 1 cacheable 0xe000 0000 ? 0xe7ff ffff 29 s29 0 noncacheable 1 cacheable 0xe800 0000 ? 0xefff ffff 30 s30 0 noncacheable 1 cacheable 0xf000 0000 ? 0xf7ff ffff 31 s31 0 noncacheable 1 cacheable 0xf800 0000 ? 0xffff ffff register 29-9. data cache cacheability register (dccr) (continued) section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-14 ? 2000 plx technology, inc. all rights reserved. dcwr spr 0x3ba see section 27.8, ? real-mode storage attribute control, ? on page 27-13. register 29-10. data cache write-thru register (dcwr) 0 w0 0 write-back 1 write-through 0x0000 0000 ? 0x07ff ffff 1 w1 0 write-back 1 write-through 0x0800 0000 ? 0x0fff ffff 2 w2 0 write-back 1 write-through 0x1000 0000 ? 0x17ff ffff 3 w3 0 write-back 1 write-through 0x1800 0000 ? 0x1fff ffff 4 w4 0 write-back 1 write-through 0x2000 0000 ? 0x27ff ffff 5 w5 0 write-back 1 write-through 0x2800 0000 ? 0x2fff ffff 6 w6 0 write-back 1 write-through 0x3000 0000 ? 0x37ff ffff 7 w7 0 write-back 1 write-through 0x3800 0000 ? 0x3fff ffff 8 w8 0 write-back 1 write-through 0x4000 0000 ? 0x47ff ffff 9 w9 0 write-back 1 write-through 0x4800 0000 ? 0x4fff ffff 10 w10 0 write-back 1 write-through 0x5000 0000 ? 0x57ff ffff 11 w11 0 write-back 1 write-through 0x5800 0000 ? 0x5fff ffff 12 w12 0 write-back 1 write-through 0x6000 0000 ? 0x67ff ffff 13 w13 0 write-back 1 write-through 0x6800 0000 ? 0x6fff ffff 14 w14 0 write-back 1 write-through 0x7000 0000 ? 0x77ff ffff 15 w15 0 write-back 1 write-through 0x7800 0000 ? 0x7fff ffff 16 w16 0 write-back 1 write-through 0x8000 0000 ? 0x87ff ffff 17 w17 0 write-back 1 write-through 0x8800 0000 ? 0x8fff ffff w10 03478111213161720 31 w0 w12 w18 w1 w11 w13 21 12 56 910 1415 1819 w2 w3 w5 w7 w9 w4 w6 w8 w14 w15 w16 w17 w19 22 23 26 28 29 30 25 27 24 w20 w22 w24 w28 w26 w30 w21 w23 w25 w27 w29 w31 section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-15 section 29 ? reg summary 18 w18 0 write-back 1 write-through 0x9000 0000 ? 0x97ff ffff 19 w19 0 write-back 1 write-through 0x9800 0000 ? 0x9fff ffff 20 w20 0 write-back 1 write-through 0xa000 0000 ? 0xa7ff ffff 21 w21 0 write-back 1 write-through 0xa800 0000 ? 0xafff ffff 22 w22 0 write-back 1 write-through 0xb000 0000 ? 0xb7ff ffff 23 w23 0 write-back 1 write-through 0xb800 0000 ? 0xbfff ffff 24 w24 0 write-back 1 write-through 0xc000 0000 ? 0xc7ff ffff 25 w25 0 write-back 1 write-through 0xc800 0000 ? 0xcfff ffff 26 w26 0 write-back 1 write-through 0xd000 0000 ? 0xd7ff ffff 27 w27 0 write-back 1 write-through 0xd800 0000 ? 0xdfff ffff 28 w28 0 write-back 1 write-through 0xe000 0000 ? 0xe7ff ffff 29 w29 0 write-back 1 write-through 0xe800 0000 ? 0xefff ffff 30 w30 0 write-back 1 write-through 0xf000 0000 ? 0xf7ff ffff 31 w31 0 write-back 1 write-through 0xf800 0000 ? 0xffff ffff register 29-10. data cache write-thru register (dcwr) (continued) section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-16 ? 2000 plx technology, inc. all rights reserved. dear spr 0x3d5 see also section 11.7.3.6, ? data exception address register (dear), ? on page 11-19. register 29-11. data exception address register (dear) 0:31 address of data error (synchronous) section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-17 section 29 ? reg summary esr spr 0x3d4 see also section 11.7.3.5, ? exception syndrome register (esr), ? on page 11-17. register 29-12. exception syndrome register (esr) 0 mci machine check ? instruction 0 instruction machine check did not occur. 1 instruction machine check occurred. 1:3 reserved 4 pil program exception ? illegal 0 illegal instruction error did not occur. 1 illegal instruction error occurred. 5 ppr program exception ? privileged 0 privileged instruction error did not occur. 1 privileged instruction error occurred. 6 ptr program exception ? trap 0 trap with successful compare did not occur. 1 trap with successful compare occurred. 7 reserved 8 dst data storage exception ? store fault 0 excepting instruction was not a store. 1 excepting instruction was a store (includes dcbi , dcbz , and dccci ). 9 diz data/instruction storage exception ? zone fault 0 excepting condition was not a zone fault. 1 excepting condition was a zone fault. 10:11 dlk data storage exception ? lock fault 00 no lock exception 01 dcbf unlock exception 10 icbi unlock exception 11 dcbz lock-out exception 12 pau program exception ? auxiliary processor unavailable 0 auxiliary processor unavailable exception did not occur. 1 auxiliary processor unavailable exception occurred. 13 reserved 14 pae program exception ? auxiliary processor enabled 0 auxiliary processor enabled exception did not occur. 1 auxiliary processor enabled exception occurred. 15 reserved 16 dsk data storage exception ? compressed 0 excepting instruction did not access compressed storage. 1 excepting instruction accessed compressed storage. 17:31 reserved 0456 7 mci pil ptr ppr 9 810 dst dlk diz 11 12 13 7 pau 13 14 16 15 31 17 pa e dsk section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-18 ? 2000 plx technology, inc. all rights reserved. evpr spr 0x3d6 see also section 11.7.3.4, ? exception vector prefix register (evpr), ? on page 11-17. register 29-13. exception vector prefix register (evpr) 0:15 exception vector prefix 16:31 reserved 015 31 16 section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-19 section 29 ? reg summary r0-r31 see also section 24.2.1, ? general purpose registers, ? on page 24-2. register 29-14. general purpose register (r0-r31) 0:31 general purpose register data section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-20 ? 2000 plx technology, inc. all rights reserved. iac1 spr 0x3f4 see also section 26.6.4, ? instruction address compare register (iac1), ? on page 26-8. register 29-15. instruction address compare register (iac1) 0:29 instruction address compare lword address omit two low-order bits of complete address. 30:31 reserved 0 29 30 31 section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-21 section 29 ? reg summary iccr spr 0x3fb see section 27.8, ? real-mode storage attribute control, ? on page 27-13. register 29-16. instruction cache cacheability register (iccr) 0 s0 0 noncacheable 1 cacheable 0x0000 0000 ? 0x07ff ffff 1 s1 0 noncacheable 1 cacheable 0x0800 0000 ? 0x0fff ffff 2 s2 0 noncacheable 1 cacheable 0x1000 0000 ? 0x17ff ffff 3 s3 0 noncacheable 1 cacheable 0x1800 0000 ? 0x1fff ffff 4 s4 0 noncacheable 1 cacheable 0x2000 0000 ? 0x27ff ffff 5 s5 0 noncacheable 1 cacheable 0x2800 0000 ? 0x2fff ffff 6 s6 0 noncacheable 1 cacheable 0x3000 0000 ? 0x37ff ffff 7 s7 0 noncacheable 1 cacheable 0x3800 0000 ? 0x3fff ffff 8 s8 0 noncacheable 1 cacheable 0x4000 0000 ? 0x47ff ffff 9 s9 0 noncacheable 1 cacheable 0x4800 0000 ? 0x4fff ffff 10 s10 0 noncacheable 1 cacheable 0x5000 0000 ? 0x57ff ffff 11 s11 0 noncacheable 1 cacheable 0x5800 0000 ? 0x5fff ffff 12 s12 0 noncacheable 1 cacheable 0x6000 0000 ? 0x67ff ffff 13 s13 0 noncacheable 1 cacheable 0x6800 0000 ? 0x6fff ffff 14 s14 0 noncacheable 1 cacheable 0x7000 0000 ? 0x77ff ffff 15 s15 0 noncacheable 1 cacheable 0x7800 0000 ? 0x7fff ffff 16 s16 0 noncacheable 1 cacheable 0x8000 0000 ? 0x87ff ffff 17 s17 0 noncacheable 1 cacheable 0x8800 0000 ? 0x8fff ffff s10 03478111213161720 31 s0 s12 s18 s1 s11 s13 21 12 56 910 1415 1819 s2 s3 s5 s7 s9 s4 s6 s8 s14 s15 s16 s17 s19 22 23 26 28 29 30 25 27 24 s20 s22 s24 s28 s26 s30 s21 s23 s25 s27 s29 s31 section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-22 ? 2000 plx technology, inc. all rights reserved. 18 s18 0 noncacheable 1 cacheable 0x9000 0000 ? 0x97ff ffff 19 s19 0 noncacheable 1 cacheable 0x9800 0000 ? 0x9fff ffff 20 s20 0 noncacheable 1 cacheable 0xa000 0000 ? 0xa7ff ffff 21 s21 0 noncacheable 1 cacheable 0xa800 0000 ? 0xafff ffff 22 s22 0 noncacheable 1 cacheable 0xb000 0000 ? 0xb7ff ffff 23 s23 0 noncacheable 1 cacheable 0xb800 0000 ? 0xbfff ffff 24 s24 0 noncacheable 1 cacheable 0xc000 0000 ? 0xc7ff ffff 25 s25 0 noncacheable 1 cacheable 0xc800 0000 ? 0xcfff ffff 26 s26 0 noncacheable 1 cacheable 0xd000 0000 ? 0xd7ff ffff 27 s27 0 noncacheable 1 cacheable 0xd800 0000 ? 0xdfff ffff 28 s28 0 noncacheable 1 cacheable 0xe000 0000 ? 0xe7ff ffff 29 s29 0 noncacheable 1 cacheable 0xe800 0000 ? 0xefff ffff 30 s30 0 noncacheable 1 cacheable 0xf000 0000 ? 0xf7ff ffff 31 s31 0 noncacheable 1 cacheable 0xf800 0000 ? 0xffff ffff register 29-16. instruction cache cacheability register (iccr) (continued) section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-23 section 29 ? reg summary icdbdr spr 0x3d3 read-only see also section 25.4, ? cache control and debugging features, ? on page 25-7. register 29-17. instruction cache debug data register (icdbdr) 0:31 instruction cache information see icread , page 28-69. register 29-18. icu tag information 0: m ? 1 tag cache tag see table 25-1, ? cache array size by core, ? on page 25-1 for information on the size of this variable-length field. m :24 reserved the size of this field depends on the size of the tag field. 25 lk cache line lock 0 unlocked 1 locked 26 reserved 27 v cache line valid 0 not valid 1 valid 28:30 reserved 31 lru least recently used (lru) 0 a-way lru 1 b-way lru section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-24 ? 2000 plx technology, inc. all rights reserved. lr spr 0x008 see also section 24.2.2.2, ? link register (lr), ? on page 24-4. register 29-19. link register (lr) 0:31 link registers contents if (lr) represents an instruction address, lr 0:31 should be zero. section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-25 section 29 ? reg summary msr spr 0x3b1 see also section 11.7.3.1, ? machine state register (msr), ? on page 11-13. register 29-20. machine state register (msr) 0:10 reserved 11 ape auxiliary processor exception enable 0 auxiliary processor exception disabled. 1 auxiliary processor exception enabled. 12 apa auxiliary processor available 0 auxiliary processor not available. 1 auxiliary processor available. 13 we wait state enable 0 the processor is not in the wait state. 1 the processor is in the wait state. if msr[we] = 1, the processor remains in the wait state until an exception is taken, a reset occurs, or an external debug tool clears we. this bit places the processor in a sleep mode. typical power in sleep mode with no other on-going operations is under 150 mw. 14 ce critical interrupt enable 0 critical interrupts are disabled. 1 critical interrupts are enabled. controls the critical interrupt input and watchdog timer first timeout interrupts. 15 ile interrupt little endian 0 interrupt handlers execute in big endian mode. 1 interrupt handlers execute in powerpc little endian mode. copied to msr(le) when an interrupt is taken. 16 ee external interrupt enable 0 asynchronous exceptions are disabled. 1 asynchronous exceptions are enabled. controls the non-critical external interrupt input, programmable interval timer, and fixed interval timer interrupts. 17 pr problem state 0 supervisor state (all instructions allowed) 1 problem state (some instructions not allowed) 18 reserved 19 me machine check enable 0 machine check exceptions are disabled 1 machine check exceptions are enabled. 20:21 reserved 22 de debug exception enable 0 debug exceptions are disabled. 1 debug exceptions are enabled. 23:25 reserved 26 ir instruction relocate 0 instruction address translation is disabled. 1 instruction address translation is enabled. if tie_cpummuen is 0, reading or writing this bit has no effect. 13 14 16 19 22 28 29 01215 17 18 20 21 23 27 30 31 we pr de ce ee me ile le 26 25 ir dr 28 11 apa ape 10 section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-26 ? 2000 plx technology, inc. all rights reserved. 27 dr data relocate 0 data address translation is disabled. 1 data address translation is enabled. if tie_cpummuen is 0, reading or writing this bit has no effect. 28:30 reserved 31 le little endian 0 processor executes in big endian mode. 1 processor executes in powerpc little endian mode. register 29-20. machine state register (msr) (continued) section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-27 section 29 ? reg summary pid see section 27.8, ? real-mode storage attribute control, ? on page 27-13. register 29-21. process id (pid) 0:23 reserved 24:31 process id 24 31 0 23 section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-28 ? 2000 plx technology, inc. all rights reserved. pit spr 0x3db see also section 11.7.18.2, ? programmable interval timer (pit), ? on page 11-32. register 29-22. programmable interval timer (pit) 0:31 programmed interval remaining number of clocks remaining until the pit event section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-29 section 29 ? reg summary pvr spr 0x11f read-only see also section 24.2.2.5, ? processor version register (pvr), ? on page 24-6. register 29-23. processor version register (pvr) 0:11 fam processor family. identifies a powerpc family, such as 4xx or 6xx. 0x002 for the 4xx family. 12:15 pcfn processor core function. identifies a specific processor core implementation. 2 for ppc401b2. 16:20 pcrv processor core revision. identifies a revision of the processor core defined by the pfn field. . 21:27 afn asic function. an assigned identifier for an asic containing a powerpc 400 series processor core. 28:31 arv asic revision. an assigned identifier for a revision of the asic defined by the afn field. 015162731 afn fam arv 11 12 pcfn pcrv 20 21 28 section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-30 ? 2000 plx technology, inc. all rights reserved. sgr spr 0x3b9 see section 27.8, ? real-mode storage attribute control, ? on page 27-13. register 29-24. storage guarded register (sgr) 0g00normal 1 guarded 0x0000 0000 ? 0x07ff ffff 1g10normal 1 guarded 0x0800 0000 ? 0x0fff ffff 2g20normal 1 guarded 0x1000 0000 ? 0x17ff ffff 3g30normal 1 guarded 0x1800 0000 ? 0x1fff ffff 4g40normal 1 guarded 0x2000 0000 ? 0x27ff ffff 5g50normal 1 guarded 0x2800 0000 ? 0x2fff ffff 6g60normal 1 guarded 0x3000 0000 ? 0x37ff ffff 7g70normal 1 guarded 0x3800 0000 ? 0x3fff ffff 8g80normal 1 guarded 0x4000 0000 ? 0x47ff ffff 9g90normal 1 guarded 0x4800 0000 ? 0x4fff ffff 10 g10 0 normal 1 guarded 0x5000 0000 ? 0x57ff ffff 11 g11 0 normal 1 guarded 0x5800 0000 ? 0x5fff ffff 12 g12 0 normal 1 guarded 0x6000 0000 ? 0x67ff ffff 13 g13 0 normal 1 guarded 0x6800 0000 ? 0x6fff ffff 14 g14 0 normal 1 guarded 0x7000 0000 ? 0x77ff ffff 15 g15 0 normal 1 guarded 0x7800 0000 ? 0x7fff ffff 16 g16 0 normal 1 guarded 0x8000 0000 ? 0x87ff ffff 17 g17 0 normal 1 guarded 0x8800 0000 ? 0x8fff ffff g10 03478111213161720 31 g0 g12 g18 g1 g11 g13 21 12 56 910 1415 1819 g2 g3 g5 g7 g9 g4 g6 g8 g14 g15 g16 g17 g19 22 23 26 28 29 30 25 27 24 g20 g22 g24 g28 g26 g30 g21 g23 g25 g27 g29 g31 section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-31 section 29 ? reg summary 18 g18 0 normal 1 guarded 0x9000 0000 ? 0x97ff ffff 19 g19 0 normal 1 guarded 0x9800 0000 ? 0x9fff ffff 20 g20 0 normal 1 guarded 0xa000 0000 ? 0xa7ff ffff 21 g21 0 normal 1 guarded 0xa800 0000 ? 0xafff ffff 22 g22 0 normal 1 guarded 0xb000 0000 ? 0xb7ff ffff 23 g23 0 normal 1 guarded 0xb800 0000 ? 0xbfff ffff 24 g24 0 normal 1 guarded 0xc000 0000 ? 0xc7ff ffff 25 g25 0 normal 1 guarded 0xc800 0000 ? 0xcfff ffff 26 g26 0 normal 1 guarded 0xd000 0000 ? 0xd7ff ffff 27 g27 0 normal 1 guarded 0xd800 0000 ? 0xdfff ffff 28 g28 0 normal 1 guarded 0xe000 0000 ? 0xe7ff ffff 29 g29 0 normal 1 guarded 0xe800 0000 ? 0xefff ffff 30 g30 0 normal 1 guarded 0xf000 0000 ? 0xf7ff ffff 31 g31 0 normal 1 guarded 0xf800 0000 ? 0xffff ffff register 29-24. storage guarded register (sgr) (continued) section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-32 ? 2000 plx technology, inc. all rights reserved. skr spr 0x3bc see section 27.8, ? real-mode storage attribute control, ? on page 27-13. register 29-25. storage compression register (skr) 0 k0 0 storage compression is off 1 storage compression is on 0x0000 0000 ? 0x07ff ffff 1 k1 0 storage compression is off 1 storage compression is on 0x0800 0000 ? 0x0fff ffff 2 k2 0 storage compression is off 1 storage compression is on 0x1000 0000 ? 0x17ff ffff 3 k3 0 storage compression is off 1 storage compression is on 0x1800 0000 ? 0x1fff ffff 4 k4 0 storage compression is off 1 storage compression is on 0x2000 0000 ? 0x27ff ffff 5 k5 0 storage compression is off 1 storage compression is on 0x2800 0000 ? 0x2fff ffff 6 k6 0 storage compression is off 1 storage compression is on 0x3000 0000 ? 0x37ff ffff 7 k7 0 storage compression is off 1 storage compression is on 0x3800 0000 ? 0x3fff ffff 8 k8 0 storage compression is off 1 storage compression is on 0x4000 0000 ? 0x47ff ffff 9 k9 0 storage compression is off 1 storage compression is on 0x4800 0000 ? 0x4fff ffff 10 k10 0 storage compression is off 1 storage compression is on 0x5000 0000 ? 0x57ff ffff 11 k11 0 storage compression is off 1 storage compression is on 0x5800 0000 ? 0x5fff ffff 12 k12 0 storage compression is off 1 storage compression is on 0x6000 0000 ? 0x67ff ffff 13 k13 0 storage compression is off 1 storage compression is on 0x6800 0000 ? 0x6fff ffff 14 k14 0 storage compression is off 1 storage compression is on 0x7000 0000 ? 0x77ff ffff 15 k15 0 storage compression is off 1 storage compression is on 0x7800 0000 ? 0x7fff ffff 16 k16 0 storage compression is off 1 storage compression is on 0x8000 0000 ? 0x87ff ffff 17 k17 0 storage compression is off 1 storage compression is on 0x8800 0000 ? 0x8fff ffff k10 03478111213161720 31 k0 k12 k18 k1 k11 k13 21 12 56 910 1415 1819 k2 k3 k5 k7 k9 k4 k6 k8 k14 k15 k16 k17 k19 22 23 26 28 29 30 25 27 24 k20 k22 k24 k28 k26 k30 k21 k23 k25 k27 k29 k31 section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-33 section 29 ? reg summary 18 k18 0 storage compression is off 1 storage compression is on 0x9000 0000 ? 0x97ff ffff 19 k19 0 storage compression is off 1 storage compression is on 0x9800 0000 ? 0x9fff ffff 20 k20 0 storage compression is off 1 storage compression is on 0xa000 0000 ? 0xa7ff ffff 21 k21 0 storage compression is off 1 storage compression is on 0xa800 0000 ? 0xafff ffff 22 k22 0 storage compression is off 1 storage compression is on 0xb000 0000 ? 0xb7ff ffff 23 k23 0 storage compression is off 1 storage compression is on 0xb800 0000 ? 0xbfff ffff 24 k24 0 storage compression is off 1 storage compression is on 0xc000 0000 ? 0xc7ff ffff 25 k25 0 storage compression is off 1 storage compression is on 0xc800 0000 ? 0xcfff ffff 26 k26 0 storage compression is off 1 storage compression is on 0xd000 0000 ? 0xd7ff ffff 27 k27 0 storage compression is off 1 storage compression is on 0xd800 0000 ? 0xdfff ffff 28 k28 0 storage compression is off 1 storage compression is on 0xe000 0000 ? 0xe7ff ffff 29 k29 0 storage compression is off 1 storage compression is on 0xe800 0000 ? 0xefff ffff 30 k30 0 storage compression is off 1 storage compression is on 0xf000 0000 ? 0xf7ff ffff 31 k31 0 storage compression is off 1 storage compression is on 0xf800 0000 ? 0xffff ffff register 29-25. storage compression register (skr) (continued) section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-34 ? 2000 plx technology, inc. all rights reserved. sler spr 0x3bb see section 27.8, ? real-mode storage attribute control, ? on page 27-13. register 29-26. storage little-endian register (sler) 0 s0 0 big endian or powerpc little endian 1 true little endian 0x0000 0000 ? 0x07ff ffff 1 s1 0 big endian or powerpc little endian 1 true little endian 0x0800 0000 ? 0x0fff ffff 2 s2 0 big endian or powerpc little endian 1 true little endian 0x1000 0000 ? 0x17ff ffff 3 s3 0 big endian or powerpc little endian 1 true little endian 0x1800 0000 ? 0x1fff ffff 4 s4 0 big endian or powerpc little endian 1 true little endian 0x2000 0000 ? 0x27ff ffff 5 s5 0 big endian or powerpc little endian 1 true little endian 0x2800 0000 ? 0x2fff ffff 6 s6 0 big endian or powerpc little endian 1 true little endian 0x3000 0000 ? 0x37ff ffff 7 s7 0 big endian or powerpc little endian 1 true little endian 0x3800 0000 ? 0x3fff ffff 8 s8 0 big endian or powerpc little endian 1 true little endian 0x4000 0000 ? 0x47ff ffff 9 s9 0 big endian or powerpc little endian 1 true little endian 0x4800 0000 ? 0x4fff ffff 10 s10 0 big endian or powerpc little endian 1 true little endian 0x5000 0000 ? 0x57ff ffff 11 s11 0 big endian or powerpc little endian 1 true little endian 0x5800 0000 ? 0x5fff ffff 12 s12 0 big endian or powerpc little endian 1 true little endian 0x6000 0000 ? 0x67ff ffff 13 s13 0 big endian or powerpc little endian 1 true little endian 0x6800 0000 ? 0x6fff ffff 14 s14 0 big endian or powerpc little endian 1 true little endian 0x7000 0000 ? 0x77ff ffff 15 s15 0 big endian or powerpc little endian 1 true little endian 0x7800 0000 ? 0x7fff ffff 16 s16 0 big endian or powerpc little endian 1 true little endian 0x8000 0000 ? 0x87ff ffff 17 s17 0 big endian or powerpc little endian 1 true little endian 0x8800 0000 ? 0x8fff ffff s10 03478111213161720 31 s0 s12 s18 s1 s11 s13 21 12 56 910 1415 1819 s2 s3 s5 s7 s9 s4 s6 s8 s14 s15 s16 s17 s19 22 23 26 28 29 30 25 27 24 s20 s22 s24 s28 s26 s30 s21 s23 s25 s27 s29 s31 section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-35 section 29 ? reg summary 18 s18 0 big endian or powerpc little endian 1 true little endian 0x9000 0000 ? 0x97ff ffff 19 s19 0 big endian or powerpc little endian 1 true little endian 0x9800 0000 ? 0x9fff ffff 20 s20 0 big endian or powerpc little endian 1 true little endian 0xa000 0000 ? 0xa7ff ffff 21 s21 0 big endian or powerpc little endian 1 true little endian 0xa800 0000 ? 0xafff ffff 22 s22 0 big endian or powerpc little endian 1 true little endian 0xb000 0000 ? 0xb7ff ffff 23 s23 0 big endian or powerpc little endian 1 true little endian 0xb800 0000 ? 0xbfff ffff 24 s24 0 big endian or powerpc little endian 1 true little endian 0xc000 0000 ? 0xc7ff ffff 25 s25 0 big endian or powerpc little endian 1 true little endian 0xc800 0000 ? 0xcfff ffff 26 s26 0 big endian or powerpc little endian 1 true little endian 0xd000 0000 ? 0xd7ff ffff 27 s27 0 big endian or powerpc little endian 1 true little endian 0xd800 0000 ? 0xdfff ffff 28 s28 0 big endian or powerpc little endian 1 true little endian 0xe000 0000 ? 0xe7ff ffff 29 s29 0 big endian or powerpc little endian 1 true little endian 0xe800 0000 ? 0xefff ffff 30 s30 0 big endian or powerpc little endian 1 true little endian 0xf000 0000 ? 0xf7ff ffff 31 s31 0 big endian or powerpc little endian 1 true little endian 0xf800 0000 ? 0xffff ffff register 29-26. storage little-endian register (sler) (continued) section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-36 ? 2000 plx technology, inc. all rights reserved. sprg0-sprg3 spr 0x110-0x113 see also section 24.2.2.4, ? special purpose register general (sprg0-sprg3), ? on page 24-6. register 29-27. special purpose register general (sprg0-sprg3) 0-31 general data privileged user-specified; no hardware usage. section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-37 section 29 ? reg summary srr0 spr 0x01a see also section 11.7.3.2, ? save/restore registers 0 and 1 (srr0 ? srr1), ? on page 11-15. register 29-28. save/restore register 0 (srr0) 0:29 srr0 receives an instruction address when a non-critical interrupt is taken; the program counter is restored from srr0 when rfi executes. 30:31 reserved 0 29 30 31 section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-38 ? 2000 plx technology, inc. all rights reserved. srr1 spr 0x01b see also section 11.7.3.2, ? save/restore registers 0 and 1 (srr0 ? srr1), ? on page 11-15. register 29-29. save/restore register 1 (srr1) 0:31 srr1 receives a copy of the msr when a non-critical interrupt is taken; the msr is restored from srr1 when rfi executes. 13 14 16 19 22 28 29 01215 17 18 20 21 23 27 30 31 we pr de ce ee me ile le 26 25 ir dr 28 11 apa ape 10 section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-39 section 29 ? reg summary srr2 spr 0x3de see also section 11.7.3.3, ? save/restore registers 2 and 3 (srr2 ? srr3), ? on page 11-15. register 29-30. save/restore register 2 (srr2) 0:29 srr2 receives an instruction address when a critical interrupt is taken; the program counter is restored from srr2 when rfci executes. 30:31 reserved 0 29 30 31 section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-40 ? 2000 plx technology, inc. all rights reserved. srr1 spr 0x3df see also section 11.7.3.3, ? save/restore registers 2 and 3 (srr2 ? srr3), ? on page 11-15. register 29-31. save/restore register 3 (srr3) 0:31 srr3 receives a copy of the msr when a critical interrupt is taken; the msr is restored from srr3 when rfci executes. 13 14 16 19 22 28 29 01215 17 18 20 21 23 27 30 31 we pr de ce ee me ile le 26 25 ir dr 28 11 apa ape 10 section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-41 section 29 ? reg summary tbhi spr 0x3dc see also section 11.7.18.1, ? time base, ? on page 11-30. register 29-32. time base high register (tbhi) 0:31 time high current count, high-order. section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-42 ? 2000 plx technology, inc. all rights reserved. tbhu spr 0x3cc read-only see also section 11.7.18.1, ? time base, ? on page 11-30. register 29-33. time base high user-mode (tbhu) 0:31 time high current count, high-order. note: tbhu is a read-only access vehicle to the time base register tbhi. it is not possible for the contents of tbhu and tbhi to differ. section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-43 section 29 ? reg summary tblo spr 0x3dd see also section 11.7.18.1, ? time base, ? on page 11-30. register 29-34. time base low register (tblo) 0:31 time low current count, low-order. section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-44 ? 2000 plx technology, inc. all rights reserved. tblu spr 0x3cd read-only see also section 11.7.18.1, ? time base, ? on page 11-30. register 29-35. time base low user-mode (tblu) 0:31 time low current count, low-order. note: tblu is a read-only access vehicle to the time base register tblo. it is not possible for the contents of tblu and tblo to differ. section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-45 section 29 ? reg summary tcr spr 0x3da see section 11.7.18.6, ? timer control register (tcr), ? on page 11-36. register 29-36. timer control register (tcr) 0:1 wp watchdog period 00 2 17 clocks 01 2 21 clocks 10 2 25 clocks 11 2 29 clocks 2:3 wrc watchdog reset control 00 no watchdog reset occurs. 01 core reset is forced by the watchdog. 10 chip reset is forced by the watchdog. 11 system reset is forced by the watchdog. tcr[wrc] resets to 00. this field can be set by software, but cannot be cleared by software, except by a software-induced reset. 4 wie watchdog interrupt enable 0 disable wdt interrupt. 1 enable wdt interrupt. 5 pie pit interrupt enable 0 disable pit interrupt. 1 enable pit interrupt. 6:7 fp fit period 00 2 9 clocks 01 2 13 clocks 10 2 17 clocks 11 2 21 clocks 8 fie fit interrupt enable 0 disable fit interrupt. 1 enable fit interrupt. 9 are auto reload enable 0 disable auto reload. 1 enable auto reload. disables on reset. 10:31 reserved 012345678 9 31 wp wie fp fie pie wrc 10 are section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-46 ? 2000 plx technology, inc. all rights reserved. tsr spr 0x3d8 read/clear see section 11.7.18.5, ? timer status register (tsr), ? on page 11-35. register 29-37. timer status register (tsr) 0 enw enable next watchdog 0 action on next watchdog event is to set tsr[0]. 1 action on next watchdog event is governed by tsr[1]. see section 11.7.18.4, ? watchdog timer, ? on page 11-33. 1 wis watchdog interrupt status 0 no watchdog interrupt is pending. 1 watchdog interrupt is pending. 2:3 wrs watchdog reset status 00 no watchdog reset has occurred. 01 core reset was forced by the watchdog. 10 chip reset was forced by the watchdog. 11 system reset was forced by the watchdog. 4 pis pit interrupt status 0 no pit interrupt is pending. 1 pit interrupt is pending. 5 fis fit interrupt status 0 no fit interrupt is pending. 1 fit interrupt is pending. 6:31 reserved 012345 31 enw wrs fis pis wis 6 section 29 alphabetical register listing iop 480 cpu register summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. 29-47 section 29 ? reg summary xer spr 0x001 see section 24.2.2.3, ? fixed point exception register (xer), ? on page 24-5. register 29-38. fixed point exception register (xer) 0 so summary overflow 0 no overflow has occurred. 1 overflow has occurred. can be set by mtspr or using arithmetic instructions with the ? oe ? option (see table 24-2, ? xer-updating arithmetic instructions, ? on page 24-5); can be reset by mtspr or by mcrxr . 1ovoverflow 0 no overflow has occurred. 0 overflow has occurred. can be set by mtspr or arithmetic instructions with the ? oe ? option (see table 24-2, ? xer-updating arithmetic instructions, ? on page 24-5); can be reset by mtspr , by mcrxr , or by arithmetic instructions with the ? oe ? option. 2 ca carry 0 carry has not occurred. 1 carry has occurred. can be set by mtspr or arithmetic instructions that update the ca field (see table 24-2, ? xer-updating arithmetic instructions, ? on page 24-5); can be reset by mtspr , by mcrxr , or by arithmetic instructions that update the ca field. 3:24 reserved 25:31 tbc transfer byte count used by lswx and stswx ; written by mtspr 012 25 31 3 24 so ca tbc ov section 29 iop 480 cpu register summary alphabetical register listing iop 480 data book r2.0 29-48 ? 2000 plx technology, inc. all rights reserved. zpr spr 0x3b0 see section 27.7.1.4, ? zone protection, ? on page 27-10. register 29-39. zone protection register (zpr) 0:1 z0 tlb page access control for all pages in this zone; tlb_entry[ex, wr] are bits that translate an effective address and pid. in the problem state (msr[pr] = 1): 00 no access 01 access controlled by ex and wr 10 access controlled by ex and wr 11 accessed as if ex and wr are set in the supervisor state (msr[pr] = 0): 00 access controlled by ex and wr 01 access controlled by ex and wr 10 access as if ex and wr are set 11 accessed as if ex and wr are set 2:3 z1 see the description of z0. 4:5 z2 see the description of z0. 6:7 z3 see the description of z0. 8:9 z4 see the description of z0. 10:11 z5 see the description of z0. 12:13 z6 see the description of z0. 14:15 z7 see the description of z0. 16:17 z8 see the description of z0. 18:19 z9 see the description of z0. 20:21 z10 see the description of z0. 22:23 z11 see the description of z0. 24:25 z12 see the description of z0. 26:27 z13 see the description of z0. 28:29 z14 see the description of z0. 30:31 z15 see the description of z0. z10 03478111213161720 31 z0 z12 z1 z11 z13 21 12 56 910 1415 1819 z2 z3 z5 z7 z9 z4 z6 z8 z14 z15 22 23 26 28 29 30 25 27 24 iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-1 appendix a?cpu instr sum a iop 480 cpu instruction summary this appendix contains iop 480 cpu instructions summarized alphabetically and by opcode. ? on page a-1, section a.1 lists all iop 480 cpu mnemonics, including extended mnemonics, alphabetically. a short functional description is included for each mnemonic. on page a-30, section a.2 lists all iop 480 cpu instructions, sorted by primary and secondary opcodes. extended mnemonics are not included in the opcode list. on page a-36, section a.3 illustrates iop 480 cpu instruction forms (allowed arrangements of fields within instructions). a.1 instruction set and extended mnemonics? alphabetical table a-1 summarizes iop 480 cpu instruction set, including required extended mnemonics. all mnemonics are listed alphabetically, without regard to whether the mnemonic is realized in hardware or software. when an instruction supports multiple hardware mnemonics (for example, b , ba , bl , bla are all forms of b ), the instruction is alphabetized under the root form. the hardware instructions are described in detail in section 28, ?iop 480 cpu instruction set,? which is also alphabetized under the root form. section 28 also describes the instruction operands and notation. note: the following applies for every branch conditional mnemonic: bit 4 of the bo field provides a hint about the most likely outcome of a conditional branch (see section 24.6.5, ?branch prediction,? on page 24-23 for a full discussion of branch prediction). assemblers should set bo 4 = 0 unless a specific reason exists otherwise. in the bo field values specified in the table below, bo 4 = 0 has always been assumed. the assembler must allow the programmer to specify branch prediction. to do this, the assembler supports a suffix to every conditional branch mnemonic, as follows: + predict branch to be taken. ? as specific examples, bc also could be coded as bc+ or bc ? , and bne also could be coded bne+ or bne ? . these alternate codings set bo 4 = 1 only if the requested prediction differs from the standard prediction (refer to section 24.6.5, ?branch prediction,? on page 24-23). table a-1. iop 480 cpu instruction syntax summary mnemonic operands function other registers changed page add rt, ra, rb add (ra) to (rb). place result in rt. 28-7 add. cr[cr0] addo xer[so, ov] addo. cr[cr0] xer[so, ov] addc rt, ra, rb add (ra) to (rb). place result in rt. place carry-out in xer[ca]. 28-7 addc. cr[cr0] addco xer[so, ov] addco. cr[cr0] xer[so, ov] appendix a iop 480 cpu instruction summary instruction set and extended mnemonics?alphabetical iop 480 data book r2.0 a-2 ? 2000 plx technology, inc. all rights reserved. adde rt, ra, rb add xer[ca], (ra), (rb). place result in rt. place carry-out in xer[ca]. 28-9 adde. cr[cr0] addeo xer[so, ov] addeo. cr[cr0] xer[so, ov] addi rt, ra, im add exts(im) to (ra|0). place result in rt. 28-10 addic rt, ra, im add exts(im) to (ra|0). place result in rt. place carry-out in xer[ca]. 28-11 addic. rt, ra, im add exts(im) to (ra|0). place result in rt. place carry-out in xer[ca]. cr[cr0] 28-12 addis rt, ra, im add (im || 16 0) to (ra|0). place result in rt. 28-13 addme rt, ra add xer[ca], (ra), (-1). place result in rt. place carry-out in xer[ca]. 28-14 addme. cr[cr0] addmeo xer[so, ov] addmeo. cr[cr0] xer[so, ov] addze rt, ra add xer[ca] to (ra). place result in rt. place carry-out in xer[ca]. 28-15 addze. cr[cr0] addzeo xer[so, ov] addzeo. cr[cr0] xer[so, ov] and ra, rs, rb and (rs) with (rb). place result in ra. 28-16 and. cr[cr0] andc ra, rs, rb and (rs) with ? (rb). place result in ra. 28-17 andc. cr[cr0] andi. ra, rs, im and (rs) with ( 16 0 || im). place result in ra. cr[cr0] 28-18 andis. ra, rs, im and (rs) with (im || 16 0). place result in ra. cr[cr0] 28-19 table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a instruction set and extended mnemonics ? alphabetical iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-3 appendix a ? cpu instr sum b target branch unconditional relative. li (target ? cia) 6:29 nia cia + exts(li || 2 0) 28-20 ba branch unconditional absolute. li target 6:29 nia exts(li || 2 0) bl branch unconditional relative. li (target ? cia) 6:29 nia cia + exts(li || 2 0) (lr) cia + 4. bla branch unconditional absolute. li target 6:29 nia exts(li || 2 0) (lr) cia + 4. bc bo, bi, target branch conditional relative. bd (target ? cia) 16:29 nia cia + exts(bd || 2 0) ctr if bo 2 = 0. 28-21 bca branch conditional absolute. bd target 16:29 nia exts(bd || 2 0) ctr if bo 2 = 0. bcl branch conditional relative. bd (target ? cia) 16:29 nia cia + exts(bd || 2 0) ctr if bo 2 = 0. (lr) cia + 4. bcla branch conditional absolute. bd target 16:29 nia exts(bd || 2 0) ctr if bo 2 = 0. (lr) cia + 4. bcctr bo, bi branch conditional to address in ctr. using (ctr) at exit from instruction, nia ctr 0:29 || 2 0. ctr if bo 2 = 0. 28-26 bcctrl ctr if bo 2 = 0. (lr) cia + 4. bclr bo, bi branch conditional to address in lr. using (lr) at entry to instruction, nia lr 0:29 || 2 0. ctr if bo 2 = 0. 28-29 bclrl ctr if bo 2 = 0. (lr) cia + 4. bctr branch unconditionally, to address in ctr. extended mnemonic for bcctr 20,0 28-26 bctrl extended mnemonic for bcctrl 20,0 (lr) cia + 4. bdnz target decrement ctr. branch if ctr 0. extended mnemonic for bc 16,0,target 28-21 bdnza extended mnemonic for bca 16,0,target bdnzl extended mnemonic for bcl 16,0,target (lr) cia + 4. bdnzla extended mnemonic for bcla 16,0,target (lr) cia + 4. table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a iop 480 cpu instruction summary instruction set and extended mnemonics ? alphabetical iop 480 data book r2.0 a-4 ? 2000 plx technology, inc. all rights reserved. bdnzlr decrement ctr. branch if ctr 0, to address in lr. extended mnemonic for bclr 16,0 28-29 bdnzlrl extended mnemonic for bclrl 16,0 (lr) cia + 4. bdnzf cr_bit, target decrement ctr. branch if ctr 0 and cr cr_bit = 0. extended mnemonic for bc 0,cr_bit,target 28-21 bdnzfa extended mnemonic for bca 0,cr_bit,target bdnzfl extended mnemonic for bcl 0,cr_bit,target (lr) cia + 4. bdnzfla extended mnemonic for bcla 0,cr_bit,target (lr) cia + 4. bdnzflr cr_bit decrement ctr. branch if ctr 0 and cr cr_bit = 0, to address in lr. extended mnemonic for bclr 0,cr_bit 28-29 bdnzflrl extended mnemonic for bclrl 0,cr_bit (lr) cia + 4. bdnzt cr_bit, target decrement ctr. branch if ctr 0 and cr cr_bit = 1. extended mnemonic for bc 8,cr_bit,target 28-21 bdnzta extended mnemonic for bca 8,cr_bit,target bdnztl extended mnemonic for bcl 8,cr_bit,target (lr) cia + 4. bdnztla extended mnemonic for bcla 8,cr_bit,target (lr) cia + 4. bdnztlr cr_bit decrement ctr. branch if ctr 0 and cr cr_bit = 1, to address in lr. extended mnemonic for bclr 8,cr_bit 28-29 bdnztlrl extended mnemonic for bclrl 8,cr_bit (lr) cia + 4. table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a instruction set and extended mnemonics ? alphabetical iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-5 appendix a ? cpu instr sum bdz target decrement ctr. branch if ctr = 0. extended mnemonic for bc 18,0,target 28-21 bdza extended mnemonic for bca 18,0,target bdzl extended mnemonic for bcl 18,0,target (lr) cia + 4. bdzla extended mnemonic for bcla 18,0,target (lr) cia + 4. bdzlr decrement ctr. branch if ctr = 0, to address in lr. extended mnemonic for bclr 18,0 28-29 bdzlrl extended mnemonic for bclrl 18,0 (lr) cia + 4. bdzf cr_bit, target decrement ctr. branch if ctr = 0 and cr cr_bit = 0. extended mnemonic for bc 2,cr_bit,target 28-21 bdzfa extended mnemonic for bca 2,cr_bit,target bdzfl extended mnemonic for bcl 2,cr_bit,target (lr) cia + 4. bdzfla extended mnemonic for bcla 2,cr_bit,target (lr) cia + 4. bdzflr cr_bit decrement ctr. branch if ctr = 0 and cr cr_bit = 0 to address in lr. extended mnemonic for bclr 2,cr_bit 28-29 bdzflrl extended mnemonic for bclrl 2,cr_bit (lr) cia + 4. bdzt cr_bit, target decrement ctr. branch if ctr = 0 and cr cr_bit = 1. extended mnemonic for bc 10,cr_bit,target 28-21 bdzta extended mnemonic for bca 10,cr_bit,target bdztl extended mnemonic for bcl 10,cr_bit,target (lr) cia + 4. bdztla extended mnemonic for bcla 10,cr_bit,target (lr) cia + 4. table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a iop 480 cpu instruction summary instruction set and extended mnemonics ? alphabetical iop 480 data book r2.0 a-6 ? 2000 plx technology, inc. all rights reserved. bdztlr cr_bit decrement ctr. branch if ctr = 0 and cr cr_bit = 1, to address in lr. extended mnemonic for bclr 10,cr_bit 28-29 bdztlrl extended mnemonic for bclrl 10,cr_bit (lr) cia + 4. beq [cr_field], target branch if equal. use cr0 if cr_field is omitted. extended mnemonic for bc 12,4 ? cr_field+2,target 28-21 beqa extended mnemonic for bca 12,4 ? cr_field+2,target beql extended mnemonic for bcl 12,4 ? cr_field+2,target (lr) cia + 4. beqla extended mnemonic for bcla 12,4 ? cr_field+2,target (lr) cia + 4. beqctr [cr_field] branch if equal, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 12,4 ? cr_field+2 28-26 beqctrl extended mnemonic for bcctrl 12,4 ? cr_field+2 (lr) cia + 4. beqlr [cr_field] branch if equal, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 12,4 ? cr_field+2 28-29 beqlrl extended mnemonic for bclrl 12,4 ? cr_field+2 (lr) cia + 4. bf cr_bit, target branch if cr cr_bit = 0. extended mnemonic for bc 4,cr_bit,target 28-21 bfa extended mnemonic for bca 4,cr_bit,target bfl extended mnemonic for bcl 4,cr_bit,target (lr) cia + 4. bfla extended mnemonic for bcla 4,cr_bit,target (lr) cia + 4. bfctr cr_bit branch if cr cr_bit = 0, to address in ctr. extended mnemonic for bcctr 4,cr_bit 28-26 bfctrl extended mnemonic for bcctrl 4,cr_bit (lr) cia + 4. table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a instruction set and extended mnemonics ? alphabetical iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-7 appendix a ? cpu instr sum bflr cr_bit branch if cr cr_bit = 0, to address in lr. extended mnemonic for bclr 4,cr_bit 28-29 bflrl extended mnemonic for bclrl 4,cr_bit (lr) cia + 4. bge [cr_field], target branch if greater than or equal. use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+0,target 28-21 bgea extended mnemonic for bca 4,4 ? cr_field+0,target bgel extended mnemonic for bcl 4,4 ? cr_field+0,target (lr) cia + 4. bgela extended mnemonic for bcla 4,4 ? cr_field+0,target (lr) cia + 4. bgectr [cr_field] branch if greater than or equal, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+0 28-26 bgectrl extended mnemonic for bcctrl 4,4 ? cr_field+0 (lr) cia + 4. bgelr [cr_field] branch if greater than or equal, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+0 28-29 bgelrl extended mnemonic for bclrl 4,4 ? cr_field+0 (lr) cia + 4. bgt [cr_field], target branch if greater than. use cr0 if cr_field is omitted. extended mnemonic for bc 12,4 ? cr_field+1,target 28-21 bgta extended mnemonic for bca 12,4 ? cr_field+1,target bgtl extended mnemonic for bcl 12,4 ? cr_field+1,target (lr) cia + 4. bgtla extended mnemonic for bcla 12,4 ? cr_field+1,target (lr) cia + 4. bgtctr [cr_field] branch if greater than, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 12,4 ? cr_field+1 28-26 bgtctrl extended mnemonic for bcctrl 12,4 ? cr_field+1 (lr) cia + 4. table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a iop 480 cpu instruction summary instruction set and extended mnemonics ? alphabetical iop 480 data book r2.0 a-8 ? 2000 plx technology, inc. all rights reserved. bgtlr [cr_field] branch if greater than, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 12,4 ? cr_field+1 28-29 bgtlrl extended mnemonic for bclrl 12,4 ? cr_field+1 (lr) cia + 4. ble [cr_field], target branch if less than or equal. use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+1,target 28-21 blea extended mnemonic for bca 4,4 ? cr_field+1,target blel extended mnemonic for bcl 4,4 ? cr_field+1,target (lr) cia + 4. blela extended mnemonic for bcla 4,4 ? cr_field+1,target (lr) cia + 4. blectr [cr_field] branch if less than or equal, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+1 28-26 blectrl extended mnemonic for bcctrl 4,4 ? cr_field+1 (lr) cia + 4. blelr [cr_field] branch if less than or equal, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+1 28-29 blelrl extended mnemonic for bclrl 4,4 ? cr_field+1 (lr) cia + 4. blr branch unconditionally, to address in lr. extended mnemonic for bclr 20,0 28-29 blrl extended mnemonic for bclrl 20,0 (lr) cia + 4. blt [cr_field], target branch if less than. use cr0 if cr_field is omitted. extended mnemonic for bc 12,4 ? cr_field+0,target 28-21 blta extended mnemonic for bca 12,4 ? cr_field+0,target bltl extended mnemonic for bcl 12,4 ? cr_field+0,target (lr) cia + 4. bltla extended mnemonic for bcla 12,4 ? cr_field+0,target (lr) cia + 4. table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a instruction set and extended mnemonics ? alphabetical iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-9 appendix a ? cpu instr sum bltctr [cr_field] branch if less than, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 12,4 ? cr_field+0 28-26 bltctrl extended mnemonic for bcctrl 12,4 ? cr_field+0 (lr) cia + 4. bltlr [cr_field] branch if less than, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 12,4 ? cr_field+0 28-29 bltlrl extended mnemonic for bclrl 12,4 ? cr_field+0 (lr) cia + 4. bne [cr_field], target branch if not equal. use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+2,target 28-21 bnea extended mnemonic for bca 4,4 ? cr_field+2,target bnel extended mnemonic for bcl 4,4 ? cr_field+2,target (lr) cia + 4. bnela extended mnemonic for bcla 4,4 ? cr_field+2,target (lr) cia + 4. bnectr [cr_field] branch if not equal, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+2 28-26 bnectrl extended mnemonic for bcctrl 4,4 ? cr_field+2 (lr) cia + 4. bnelr [cr_field] branch if not equal, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+2 28-29 bnelrl extended mnemonic for bclrl 4,4 ? cr_field+2 (lr) cia + 4. bng [cr_field], target branch if not greater than. use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+1,target 28-21 bnga extended mnemonic for bca 4,4 ? cr_field+1,target bngl extended mnemonic for bcl 4,4 ? cr_field+1,target (lr) cia + 4. bngla extended mnemonic for bcla 4,4 ? cr_field+1,target (lr) cia + 4. table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a iop 480 cpu instruction summary instruction set and extended mnemonics ? alphabetical iop 480 data book r2.0 a-10 ? 2000 plx technology, inc. all rights reserved. bngctr [cr_field] branch if not greater than, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+1 28-26 bngctrl extended mnemonic for bcctrl 4,4 ? cr_field+1 (lr) cia + 4. bnglr [cr_field] branch if not greater than, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+1 28-29 bnglrl extended mnemonic for bclrl 4,4 ? cr_field+1 (lr) cia + 4. bnl [cr_field], target branch if not less than. use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+0,target 28-21 bnla extended mnemonic for bca 4,4 ? cr_field+0,target bnll extended mnemonic for bcl 4,4 ? cr_field+0,target (lr) cia + 4. bnlla extended mnemonic for bcla 4,4 ? cr_field+0,target (lr) cia + 4. bnlctr [cr_field] branch if not less than, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+0 28-26 bnlctrl extended mnemonic for bcctrl 4,4 ? cr_field+0 (lr) cia + 4. bnllr [cr_field] branch if not less than, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+0 28-29 bnllrl extended mnemonic for bclrl 4,4 ? cr_field+0 (lr) cia + 4. bns [cr_field], target branch if not summary overflow. use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+3,target 28-21 bnsa extended mnemonic for bca 4,4 ? cr_field+3,target bnsl extended mnemonic for bcl 4,4 ? cr_field+3,target (lr) cia + 4. bnsla extended mnemonic for bcla 4,4 ? cr_field+3,target (lr) cia + 4. table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a instruction set and extended mnemonics ? alphabetical iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-11 appendix a ? cpu instr sum bnsctr [cr_field] branch if not summary overflow, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+3 28-26 bnsctrl extended mnemonic for bcctrl 4,4 ? cr_field+3 (lr) cia + 4. bnslr [cr_field] branch if not summary overflow, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+3 28-29 bnslrl extended mnemonic for bclrl 4,4 ? cr_field+3 (lr) cia + 4. bnu [cr_field], target branch if not unordered. use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+3,target 28-21 bnua extended mnemonic for bca 4,4 ? cr_field+3,target bnul extended mnemonic for bcl 4,4 ? cr_field+3,target (lr) cia + 4. bnula extended mnemonic for bcla 4,4 ? cr_field+3,target (lr) cia + 4. bnuctr [cr_field] branch if not unordered, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+3 28-26 bnuctrl extended mnemonic for bcctrl 4,4 ? cr_field+3 (lr) cia + 4. bnulr [cr_field] branch if not unordered, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+3 28-29 bnulrl extended mnemonic for bclrl 4,4 ? cr_field+3 (lr) cia + 4. bso [cr_field], target branch if summary overflow. use cr0 if cr_field is omitted. extended mnemonic for bc 12,4 ? cr_field+3,target 28-21 bsoa extended mnemonic for bca 12,4 ? cr_field+3,target bsol extended mnemonic for bcl 12,4 ? cr_field+3,target (lr) cia + 4. bsola extended mnemonic for bcla 12,4 ? cr_field+3,target (lr) cia + 4. table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a iop 480 cpu instruction summary instruction set and extended mnemonics ? alphabetical iop 480 data book r2.0 a-12 ? 2000 plx technology, inc. all rights reserved. bsoctr [cr_field] branch if summary overflow, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 12,4 ? cr_field+3 28-26 bsoctrl extended mnemonic for bcctrl 12,4 ? cr_field+3 (lr) cia + 4. bsolr [cr_field] branch if summary overflow, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 12,4 ? cr_field+3 28-29 bsolrl extended mnemonic for bclrl 12,4 ? cr_field+3 (lr) cia + 4. bt cr_bit, target branch if cr cr_bit = 1. extended mnemonic for bc 12,cr_bit,target 28-21 bta extended mnemonic for bca 12,cr_bit,target btl extended mnemonic for bcl 12,cr_bit,target (lr) cia + 4. btla extended mnemonic for bcla 12,cr_bit,target (lr) cia + 4. btctr cr_bit branch if cr cr_bit = 1, to address in ctr. extended mnemonic for bcctr 12,cr_bit 28-26 btctrl extended mnemonic for bcctrl 12,cr_bit (lr) cia + 4. btlr cr_bit branch if cr cr_bit = 1, to address in lr. extended mnemonic for bclr 12,cr_bit 28-29 btlrl extended mnemonic for bclrl 12,cr_bit (lr) cia + 4. bun [cr_field], target branch if unordered. use cr0 if cr_field is omitted. extended mnemonic for bc 12,4 ? cr_field+3,target 28-21 buna extended mnemonic for bca 12,4 ? cr_field+3,target bunl extended mnemonic for bcl 12,4 ? cr_field+3,target (lr) cia + 4. bunla extended mnemonic for bcla 12,4 ? cr_field+3,target (lr) cia + 4. table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a instruction set and extended mnemonics ? alphabetical iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-13 appendix a ? cpu instr sum bunctr [cr_field] branch if unordered, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 12,4 ? cr_field+3 28-26 bunctrl extended mnemonic for bcctrl 12,4 ? cr_field+3 (lr) cia + 4. bunlr [cr_field] branch if unordered, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 12,4 ? cr_field+3 28-29 bunlrl extended mnemonic for bclrl 12,4 ? cr_field+3 (lr) cia + 4. clrlwi ra, rs, n clear left immediate. (n < 32) (ra) 0:n ? 1 n 0 extended mnemonic for rlwinm ra,rs,0,n,31 28-122 clrlwi. extended mnemonic for rlwinm. ra,rs,0,n,31 cr[cr0] clrlslwi ra, rs, b, n clear left and shift left immediate. (n b < 32) (ra) b ? n:31 ? n (rs) b:31 (ra) 32 ? n:31 n 0 (ra) 0:b ? n ? 1 b ? n 0 extended mnemonic for rlwinm ra,rs,n,b ? n,31 ? n 28-122 clrlslwi. extended mnemonic for rlwinm. ra,rs,n,b ? n,31 ? n cr[cr0] clrrwi ra, rs, n clear right immediate. (n < 32) (ra) 32 ? n:31 n 0 extended mnemonic for rlwinm ra,rs,0,0,31 ? n 28-122 clrrwi. extended mnemonic for rlwinm. ra,rs,0,0,31 ? n cr[cr0] cmp bf, 0, ra, rb compare (ra) to (rb), signed. results in cr[crn], where n = bf. 28-33 cmpi bf, 0, ra, im compare (ra) to exts(im), signed. results in cr[crn], where n = bf. 28-34 cmpl bf, 0, ra, rb compare (ra) to (rb), unsigned. results in cr[crn], where n = bf. 28-35 cmpli bf, 0, ra, im compare (ra) to ( 16 0 || im), unsigned. results in cr[crn], where n = bf. 28-36 cmplw [bf,] ra, rb compare logical lword. use cr0 if bf is omitted. extended mnemonic for cmpl bf,0,ra,rb 28-35 table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a iop 480 cpu instruction summary instruction set and extended mnemonics ? alphabetical iop 480 data book r2.0 a-14 ? 2000 plx technology, inc. all rights reserved. cmplwi [bf,] ra, im compare logical lword immediate. use cr0 if bf is omitted. extended mnemonic for cmpli bf,0,ra,im 28-36 cmpw [bf,] ra, rb compare lword. use cr0 if bf is omitted. extended mnemonic for cmp bf,0,ra,rb 28-33 cmpwi [bf,] ra, im compare lword immediate. use cr0 if bf is omitted. extended mnemonic for cmpi bf,0,ra,im 28-34 cntlzw ra, rs count leading zeros in rs. place result in ra. 28-37 cntlzw. cr[cr0] crand bt, ba, bb and bit (cr ba ) with (cr bb ). place result in cr bt . 28-38 crandc bt, ba, bb and bit (cr ba ) with ? (cr bb ). place result in cr bt . 28-39 crclr bx condition register clear. extended mnemonic for crxor bx,bx,bx 28-45 creqv bt, ba, bb equivalence of bit cr ba with cr bb . cr bt ? (cr ba cr bb ) 28-40 crmove bx, by condition register move. extended mnemonic for cror bx,by,by 28-43 crnand bt, ba, bb nand bit (cr ba ) with (cr bb ). place result in cr bt . 28-38 crnor bt, ba, bb nor bit (cr ba ) with (cr bb ). place result in cr bt . 28-42 crnot bx, by condition register not. extended mnemonic for crnor bx,by,by 28-42 cror bt, ba, bb or bit (cr ba ) with (cr bb ). place result in cr bt . 28-43 crorc bt, ba, bb or bit (cr ba ) with ? (cr bb ). place result in cr bt . 28-44 crset bx condition register set. extended mnemonic for creqv bx,bx,bx 28-40 crxor bt, ba, bb xor bit (cr ba ) with (cr bb ). place result in cr bt . 28-45 dcba ra, rb speculatively establish the data cache block which contains the effective address (ra|0) + (rb). 28-46 dcbf ra, rb flush (store, then invalidate) the data cache block which contains the effective address (ra|0) + (rb). 28-48 table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a instruction set and extended mnemonics ? alphabetical iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-15 appendix a ? cpu instr sum dcbi ra, rb invalidate the data cache block which contains the effective address (ra|0) + (rb). 28-49 dcbst ra, rb store the data cache block which contains the effective address (ra|0) + (rb). 28-50 dcbt ra, rb load the data cache block which contains the effective address (ra|0) + (rb). 28-51 dcbtst ra,rb load the data cache block which contains the effective address (ra|0) + (rb). 28-52 dcbz ra, rb zero the data cache block which contains the effective address (ra|0) + (rb). 28-53 dccci ra, rb invalidate the data cache congruence class associated with the effective address (ra|0) + (rb). 28-55 dcread rt, ra, rb read either tag or data information from the data cache congruence class associated with the effective address (ra|0) + (rb). place the results in rt. 28-56 divw rt, ra, rb divide (ra) by (rb), signed. place result in rt. 28-58 divw. cr[cr0] divwo xer[so, ov] divwo. cr[cr0] xer[so, ov] divwu rt, ra, rb divide (ra) by (rb), unsigned. place result in rt. 28-59 divwu. cr[cr0] divwuo xer[so, ov] divwuo. cr[cr0] xer[so, ov] eieio storage synchronization. all loads and stores that precede the eieio instruction complete before any loads and stores that follow the instruction access main storage. implemented as sync , which is more restrictive. 28-60 eqv ra, rs, rb equivalence of (rs) with (rb). (ra) ? ((rs) (rb)) 28-61 eqv. cr[cr0] extlwi ra, rs, n, b extract and left justify immediate. (n > 0) (ra) 0:n ? 1 (rs) b:b+n ? 1 (ra) n:31 32 ? n 0 extended mnemonic for rlwinm ra,rs,b,0,n ? 1 28-122 extlwi. extended mnemonic for rlwinm. ra,rs,b,0,n ? 1 cr[cr0] table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a iop 480 cpu instruction summary instruction set and extended mnemonics ? alphabetical iop 480 data book r2.0 a-16 ? 2000 plx technology, inc. all rights reserved. extrwi ra, rs, n, b extract and right justify immediate. (n > 0) (ra) 32 ? n:31 (rs) b:b+n ? 1 (ra) 0:31 ? n 32 ? n 0 extended mnemonic for rlwinm ra,rs,b+n,32 ? n,31 28-122 extrwi. extended mnemonic for rlwinm. ra,rs,b+n,32 ? n,31 cr[cr0] extsb ra, rs extend the sign of byte (rs) 24:31 . place the result in ra. 28-62 extsb. cr[cr0] extsh ra, rs extend the sign of wordword (rs) 16:31 . place the result in ra. 28-63 extsh. cr[cr0] icbi ra, rb invalidate the instruction cache block which contains the effective address (ra|0) + (rb). 28-64 icbt ra, rb load the instruction cache block which contains the effective address (ra|0) + (rb). 28-65 iccci ra, rb invalidate instruction cache congruence class associated with the effective address (ra|0) + (rb). 28-67 icread ra, rb read either tag or data information from the instruction cache congruence class associated with the effective address (ra|0) + (rb). place the results in icdbdr. 28-69 inslwi ra, rs, n, b insert from left immediate. (n > 0) (ra) b:b+n ? 1 (rs) 0:n ? 1 extended mnemonic for rlwimi ra,rs,32 ? b,b,b+n ? 1 28-121 inslwi. extended mnemonic for rlwimi. ra,rs,32 ? b,b,b+n ? 1 cr[cr0] insrwi ra, rs, n, b insert from right immediate. (n > 0) (ra) b:b+n ? 1 (rs) 32 ? n:31 extended mnemonic for rlwimi ra,rs,32 ? b ? n,b,b+n ? 1 28-121 insrwi. extended mnemonic for rlwimi. ra,rs,32 ? b ? n,b,b+n ? 1 cr[cr0] isync synchronize execution context by flushing the prefetch queue. 28-71 la rt, d(ra) load address. (ra 0) d is an offset from a base address that is assumed to be (ra). (rt) (ra) + exts(d) extended mnemonic for addi rt,ra,d 28-10 lbz rt, d(ra) load byte from ea = (ra|0) + exts(d) and pad left with zeroes, (rt) 24 0|| ms(ea,1). 28-72 table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a instruction set and extended mnemonics ? alphabetical iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-17 appendix a ? cpu instr sum lbzu rt, d(ra) load byte from ea = (ra|0) + exts(d) and pad left with zeroes, (rt) 24 0|| ms(ea,1). update the base address, (ra) ea. 28-73 lbzux rt, ra, rb load byte from ea = (ra|0) + (rb) and pad left with zeroes, (rt) 24 0|| ms(ea,1). update the base address, (ra) ea. 28-74 lbzx rt, ra, rb load byte from ea = (ra|0) + (rb) and pad left with zeroes, (rt) 24 0|| ms(ea,1). 28-75 lha rt, d(ra) load word from ea = (ra|0) + exts(d) and sign extend, (rt) exts(ms(ea,2)). 28-76 lhau28-80 rt, d(ra) load word from ea = (ra|0) + exts(d) and sign extend, (rt) exts(ms(ea,2)). update the base address, (ra) ea. 28-77 lhaux rt, ra, rb load word from ea = (ra|0) + (rb) and sign extend, (rt) exts(ms(ea,2)). update the base address, (ra) ea. 28-78 lhax rt, ra, rb load word from ea = (ra|0) + (rb) and sign extend, (rt) exts(ms(ea,2)). 28-79 lhbrx rt, ra, rb load word from ea = (ra|0) + (rb) then reverse byte order and pad left with zeroes, (rt) 16 0 || ms(ea+1,1) || ms(ea,1). 28-80 lhz rt, d(ra) load word from ea = (ra|0) + exts(d) and pad left with zeroes, (rt) 16 0|| ms(ea,2). 28-81 lhzu rt, d(ra) load word from ea = (ra|0) + exts(d) and pad left with zeroes, (rt) 16 0|| ms(ea,2). update the base address, (ra) ea. 28-82 lhzux rt, ra, rb load word from ea = (ra|0) + (rb) and pad left with zeroes, (rt) 16 0|| ms(ea,2). update the base address, (ra) ea. 28-83 lhzx rt, ra, rb load word from ea = (ra|0) + (rb) and pad left with zeroes, (rt) 16 0|| ms(ea,2). 28-84 table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a iop 480 cpu instruction summary instruction set and extended mnemonics ? alphabetical iop 480 data book r2.0 a-18 ? 2000 plx technology, inc. all rights reserved. li rt, im load immediate. (rt) exts(im) extended mnemonic for addi rt,0,value 28-10 lis rt, im load immediate shifted. (rt) (im || 16 0) extended mnemonic for addis rt,0,value 28-13 lmw rt, d(ra) load multiple words starting from ea = (ra|0) + exts(d). place into consecutive registers, rt through gpr(31). ra is not altered unless ra = gpr(31). 28-85 lswi rt, ra, nb load consecutive bytes from ea=(ra|0). number of bytes n=32 if nb=0, else n=nb. stack bytes into words in ceil(n/4) consecutive registers starting with rt, to r final ((rt + ceil(n/4) ? 1) % 32). gpr(0) is consecutive to gpr(31). ra is not altered unless ra = r final . 28-86 lswx rt, ra, rb load consecutive bytes from ea=(ra|0)+(rb). number of bytes n=xer[tbc]. stack bytes into words in ceil(n/4) consecutive registers starting with rt, to r final ((rt + ceil(n/4) ? 1) % 32). gpr(0) is consecutive to gpr(31). ra is not altered unless ra = r final . rb is not altered unless rb = r final . if n=0, content of rt is undefined. 28-88 lwarx rt, ra, rb load lword from ea = (ra|0) + (rb) and place in rt, (rt) ms(ea,4). set the reservation bit. 28-90 lwbrx rt, ra, rb load lword from ea = (ra|0) + (rb) then reverse byte order, (rt) ms(ea+3,1) || ms(ea+2,1) || ms(ea+1,1) || ms(ea,1). 28-91 lwz rt, d(ra) load lword from ea = (ra|0) + exts(d) and place in rt, (rt) ms(ea,4). 28-92 lwzu rt, d(ra) load lword from ea = (ra|0) + exts(d) and place in rt, (rt) ms(ea,4). update the base address, (ra) ea. 28-93 lwzux rt, ra, rb load lword from ea = (ra|0) + (rb) and place in rt, (rt) ms(ea,4). update the base address, (ra) ea. 28-94 table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a instruction set and extended mnemonics ? alphabetical iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-19 appendix a ? cpu instr sum lwzx rt, ra, rb load lword from ea = (ra|0) + (rb) and place in rt, (rt) ms(ea,4). 28-95 mcrf bf, bfa move cr field, (cr[crn]) (cr[crm]) where m bfa and n bf. 28-96 mcrxr bf move xer[0:3] into field crn, where n bf. cr[crn] (xer[so, ov, ca]). (xer[so, ov, ca]) 3 0. 28-97 mfcr rt move from cr to rt, (rt) (cr). 28-98 mfdcr rt, dcrn move from dcr to rt, (rt) (dcr(dcrn)). 28-99 mfmsr rt move from msr to rt, (rt) (msr). 28-100 mfcdbcr mfctr mfdac1 mfdbsr mfdccr mfdcwr mfdear mfesr mfevpr mfiac1 mficcr mficdbdr mflr mfpit mfpvr mfsgr mfsprg0 mfsprg1 mfsprg2 mfsprg3 mfsrr0 mfsrr1 mfsrr2 mfsrr3 mftbhi mftbhu mftblo mftblu mftcr mftsr mfxer rt move from special purpose register (spr) sprn. extended mnemonic for mfspr rt,sprn see table 29-2 on page 29-2 for listing of valid sprn values. 28-101 mfspr rt, sprn move from spr to rt, (rt) (spr(sprn)). 28-101 mr rt, rs move register. (rt) (rs) extended mnemonic for or rt,rs,rs 28-115 mr. extended mnemonic for or. rt,rs,rs cr[cr0] table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a iop 480 cpu instruction summary instruction set and extended mnemonics ? alphabetical iop 480 data book r2.0 a-20 ? 2000 plx technology, inc. all rights reserved. mtcr rs move to condition register. extended mnemonic for mtcrf 0xff,rs 28-103 mtcrf fxm, rs move some or all of the contents of rs into cr as specified by fxm field, mask 4 (fxm 0 ) || 4 (fxm 1 ) || ... || 4 (fxm 6 ) || 4 (fxm 7 ). (cr) ((rs) mask) (cr) ? mask). 28-103 mtdcr dcrn, rs move to dcr from rs, (dcr(dcrn)) (rs). 28-104 mtmsr rs move to msr from rs, (msr) (rs). 28-105 mtcdbcr mtctr mtdac1 mtdbcr mtdbsr mtdccr mtdcwr mtesr mtevpr mtiac1 mticcr mticdbdr mtlr mtpit mtpvr mtsgr mtsprg0 mtsprg1 mtsprg2 mtsprg3 mtsrr0 mtsrr1 mtsrr2 mtsrr3 mttbhi mttblo mttcr mttsr mtxer rs move to spr sprn. extended mnemonic for mtspr sprn,rs see table 29-2 on page 29-2 for listing of valid sprn values. 28-106 mtspr sprn, rs move to spr from rs, (spr(sprn)) (rs). 28-106 mulhw rt, ra, rb multiply (ra) and (rb), signed. place high-order result in rt. prod 0:63 (ra) (rb) (signed). (rt) prod 0:31. 28-108 mulhw. cr[cr0] mulhwu rt, ra, rb multiply (ra) and (rb), unsigned. place high-order result in rt. prod 0:63 (ra) (rb) (unsigned). (rt) prod 0:31. 28-108 mulhwu. cr[cr0] table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a instruction set and extended mnemonics ? alphabetical iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-21 appendix a ? cpu instr sum mulli rt, ra, im multiply (ra) and im, signed. place low-order result in rt. prod 0:47 (ra) im (signed) (rt) prod 16:47 28-110 mullw rt, ra, rb multiply (ra) and (rb), signed. place low-order result in rt. prod 0:63 (ra) (rb) (signed). (rt) prod 32:63. 28-111 mullw. cr[cr0] mullwo xer[so, ov] mullwo. cr[cr0] xer[so, ov] nand ra, rs, rb nand (rs) with (rb). place result in ra. 28-112 nand. cr[cr0] neg rt, ra negative ( twos complement) of ra. (rt) ? (ra) + 1 28-113 neg. cr[cr0] nego xer[so, ov] nego. cr[cr0] xer[so, ov] nop preferred no-op, triggers optimizations based on no-ops. extended mnemonic for ori 0,0,0 28-117 nor ra, rs, rb nor (rs) with (rb). place result in ra. 28-114 nor. cr[cr0] not ra, rs complement register. (ra) ? (rs) extended mnemonic for nor ra,rs,rs 28-114 not. extended mnemonic for nor. ra,rs,rs cr[cr0] or ra, rs, rb or (rs) with (rb). place result in ra. 28-115 or. cr[cr0] orc ra, rs, rb or (rs) with ? (rb). place result in ra. 28-116 orc. cr[cr0] ori ra, rs, im or (rs) with ( 16 0 || im). place result in ra. 28-117 oris ra, rs, im or (rs) with (im || 16 0). place result in ra. 28-118 rfci return from critical interrupt (pc) (srr2). (msr) (srr3). 28-119 rfi return from interrupt. (pc) (srr0). (msr) (srr1). 28-120 table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a iop 480 cpu instruction summary instruction set and extended mnemonics ? alphabetical iop 480 data book r2.0 a-22 ? 2000 plx technology, inc. all rights reserved. rlwimi ra, rs, sh, mb, me rotate left lword immediate, then insert according to mask. r rotl((rs), sh) m mask(mb, me) (ra) (r m) ((ra) ? m) 28-121 rlwimi. cr[cr0] rlwinm ra, rs, sh, mb, me rotate left lword immediate, then and with mask. r rotl((rs), sh) m mask(mb, me) (ra) (r m) 28-122 rlwinm. cr[cr0] rlwnm ra, rs, rb, mb, me rotate left lword, then and with mask. r rotl((rs), (rb) 27:31 ) m mask(mb, me) (ra) (r m) 28-124 rlwnm. cr[cr0] rotlw ra, rs, rb rotate left. (ra) rotl((rs), (rb) 27:31 ) extended mnemonic for rlwnm ra,rs,rb,0,31 28-124 rotlw. extended mnemonic for rlwnm. ra,rs,rb,0,31 cr[cr0] rotlwi ra, rs, n rotate left immediate. (ra) rotl((rs), n) extended mnemonic for rlwinm ra,rs,n,0,31 28-122 rotlwi. extended mnemonic for rlwinm. ra,rs,n,0,31 cr[cr0] rotrwi ra, rs, n rotate right immediate. (ra) rotl((rs), 32 ? n) extended mnemonic for rlwinm ra,rs,32 ? n,0,31 28-122 rotrwi. extended mnemonic for rlwinm. ra,rs,32 ? n,0,31 cr[cr0] sc system call exception is generated. (srr1) (msr) (srr0) (pc) pc evpr 0:15 || x'0c00' (msr[we, pr, ee, pe, dr, ir]) 0 (msr[le]) (msr[ile]) 28-125 slw ra, rs, rb shift left (rs) by (rb) 27:31 . n (rb) 27:31. r rotl((rs), n). if (rb) 26 = 0 then m mask(0, 31 ? n) else m 32 0. (ra) r m. 28-126 slw. cr[cr0] slwi ra, rs, n shift left immediate. (n < 32) (ra) 0:31 ? n (rs) n:31 (ra) 32 ? n:31 n 0 extended mnemonic for rlwinm ra,rs,n,0,31 ? n 28-122 slwi. extended mnemonic for rlwinm. ra,rs,n,0,31 ? n cr[cr0] table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a instruction set and extended mnemonics ? alphabetical iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-23 appendix a ? cpu instr sum sraw ra, rs, rb shift right algebraic (rs) by (rb) 27:31 . n (rb) 27:31 . r rotl((rs), 32 ? n). if (rb) 26 = 0 then m mask(n, 31) else m 32 0. s (rs) 0. (ra) (r m) ( 32 s ? m). xer[ca] s ((r ? m) 0). 28-127 sraw. cr[cr0] srawi ra, rs, sh shift right algebraic (rs) by sh. n sh. r rotl((rs), 32 ? n). m mask(n, 31). s (rs) 0. (ra) (r m) ( 32 s ? m). xer[ca] s ((r ? m) 0). 28-128 srawi. cr[cr0] srw ra, rs, rb shift right (rs) by (rb) 27:31 . n (rb) 27:31 . r rotl((rs), 32 ? n). if (rb) 26 = 0 then m mask(n, 31) else m 32 0. (ra) r m. 28-129 srw. cr[cr0] srwi ra, rs, n shift right immediate. (n < 32) (ra) n:31 (rs) 0:31 ? n (ra) 0:n ? 1 n 0 extended mnemonic for rlwinm ra,rs,32 ? n,n,31 28-122 srwi. extended mnemonic for rlwinm. ra,rs,32 ? n,n,31 cr[cr0] stb rs, d(ra) store byte (rs) 24:31 in memory at ea = (ra|0) + exts(d). 28-130 stbu rs, d(ra) store byte (rs) 24:31 in memory at ea = (ra|0) + exts(d). update the base address, (ra) ea. 28-131 stbux rs, ra, rb store byte (rs) 24:31 in memory at ea = (ra|0) + (rb). update the base address, (ra) ea. 28-132 stbx rs, ra, rb store byte (rs) 24:31 in memory at ea = (ra|0) + (rb). 28-133 sth rs, d(ra) store word (rs) 16:31 in memory at ea = (ra|0) + exts(d). 28-134 sthbrx rs, ra, rb store word (rs) 16:31 byte-reversed in memory at ea = (ra|0) + (rb). ms(ea, 2) (rs) 24:31 || (rs) 16:23 28-135 sthu rs, d(ra) store word (rs) 16:31 in memory at ea = (ra|0) + exts(d). update the base address, (ra) ea. 28-136 table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a iop 480 cpu instruction summary instruction set and extended mnemonics ? alphabetical iop 480 data book r2.0 a-24 ? 2000 plx technology, inc. all rights reserved. sthux rs, ra, rb store word (rs) 16:31 in memory at ea = (ra|0) + (rb). update the base address, (ra) ea. 28-137 sthx rs, ra, rb store word (rs) 16:31 in memory at ea = (ra|0) + (rb). 28-138 stmw rs, d(ra) store consecutive words from rs through gpr(31) in memory starting at ea = (ra|0) + exts(d). 28-139 stswi rs, ra, nb store consecutive bytes in memory starting at ea=(ra|0). number of bytes n=32 if nb=0, else n=nb. bytes are unstacked from ceil(n/4) consecutive registers starting with rs. gpr(0) is consecutive to gpr(31). 28-140 stswx rs, ra, rb store consecutive bytes in memory starting at ea=(ra|0) + (rb). number of bytes n=xer[tbc]. bytes are unstacked from ceil(n/4) consecutive registers starting with rs. gpr(0) is consecutive to gpr(31). 28-141 stw rs, d(ra) store lword (rs) in memory at ea = (ra|0) + exts(d). 28-143 stwbrx rs, ra, rb store lword (rs) byte-reversed in memory at ea = (ra|0) + (rb). ms(ea, 4) (rs) 24:31 || (rs) 16:23 || (rs) 8:15 || (rs) 0:7 28-144 stwcx. rs, ra, rb store lword (rs) in memory at ea = (ra|0) + (rb) only if reservation bit is set. if reserve = 1 then ms(ea, 4) (rs) reserve 0 (cr[cr0]) 2 0 || 1 || xer so else (cr[cr0]) 2 0 || 0 || xer so. 28-145 stwu rs, d(ra) store lword (rs) in memory at ea = (ra|0) + exts(d). update the base address, (ra) ea. 28-146 stwux rs, ra, rb store lword (rs) in memory at ea = (ra|0) + (rb). update the base address, (ra) ea. 28-147 stwx rs, ra, rb store lword (rs) in memory at ea = (ra|0) + (rb). 28-148 table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a instruction set and extended mnemonics ? alphabetical iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-25 appendix a ? cpu instr sum sub rt, ra, rb subtract (rb) from (ra). (rt) ? (rb) + (ra) + 1. extended mnemonic for subf rt,rb,ra 28-149 sub. extended mnemonic for subf. rt,rb,ra cr[cr0] subo extended mnemonic for subfo rt,rb,ra xer[so, ov] subo. extended mnemonic for subfo. rt,rb,ra cr[cr0] xer[so, ov] subc rt, ra, rb subtract (rb) from (ra). (rt) ? (rb) + (ra) + 1. place carry-out in xer[ca]. extended mnemonic for subfc rt,rb,ra 28-150 subc. extended mnemonic for subfc. rt,rb,ra cr[cr0] subco extended mnemonic for subfco rt,rb,ra xer[so, ov] subco. extended mnemonic for subfco. rt,rb,ra cr[cr0] xer[so, ov] subf rt, ra, rb subtract (ra) from (rb). (rt) ? (ra) + (rb) + 1. 28-149 subf. cr[cr0] subfo xer[so, ov] subfo. cr[cr0] xer[so, ov] subfc rt, ra, rb subtract (ra) from (rb). (rt) ? (ra) + (rb) + 1. place carry-out in xer[ca]. 28-150 subfc. cr[cr0] subfco xer[so, ov] subfco. cr[cr0] xer[so, ov] subfe rt, ra, rb subtract (ra) from (rb) with carry-in. (rt) ? (ra) + (rb) + xer[ca]. place carry-out in xer[ca]. 28-151 subfe. cr[cr0] subfeo xer[so, ov] subfeo. cr[cr0] xer[so, ov] subfic rt, ra, im subtract (ra) from exts(im). (rt) ? (ra) + exts(im) + 1. place carry-out in xer[ca]. 28-152 table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a iop 480 cpu instruction summary instruction set and extended mnemonics ? alphabetical iop 480 data book r2.0 a-26 ? 2000 plx technology, inc. all rights reserved. subfme rt, ra, rb subtract (ra) from ( ? 1) with carry-in. (rt) ? (ra) + ( ? 1) + xer[ca]. place carry-out in xer[ca]. 28-153 subfme. cr[cr0] subfmeo xer[so, ov] subfmeo. cr[cr0] xer[so, ov] subfze rt, ra, rb subtract (ra) from zero with carry-in. (rt) ? (ra) + xer[ca]. place carry-out in xer[ca]. 28-154 subfze. cr[cr0] subfzeo xer[so, ov] subfzeo. cr[cr0] xer[so, ov] subi rt, ra, im subtract exts(im) from (ra|0). place result in rt. extended mnemonic for addi rt,ra, ? im 28-10 subic rt, ra, im subtract exts(im) from (ra). place result in rt. place carry-out in xer[ca]. extended mnemonic for addic rt,ra, ? im 28-11 subic. rt, ra, im subtract exts(im) from (ra). place result in rt. place carry-out in xer[ca]. extended mnemonic for addic. rt,ra, ? im cr[cr0] 28-12 subis rt, ra, im subtract (im || 16 0) from (ra|0). place result in rt. extended mnemonic for addis rt,ra, ? im 28-13 sync synchronization. all instructions that precede sync complete before any instructions that follow sync begin. when sync completes, all storage accesses initiated prior to sync are completed. 28-155 tlbia all of the entries in the tlb are invalidated and become unavailable for translation by clearing the valid (v) bit in the tlbhi portion of each tlb entry. the rest of the fields in the tlb entries are unmodified. 28-156 tlbre rt, ra,ws if ws = 0: load tlbhi portion of the selected tlb entry into rt. load the pid register with the contents of the tid field of the selected tlb entry. (rt) tlbhi[(ra)] (pid) tlb[(ra)]tid if ws = 1: load tlblo portion of the selected tlb entry into rt. (rt) tlblo[(ra)] 28-157 table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a instruction set and extended mnemonics ? alphabetical iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-27 appendix a ? cpu instr sum tlbrehi rt, ra load tlbhi portion of the selected tlb entry into rt. load the pid register with the contents of the tid field of the selected tlb entry. (rt) tlbhi[(ra)] (pid) tlb[(ra)]tid extended mnemonic for tlbre rt,ra,0 28-157 tlbrelo rt, ra load tlblo portion of the selected tlb entry into rt. (rt) tlblo[(ra)] extended mnemonic for tlbre rt,ra,1 28-157 tlbsx rt,ra,rb search the tlb array for a valid entry which translates the effective address ea = (ra|0) + (rb). if found, (rt) index of tlb entry. if not found, (rt) undefined. 28-159 tlbsx. if found, (rt) index of tlb entry. cr[cr0] eq 1. if not found, (rt) undefined. cr[cr0] eq 1. cr[cr0] lt,gt,so tlbsync tlbsync does not complete until all previous tlb-update instructions executed by this processor have been received and completed by all other processors. for iop 480 cpu, tlbsync is a no-op. 28-160 tlbwe rs, ra,ws if ws = 0: write tlbhi portion of the selected tlb entry from rs. write the tid field of the selected tlb entry from the pid register. tlbhi[(ra)] (rs) tlb[(ra)]tid (pid)24:31 if ws = 1: write tlblo portion of the selected tlb entry from rs. tlblo[(ra)] (rs) 28-161 tlbwehi rs, ra write tlbhi portion of the selected tlb entry from rs. write the tid field of the selected tlb entry from the pid register. tlbhi[(ra)] (rs) tlb[(ra)]tid (pid)24:31 extended mnemonic for tlbwe rs,ra,0 28-161 table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a iop 480 cpu instruction summary instruction set and extended mnemonics ? alphabetical iop 480 data book r2.0 a-28 ? 2000 plx technology, inc. all rights reserved. tlbwelo rs, ra write tlblo portion of the selected tlb entry from rs. tlblo[(ra)] (rs) extended mnemonic for tlbwe rs,ra,1 28-161 trap trap unconditionally. extended mnemonic for tw 31,0,0 tweq ra, rb trap if (ra) equal to (rb). extended mnemonic for tw 4,ra,rb twge trap if (ra) greater than or equal to (rb). extended mnemonic for tw 12,ra,rb twgt trap if (ra) greater than (rb). extended mnemonic for tw 8,ra,rb twle trap if (ra) less than or equal to (rb). extended mnemonic for tw 20,ra,rb twlge trap if (ra) logically greater than or equal to (rb). extended mnemonic for tw 5,ra,rb twlgt trap if (ra) logically greater than (rb). extended mnemonic for tw 1,ra,rb twlle trap if (ra) logically less than or equal to (rb). extended mnemonic for tw 6,ra,rb twllt trap if (ra) logically less than (rb). extended mnemonic for tw 2,ra,rb twlng trap if (ra) logically not greater than (rb). extended mnemonic for tw 6,ra,rb twlnl trap if (ra) logically not less than (rb). extended mnemonic for tw 5,ra,rb twlt trap if (ra) less than (rb). extended mnemonic for tw 16,ra,rb twne trap if (ra) not equal to (rb). extended mnemonic for tw 24,ra,rb twng trap if (ra) not greater than (rb). extended mnemonic for tw 20,ra,rb twnl trap if (ra) not less than (rb). extended mnemonic for tw 12,ra,rb tw to, ra, rb trap exception is generated if, comparing (ra) with (rb), any condition specified by to is true. 28-163 table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a instruction set and extended mnemonics ? alphabetical iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-29 appendix a ? cpu instr sum tweqi ra, im trap if (ra) equal to exts(im). extended mnemonic for twi 4,ra,im twgei trap if (ra) greater than or equal to exts(im). extended mnemonic for twi 12,ra,im twgti trap if (ra) greater than exts(im). extended mnemonic for twi 8,ra,im twlei trap if (ra) less than or equal to exts(im). extended mnemonic for twi 20,ra,im twlgei trap if (ra) logically greater than or equal to exts(im). extended mnemonic for twi 5,ra,im twlgti trap if (ra) logically greater than exts(im). extended mnemonic for twi 1,ra,im twllei trap if (ra) logically less than or equal to exts(im). extended mnemonic for twi 6,ra,im twllti trap if (ra) logically less than exts(im). extended mnemonic for twi 2,ra,im twlngi trap if (ra) logically not greater than exts(im). extended mnemonic for twi 6,ra,im twlnli trap if (ra) logically not less than exts(im). extended mnemonic for twi 5,ra,im twlti trap if (ra) less than exts(im). extended mnemonic for twi 16,ra,im twnei trap if (ra) not equal to exts(im). extended mnemonic for twi 24,ra,im twngi trap if (ra) not greater than exts(im). extended mnemonic for twi 20,ra,im twnli trap if (ra) not less than exts(im). extended mnemonic for twi 12,ra,im twi to, ra, im trap exception is generated if, comparing (ra) with exts(im), any condition specified by to is true. wrtee rs write value of rs 16 to the external enable bit (msr[ee]). 28-169 wrteei e write value of e to the external enable bit (msr[ee]). xor ra, rs, rb xor (rs) with (rb). place result in ra. xor. cr[cr0] xori ra, rs, im xor (rs) with ( 16 0 || im). place result in ra. xoris ra, rs, im xor (rs) with (im || 16 0). place result in ra. table a-1. iop 480 cpu instruction syntax summary (continued) mnemonic operands function other registers changed page appendix a iop 480 cpu instruction summary instructions sorted by opcode iop 480 data book r2.0 a-30 ? 2000 plx technology, inc. all rights reserved. a.2 instructions sorted by opcode all instructions are four bytes long and lword-aligned. all instructions have a primary opcode field (shown as field opcd in figure a-1 through figure a-9 beginning on page a-38) in bits 0:5. some instructions also have a secondary opcode field (shown as field xo in figure a-1 through figure a-9). iop 480 cpu instructions sorted by primary and secondary opcode may be found in table a-2. the ? form ? indicated in the table refers to the arrangement of valid field combinations within the four-byte instruction. see section a.3, ? instruction formats, ? on page a-36 for illustration of the field layouts associated with each form. form x has a 10-bit secondary opcode field, while form xo uses only the low-order 9-bits of that field. form xo uses the high-order secondary opcode bit (the tenth bit) as a variable; therefore, every form xo instruction really consumes two secondary opcodes from the 10-bit secondary-opcode space. the implicitly consumed secondary opcode is listed in parentheses for form xo instructions in table a-2. table a-2. iop 480 cpu instructions by opcode primary opcode secondary opcode form mnemonic operands page 3 d twi to, ra, im 28-166 7 d mulli rt, ra, im 28-110 8 d subfic rt, ra, im 28-152 10 d cmpli bf, 0, ra, im 28-36 11 d cmpi bf, 0, ra, im 28-34 12 d addic rt, ra, im 28-11 13 d addic. rt, ra, im 28-12 14 d addi rt, ra, im 28-10 15 d addis rt, ra, im 28-13 16 b bc bo, bi, target 28-21 bca bcl bcla 17 sc sc 28-125 18 i b target 28-20 ba bl bla 19 0 xl mcrf bf, bfa 28-96 19 16 xl bclr bo, bi 28-29 bclrl 19 33 xl crnor bt, ba, bb 28-42 19 50 xl rfi 28-120 19 51 xl rfci 28-119 19 129 xl crandc bt, ba, bb 28-39 appendix a instructions sorted by opcode iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-31 appendix a ? cpu instr sum 19 150 xl isync 28-71 19 193 xl crxor bt, ba, bb 28-45 19 225 xl crnand bt, ba, bb 28-41 19 257 xl crand bt, ba, bb 28-38 19 289 xl creqv bt, ba, bb 28-40 19 417 xl crorc bt, ba, bb 28-44 19 449 xl cror bt, ba, bb 28-43 19 528 xl bcctr bo, bi 28-26 bcctrl 20 m rlwimi ra, rs, sh, mb, me 28-121 rlwimi. 21 m rlwinm ra, rs, sh, mb, me 28-122 rlwinm. 23 m rlwnm ra, rs, rb, mb, me 28-124 rlwnm. 24 d ori ra, rs, im 28-117 25 d oris ra, rs, im 28-118 26 d xori ra, rs, im 28-172 27 d xoris ra, rs, im 28-173 28 d andi. ra, rs, im 28-18 29 d andis. ra, rs, im 28-19 31 0 x cmp bf, 0, ra, rb 28-33 31 4 x tw to, ra, rb 28-163 31 8 (520) xo subfc rt, ra, rb 28-150 subfc. subfco subfco. 31 10 (522) xo addc rt, ra, rb 28-8 addc. addco addco. 31 11 (523) xo mulhwu rt, ra, rb 28-109 mulhwu. 31 19 x mfcr rt 28-98 31 20 x lwarx rt, ra, rb 28-90 31 23 x lwzx rt, ra, rb 28-95 table a-2. iop 480 cpu instructions by opcode (continued) primary opcode secondary opcode form mnemonic operands page appendix a iop 480 cpu instruction summary instructions sorted by opcode iop 480 data book r2.0 a-32 ? 2000 plx technology, inc. all rights reserved. 31 24 x slw ra, rs, rb 28-126 slw. 31 26 x cntlzw ra, rs 28-37 cntlzw. 31 28 x and ra, rs, rb 28-16 and. 31 32 x cmpl bf, 0, ra, rb 28-35 31 40 (552) xo subf rt, ra, rb 28-149 subf. subfo subfo. 31 54 x dcbst ra, rb 28-50 31 55 x lwzux rt, ra, rb 28-94 31 60 x andc ra, rs, rb 28-17 andc. 31 75 (587) xo mulhw rt, ra, rb 28-108 mulhw. 31 83 x mfmsr rt 28-100 31 86 x dcbf ra, rb 28-48 31 87 x lbzx rt, ra, rb 28-75 31 104 (616) xo neg rt, ra 28-113 neg. nego nego. 31 119 x lbzux rt, ra, rb 28-74 31 124 x nor ra, rs, rb 28-114 nor. 31 131 x wrtee rs 28-169 31 136 (648) xo subfe rt, ra, rb 28-151 subfe. subfeo subfeo. 31 138 (650) xo adde rt, ra, rb 28-9 adde. addeo addeo. table a-2. iop 480 cpu instructions by opcode (continued) primary opcode secondary opcode form mnemonic operands page appendix a instructions sorted by opcode iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-33 appendix a ? cpu instr sum 31 144 xfx mtcrf fxm, rs 28-103 31 146 x mtmsr rs 28-105 31 150 x stwcx. rs, ra, rb 28-145 31 151 x stwx rs, ra, rb 28-148 31 163 x wrteei e 28-170 31 183 x stwux rs, ra, rb 28-147 31 200 (712) xo subfze rt, ra, rb 28-154 subfze. subfzeo subfzeo. 31 202 (714) xo addze rt, ra 28-15 addze. addzeo addzeo. 31 215 x stbx rs, ra, rb 28-133 31 232 (744) xo subfme rt, ra, rb 28-153 subfme. subfmeo subfmeo. 31 234 (746) xo addme rt, ra 28-14 addme. addmeo addmeo. 31 235 (747) xo mullw rt, ra, rb 28-111 mullw. mullwo mullwo. 31 246 x dcbtst ra,rb 28-52 31 247 x stbux rs, ra, rb 28-132 31 262 x icbt ra, rb 28-65 31 266 (778) xo add rt, ra, rb 28-7 add. addo addo. 31 278 x dcbt ra, rb 28-51 31 279 x lhzx rt, ra, rb 28-84 table a-2. iop 480 cpu instructions by opcode (continued) primary opcode secondary opcode form mnemonic operands page appendix a iop 480 cpu instruction summary instructions sorted by opcode iop 480 data book r2.0 a-34 ? 2000 plx technology, inc. all rights reserved. 31 284 x eqv ra, rs, rb 28-61 eqv. 31 311 x lhzux rt, ra, rb 28-83 31 316 x xor ra, rs, rb 28-171 xor. 31 323 xfx mfdcr rt, dcrn 28-99 31 339 xfx mfspr rt, sprn 28-101 31 343 x lhax rt, ra, rb 28-79 31 370 x tlbia 28-156 31 375 x lhaux rt, ra, rb 28-78 31 407 x sthx rs, ra, rb 28-138 31 412 x orc ra, rs, rb 28-116 orc. 31 439 x sthux rs, ra, rb 28-137 31 444 x or ra, rs, rb 28-115 or. 31 451 xfx mtdcr dcrn, rs 28-104 31 454 x dccci ra, rb 28-55 31 459 (971) xo divwu rt, ra, rb 28-59 divwu. divwuo divwuo. 31 467 xfx mtspr sprn, rs 28-106 31 470 x dcbi ra, rb 28-49 31 476 x nand ra, rs, rb 28-112 nand. 31 486 x dcread rt, ra, rb 28-56 31 491 (1003) xo divw rt, ra, rb 28-58 divw. divwo divwo. 31 512 x mcrxr bf 28-97 31 533 x lswx rt, ra, rb 28-88 31 534 x lwbrx rt, ra, rb 28-91 31 536 x srw ra, rs, rb 28-129 srw. table a-2. iop 480 cpu instructions by opcode (continued) primary opcode secondary opcode form mnemonic operands page appendix a instructions sorted by opcode iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-35 appendix a ? cpu instr sum 31 566 x tlbsync 28-160 31 597 x lswi rt, ra, nb 28-86 31 598 x sync 28-155 31 661 x stswx rs, ra, rb 28-141 31 662 x stwbrx rs, ra, rb 28-144 31 725 x stswi rs, ra, nb 28-140 31 790 x lhbrx rt, ra, rb 28-80 31 792 x sraw ra, rs, rb 28-127 sraw. 31 824 x srawi ra, rs, sh 28-128 srawi. 31 854 x eieio 28-60 31 914 x tlbsx rt,ra,rb 28-159 tlbsx. 31 918 x sthbrx rs, ra, rb 28-135 31 922 x extsh ra, rs 28-63 extsh. 31 946 x tlbre rt, ra,ws 28-157 31 954 x extsb ra, rs 28-62 extsb. 31 966 x iccci ra, rb 28-67 31 978 x tlbwe rs, ra,ws 28-161 31 982 x icbi ra, rb 28-64 31 998 x icread ra, rb 28-69 31 1014 x dcbz ra, rb 28-53 31 tbd x dcba ra, rb 28-46 32 d lwz rt, d(ra) 28-92 33 d lwzu rt, d(ra) 28-93 34 d lbz rt, d(ra) 28-72 35 d lbzu rt, d(ra) 28-73 36 d stw rs, d(ra) 28-143 37 d stwu rs, d(ra) 28-146 38 d stb rs, d(ra) 28-130 39 d stbu rs, d(ra) 28-131 40 d lhz rt, d(ra) 28-81 41 d lhzu rt, d(ra) 28-82 table a-2. iop 480 cpu instructions by opcode (continued) primary opcode secondary opcode form mnemonic operands page appendix a iop 480 cpu instruction summary instruction formats iop 480 data book r2.0 a-36 ? 2000 plx technology, inc. all rights reserved. a.3 instruction formats instructions are four bytes long. instruction addresses are always lword-aligned. instruction bits 0 through 5 always contain the primary opcode. many instructions have an extended opcode in another field. the remaining instruction bits contain additional fields. all instruction fields belong to one of the following categories: defined these instructions contain values, such as opcodes, that cannot be altered. the instruction format diagrams specify the values of defined fields. variable these fields contain operands, such as general purpose register selectors and immediate values, that may vary from execution to execution. the instruction format diagrams specify the operands in variable fields. reserved bits in a reserved field should be set to 0. in the instruction format diagrams, reserved fields are shaded. if any bit in a defined field does not contain the expected value, the instruction is illegal and an illegal instruction exception occurs. if any bit in a reserved field does not contain 0, the instruction form is invalid and its result is architecturally undefined. iop 480 cpu executes all invalid instruction forms without causing an illegal instruction exception. a.3.1 instruction fields iop 480 cpu instructions contain various combinations of the following fields, as indicated in the instruction format diagrams. the numbers, enclosed in parentheses, that follow the field names indicate the bit positions; bit fields are indicated by starting and stopping bit positions separated by colons. aa (30) absolute address bit. 0 the immediate field represents an address relative to the current instruction address (cia). the effective address (ea) of the branch is either the sum of the li field sign- extended to 32 bits and the branch instruction address, or the sum of the bd field sign-extended to 32 bits and the branch instruction address. 1 the immediate field represents an absolute address. the ea of the branch is either the li field or the bd field, sign-extended to 32 bits. ba (11:15) specifies a bit in the condition register (cr) used as a source of a cr-logical instruction. bb (16:20) specifies a bit in the cr used as a source of a cr-logical instruction. bd (16:29) an immediate field specifying a 14-bit signed twos complement branch displacement. this field is concatenated on the right with 0b00 and sign-extended to 32 bits. bf (6:8) specifies a field in the cr used as a target in a compare or mcrf instruction. 42 d lha rt, d(ra) 28-76 43 d lhau rt, d(ra) 28-77 44 d sth rs, d(ra) 28-134 45 d sthu rs, d(ra) 28-136 46 d lmw rt, d(ra) 28-85 47 d stmw rs, d(ra) 28-139 table a-2. iop 480 cpu instructions by opcode (continued) primary opcode secondary opcode form mnemonic operands page appendix a instruction formats iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-37 appendix a ? cpu instr sum bfa (11:13) specifies a field in the cr used as a source in a mcrf instruction. bi (11:15) specifies a bit in the cr used as a source for the condition of a conditional branch instruction. bo (6:10) specifies options for conditional branch instructions. see section 24.6.4, ? bo field on conditional branches, ? on page 24-22. bt (6:10) specifies a bit in the cr used as a target as the result of a cr-logical instruction. d (16:31) specifies a 16-bit signed twos - complement integer displacement for load/store instructions. dcrn (11:20) specifies a device control register (dcr). fxm (12:19) field mask used to identify cr fields to be updated by the mtcrf instruction. im (16:31) an immediate field used to specify a 16-bit value (either signed integer or unsigned). li (6:29) an immediate field specifying a 24-bit signed twos complement branch displacement; this field is concatenated on the right with b'00' and sign-extended to 32 bits. lk (31) link bit. 0 do not update the link register (lr). 1 update the lr with the address of the next instruction. mb (21:25) mask begin. used in rotate-and-mask instructions to specify the beginning bit of a mask. me (26:30) mask end. used in rotate-and-mask instructions to specify the ending bit of a mask. nb (16:20) specifies the number of bytes to move in an immediate string load or store. opcd (0:5) primary opcode. primary opcodes, in decimal, appear in the instruction format diagrams presented with individual instructions. the opcd field name does not appear in instruction descriptions. oe (21) enables setting the ov and so fields in the fixed-point exception register (xer) for extended arithmetic. ra (11:15) a gpr used as a source or target. rb (16:20) a gpr used as a source. rc (31) record bit. 0 do not set the cr. 1 set the cr to reflect the result of an operation. see section 24.2.3, ? condition register (cr), ? on page 24-7, for a further discussion of how the cr bits are set. rs (6:10) a gpr used as a source. rt (6:10) a gpr used as a target. sh (16:20) specifies a shift amount. sprf (11:20) specifies a special purpose register (spr). to (6:10) specifies the conditions on which to trap, as described under tw and twi instructions. xo (21:30) extended opcode for instructions without an oe field. extended opcodes, in decimal, appear in the instruction format diagrams presented with individual instructions. the xo field name does not appear in instruction descriptions. xo (22:30) extended opcode for instructions with an oe field. extended opcodes, in decimal, appear in the instruction format diagrams presented with individual instructions. the xo field name does not appear in instruction descriptions. appendix a iop 480 cpu instruction summary instruction formats iop 480 data book r2.0 a-38 ? 2000 plx technology, inc. all rights reserved. a.3.2 instruction format diagrams the ? forms ? shown in figure a-1 through figure a-9 are valid combinations of instruction fields for iop 480 cpu. table a-2 on page a-30 indicates which ? form ? is utilized by each iop 480 cpu opcode. fields indicated by slashes (/, //, or ///) are reserved. these figures have been adapted from the powerpc user instruction set architecture. i-form b-form sc-form d-form opcd li aa lk 06 30 31 figure a-1. instruction format opcd bo bi bd aa lk 0 6 11 16 30 31 figure a-2. b instruction format opcd /// /// /// 1 / 0 6 11 16 30 31 figure a-3. sc instruction format opcd rt ra d opcd rt ra si opcd rs ra d opcd rs ra ui opcd bf / l ra si opcd bf / l ra ui opcd to ra si 0 6 11 16 31 figure a-4. d instruction format appendix a instruction formats iop 480 cpu instruction summary iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. a-39 appendix a ? cpu instr sum x-form opcd rt ra rb xo rc opcd rt ra rb xo / opcd rt ra nb xo / opcd rt ra ws xo / opcd rt /// rb xo / opcd rt /// /// xo / opcd rs ra rb xo rc opcd rs ra rb xo 1 opcd rs ra rb xo / opcd rs ra nb xo / opcd rs ra ws xo / opcd rs ra sh xo rc opcd rs ra /// xo rc opcd rs /// rb xo / opcd rs /// /// xo / opcd bf / l ra rb xo / opcd bf // bfa // /// xo / opcd bf // /// u / xo rc opcd bf // /// /// xo / opcd to ra rb xo / opcd bt /// /// xo rc opcd /// ra rb xo / opcd /// /// rb xo / opcd /// /// /// xo / opcd /// /// e // xo / 0 6 11 16 21 31 figure a-5. x instruction format appendix a iop 480 cpu instruction summary instruction formats iop 480 data book r2.0 a-40 ? 2000 plx technology, inc. all rights reserved. xl-form xfx-form xo-form m-form opcd bt ba bb xo / opcd bo bi /// xo lk opcd bf // bfa // /// xo / opcd /// /// /// xo / 0 6 11 16 21 31 figure a-6. xl instruction format opcd rt sprf xo / opcd rt dcrf xo / opcd rt / fxm / xo / opcd rs sprf xo / opcd rs dcrf xo / 0 6 11 21 31 figure a-7. xfx instruction format opcd rt ra rb o e xo rc opcd rt ra rb / xo rc opcd rt ra /// o e xo rc 0 6 11 16 21 22 31 figure a-8. xo instruction format opcd rs ra rb mb me rc opcd rs ra sh mb me rc 0 6 11 16 21 26 31 figure a-9. m instruction format iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-1 appendix b ? cpu instr/cat b iop 480 cpu instructions by category b.1 instruction set summary categories section 28, ? iop 480 cpu instruction set, ? contains detailed descriptions of the instructions, their operands, and notation. table b-1 summarizes the instruction categories in the iop 480 cpu instruction set. the instructions within each category are listed in subsequent tables. table b-1. iop 480 cpu instruction set functional summary storage reference load, store arithmetic and logical add, subtract, negate, multiply, divide, and, andc, or, orc, xor, nand, nor, xnor, sign extension, count leading zeros comparison compare, compare logical, compare immediate branch branch, branch conditional, branch to lr, branch to ctr cr logical crand, crandc, cror, crorc, crnand, crnor, crxor, crxnor, move cr field rotate/shift rotate and insert, rotate and mask, shift left, shift right cache control invalidate, touch, zero, flush, store, read interrupt control write to external interrupt enable bit, move to/from msr, return from interrupt, return from critical interrup t processor management system call, synchronize, trap, move to/from dcrs, move to/from sprs, move to/from cr appendix b iop 480 cpu instructions by category instructions specific to powerpc embedded controllers iop 480 data book r2.0 b-2 ? 2000 plx technology, inc. all rights reserved. b.2 instructions specific to powerpc embedded controllers to meet the functional requirements of processors for embedded systems and real-time applications, the powerpc-embedded controller family defines instructions that are not part of the powerpc architecture. table b-2 summarizes iop 480 cpu instructions specific to powerpc embedded controller family. table b-2. instructions specific to powerpc-embedded controllers mnemonic operands function other registers changed page dccci ra, rb invalidate the data cache congruence class associated with the effective address (ra|0) + (rb). 28-55 dcread rt, ra, rb read either tag or data information from the data cache congruence class associated with the effective address (ra|0) + (rb). place the results in rt. 28-56 icbt ra, rb load the instruction cache block which contains the effective address (ra|0) + (rb). 28-65 iccci ra, rb invalidate instruction cache congruence class associated with the effective address (ra|0) + (rb). 28-67 icread ra, rb read either tag or data information from the instruction cache congruence class associated with the effective address (ra|0) + (rb). place the results in icdbdr. 28-69 mfdcr rt, dcrn move from dcr to rt, (rt) (dcr(dcrn)). 28-99 mtdcr dcrn, rs move to dcr from rs, (dcr(dcrn)) (rs). 28-104 rfci return from critical interrupt (pc) (srr2). (msr) (srr3). 28-119 wrtee rs write value of rs 16 to msr[ee]. 28-169 wrteei e write value of e to msr[ee]. 28-170 tlbre rt, ra,ws if ws = 0: load tlbhi portion of the selected tlb entry into rt. load the pid register with the contents of the tid field of the selected tlb entry. (rt) tlbhi[(ra)] (pid) tlb[(ra)]tid if ws = 1: load tlblo portion of the selected tlb entry into rt. (rt) tlblo[(ra)] 28-157 appendix b instructions specific to powerpc embedded controllers iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-3 appendix b ? cpu instr/cat tlbsx rt,ra,rb search the tlb array for a valid entry which translates the effective address ea = (ra|0) + (rb). if found, (rt) index of tlb entry. if not found, (rt) undefined. 28-159 tlbsx. if found, (rt) index of tlb entry. cr[cr0] eq 1. if not found, (rt) undefined. cr[cr0] eq 1. cr[cr0] lt,gt,so tlbwe rs, ra,ws if ws = 0: write tlbhi portion of the selected tlb entry from rs. write the tid field of the selected tlb entry from the pid register. tlbhi[(ra)] (rs) tlb[(ra)]tid (pid)24:31 if ws = 1: write tlblo portion of the selected tlb entry from rs. tlblo[(ra)] (rs) 28-161 wrtee rs write value of rs 16 to the external enable bit (msr[ee]). 28-169 wrteei e write value of e to the external enable bit (msr[ee]). 28-170 table b-2. instructions specific to powerpc-embedded controllers (continued) mnemonic operands function other registers changed page appendix b iop 480 cpu instructions by category privileged instructions iop 480 data book r2.0 b-4 ? 2000 plx technology, inc. all rights reserved. b.3 privileged instructions table b-3 lists instructions that are under control of the msr[pr] bit. these instructions are not allowed to be executed when msr[pr] = 1. table b-3. privileged instructions mnemonic operands function other registers changed page dcbi ra, rb invalidate the data cache block which contains the effective address (ra|0) + (rb). 28-49 dccci ra, rb invalidate the data cache congruence class associated with the effective address (ra|0) + (rb). 28-55 dcread rt, ra, rb read either tag or data information from the data cache congruence class associated with the effective address (ra|0) + (rb). place the results in rt. 28-56 icbt ra, rb load the instruction cache block which contains the effective address (ra|0) + (rb). 28-65 iccci ra, rb invalidate instruction cache congruence class associated with the effective address (ra|0) + (rb). 28-67 icread ra, rb read either tag or data information from the instruction cache congruence class associated with the effective address (ra|0) + (rb). place the results in icdbdr. 28-69 mfdcr rt, dcrn move from dcr to rt, (rt) (dcr(dcrn)). 28-99 mfmsr rt move from msr to rt, (rt) (msr). 28-100 mfspr rt, sprn move from spr to rt, (rt) (spr(sprn)). privileged for all sprs except lr, ctr, tbhu, tblu, and xer. 28-101 mtdcr dcrn, rs move to dcr from rs, (dcr(dcrn)) (rs). 28-104 mtmsr rs move to msr from rs, (msr) (rs). 28-105 mtspr sprn, rs move to spr from rs, (spr(sprn)) (rs). privileged for all sprs except lr, ctr, tbhu, tblu, and xer. 28-106 rfci return from critical interrupt (pc) (srr2). (msr) (srr3). 28-119 rfi return from interrupt. (pc) (srr0). (msr) (srr1). 28-120 tlbia all of the entries in the tlb are invalidated and become unavailable for translation by clearing the valid (v) bit in the tlbhi portion of each tlb entry. the remaining fields in the tlb entries are unmodified. 28-156 appendix b privileged instructions iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-5 appendix b ? cpu instr/cat tlbre rt, ra,ws if ws = 0: load tlbhi portion of the selected tlb entry into rt. load the pid register with the contents of the tid field of the selected tlb entry. (rt) tlbhi[(ra)] (pid) tlb[(ra)]tid if ws = 1: load tlblo portion of the selected tlb entry into rt. (rt) tlblo[(ra)] 28-157 tlbsx rt,ra,rb search the tlb array for a valid entry which translates the effective address ea = (ra|0) + (rb). if found, (rt) index of tlb entry. if not found, (rt) undefined. 28-159 tlbsx. if found, (rt) index of tlb entry. cr[cr0] eq 1. if not found, (rt) undefined. cr[cr0] eq 1. cr[cr0] lt,gt,so tlbsync tlbsync does not complete until all previous tlb-update instructions executed by this processor have been received and completed by all other processors. for iop 480 cpu, tlbsync is a no-op. 28-21 tlbwe rs, ra,ws if ws = 0: write tlbhi portion of the selected tlb entry from rs. write the tid field of the selected tlb entry from the pid register. tlbhi[(ra)] (rs) tlb[(ra)]tid (pid)24:31 if ws = 1: write tlblo portion of the selected tlb entry from rs. tlblo[(ra)] (rs) 28-161 wrtee rs write value of rs 16 to the external enable bit (msr[ee]). 28-169 wrteei e write value of e to the external enable bit (msr[ee]). 28-170 table b-3. privileged instructions (continued) mnemonic operands function other registers changed page appendix b iop 480 cpu instructions by category assembler extended mnemonics iop 480 data book r2.0 b-6 ? 2000 plx technology, inc. all rights reserved. b.4 assembler extended mnemonics in the appendix ? assembler extended mnemonics ? of the powerpc architecture, it is required that a powerpc assembler support at least a minimal set of extended mnemonics. these mnemonics encode to the opcodes of other instructions; the only benefit of extended mnemonics is improved usability. code using extended mnemonics can be easier to write and to understand. table b-4 lists the extended mnemonics required for iop 480 cpu. note the following for every branch conditional mnemonic: bit 4 of the bo field provides a hint about the most likely outcome of a conditional branch (see section 24.6.5, ? branch prediction, ? on page 24-23 for a full discussion of branch prediction). assemblers should set bo 4 = 0 unless a specific reason exists otherwise. in the bo field values specified in the table below, bo 4 = 0 has always been assumed. the assembler must allow the programmer to specify branch prediction. to do this, the assembler supports a suffix to every conditional branch mnemonic, as follows: + predict branch to be taken. ? predict branch not to be taken. as specific examples, bc also could be coded as bc+ or bc ? , and bne also could be coded bne+ or bne ? . these alternate codings set bo 4 = 1 only if the requested prediction differs from the standard prediction (see section 24.6.5, ? branch prediction, ? on page 24-23). table b-4. iop 480 cpu extended mnemonics mnemonic operands function other registers changed page bctr branch unconditionally, to address in ctr. extended mnemonic for bcctr 20,0 28-26 bctrl extended mnemonic for bcctrl 20,0 (lr) cia + 4. bdnz target decrement ctr. branch if ctr 0. extended mnemonic for bc 16,0,target 28-21 bdnza extended mnemonic for bca 16,0,target bdnzl extended mnemonic for bcl 16,0,target (lr) cia + 4. bdnzla extended mnemonic for bcla 16,0,target (lr) cia + 4. bdnzlr decrement ctr. branch if ctr 0, to address in lr. extended mnemonic for bclr 16,0 28-29 bdnzlrl extended mnemonic for bclrl 16,0 (lr) cia + 4. appendix b assembler extended mnemonics iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-7 appendix b ? cpu instr/cat bdnzf cr_bit, target decrement ctr. branch if ctr 0 and cr cr_bit = 0. extended mnemonic for bc 0,cr_bit,target 28-21 bdnzfa extended mnemonic for bca 0,cr_bit,target bdnzfl extended mnemonic for bcl 0,cr_bit,target (lr) cia + 4. bdnzfla extended mnemonic for bcla 0,cr_bit,target (lr) cia + 4. bdnzflr cr_bit decrement ctr. branch if ctr 0 and cr cr_bit = 0, to address in lr. extended mnemonic for bclr 0,cr_bit 28-29 bdnzflrl extended mnemonic for bclrl 0,cr_bit (lr) cia + 4. bdnzt cr_bit, target decrement ctr. branch if ctr 0 and cr cr_bit = 1. extended mnemonic for bc 8,cr_bit,target 28-21 bdnzta extended mnemonic for bca 8,cr_bit,target bdnztl extended mnemonic for bcl 8,cr_bit,target (lr) cia + 4. bdnztla extended mnemonic for bcla 8,cr_bit,target (lr) cia + 4. bdnztlr cr_bit decrement ctr. branch if ctr 0 and cr cr_bit = 1, to address in lr. extended mnemonic for bclr 8,cr_bit 28-29 bdnztlrl extended mnemonic for bclrl 8,cr_bit (lr) cia + 4. bdz target decrement ctr. branch if ctr = 0. extended mnemonic for bc 18,0,target 28-21 bdza extended mnemonic for bca 18,0,target bdzl extended mnemonic for bcl 18,0,target (lr) cia + 4. bdzla extended mnemonic for bcla 18,0,target (lr) cia + 4. table b-4. iop 480 cpu extended mnemonics (continued) mnemonic operands function other registers changed page appendix b iop 480 cpu instructions by category assembler extended mnemonics iop 480 data book r2.0 b-8 ? 2000 plx technology, inc. all rights reserved. bdzlr decrement ctr. branch if ctr = 0, to address in lr. extended mnemonic for bclr 18,0 28-29 bdzlrl extended mnemonic for bclrl 18,0 (lr) cia + 4. bdzf cr_bit, target decrement ctr. branch if ctr = 0 and cr cr_bit = 0. extended mnemonic for bc 2,cr_bit,target 28-21 bdzfa extended mnemonic for bca 2,cr_bit,target bdzfl extended mnemonic for bcl 2,cr_bit,target (lr) cia + 4. bdzfla extended mnemonic for bcla 2,cr_bit,target (lr) cia + 4. bdzflr cr_bit decrement ctr. branch if ctr = 0 and cr cr_bit = 0 to address in lr. extended mnemonic for bclr 2,cr_bit 28-29 bdzflrl extended mnemonic for bclrl 2,cr_bit (lr) cia + 4. bdzt cr_bit, target decrement ctr. branch if ctr = 0 and cr cr_bit = 1. extended mnemonic for bc 10,cr_bit,target 28-21 bdzta extended mnemonic for bca 10,cr_bit,target bdztl extended mnemonic for bcl 10,cr_bit,target (lr) cia + 4. bdztla extended mnemonic for bcla 10,cr_bit,target (lr) cia + 4. bdztlr cr_bit decrement ctr. branch if ctr = 0 and cr cr_bit = 1, to address in lr. extended mnemonic for bclr 10,cr_bit 28-29 bdztlrl extended mnemonic for bclrl 10,cr_bit (lr) cia + 4. table b-4. iop 480 cpu extended mnemonics (continued) mnemonic operands function other registers changed page appendix b assembler extended mnemonics iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-9 appendix b ? cpu instr/cat beq [cr_field,] target branch if equal. use cr0 if cr_field is omitted. extended mnemonic for bc 12,4 ? cr_field+2,target 28-21 beqa extended mnemonic for bca 12,4 ? cr_field+2,target beql extended mnemonic for bcl 12,4 ? cr_field+2,target (lr) cia + 4. beqla extended mnemonic for bcla 12,4 ? cr_field+2,target (lr) cia + 4. beqctr [cr_field] branch if equal, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 12,4 ? cr_field+2 28-26 beqctrl extended mnemonic for bcctrl 12,4 ? cr_field+2 (lr) cia + 4. beqlr [cr_field] branch if equal, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 12,4 ? cr_field+2 28-29 beqlrl extended mnemonic for bclrl 12,4 ? cr_field+2 (lr) cia + 4. bf cr_bit, target branch if cr cr_bit = 0. extended mnemonic for bc 4,cr_bit,target 28-21 bfa extended mnemonic for bca 4,cr_bit,target bfl extended mnemonic for bcl 4,cr_bit,target (lr) cia + 4. bfla extended mnemonic for bcla 4,cr_bit,target (lr) cia + 4. bfctr cr_bit branch if cr cr_bit = 0, to address in ctr. extended mnemonic for bcctr 4,cr_bit 28-26 bfctrl extended mnemonic for bcctrl 4,cr_bit (lr) cia + 4. bflr cr_bit branch if cr cr_bit = 0, to address in lr. extended mnemonic for bclr 4,cr_bit 28-29 bflrl extended mnemonic for bclrl 4,cr_bit (lr) cia + 4. table b-4. iop 480 cpu extended mnemonics (continued) mnemonic operands function other registers changed page appendix b iop 480 cpu instructions by category assembler extended mnemonics iop 480 data book r2.0 b-10 ? 2000 plx technology, inc. all rights reserved. bge [cr_field,] target branch if greater than or equal. use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+0,target 28-21 bgea extended mnemonic for bca 4,4 ? cr_field+0,target bgel extended mnemonic for bcl 4,4 ? cr_field+0,target (lr) cia + 4. bgela extended mnemonic for bcla 4,4 ? cr_field+0,target (lr) cia + 4. bgectr [cr_field] branch if greater than or equal, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+0 28-26 bgectrl extended mnemonic for bcctrl 4,4 ? cr_field+0 (lr) cia + 4. bgelr [cr_field] branch if greater than or equal, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+0 28-29 bgelrl extended mnemonic for bclrl 4,4 ? cr_field+0 (lr) cia + 4. bgt [cr_field,] target branch if greater than. use cr0 if cr_field is omitted. extended mnemonic for bc 12,4 ? cr_field+1,target 28-21 bgta extended mnemonic for bca 12,4 ? cr_field+1,target bgtl extended mnemonic for bcl 12,4 ? cr_field+1,target (lr) cia + 4. bgtla extended mnemonic for bcla 12,4 ? cr_field+1,target (lr) cia + 4. bgtctr [cr_field] branch if greater than, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 12,4 ? cr_field+1 28-26 bgtctrl extended mnemonic for bcctrl 12,4 ? cr_field+1 (lr) cia + 4. bgtlr [cr_field] branch if greater than, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 12,4 ? cr_field+1 28-29 bgtlrl extended mnemonic for bclrl 12,4 ? cr_field+1 (lr) cia + 4. table b-4. iop 480 cpu extended mnemonics (continued) mnemonic operands function other registers changed page appendix b assembler extended mnemonics iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-11 appendix b ? cpu instr/cat ble [cr_field,] target branch if less than or equal. use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+1,target 28-21 blea extended mnemonic for bca 4,4 ? cr_field+1,target blel extended mnemonic for bcl 4,4 ? cr_field+1,target (lr) cia + 4. blela extended mnemonic for bcla 4,4 ? cr_field+1,target (lr) cia + 4. blectr [cr_field] branch if less than or equal, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+1 28-26 blectrl extended mnemonic for bcctrl 4,4 ? cr_field+1 (lr) cia + 4. blelr [cr_field] branch if less than or equal, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+1 28-29 blelrl extended mnemonic for bclrl 4,4 ? cr_field+1 (lr) cia + 4. blr branch unconditionally, to address in lr. extended mnemonic for bclr 20,0 28-29 blrl extended mnemonic for bclrl 20,0 (lr) cia + 4. blt [cr_field,] target branch if less than. use cr0 if cr_field is omitted. extended mnemonic for bc 12,4 ? cr_field+0,target 28-21 blta extended mnemonic for bca 12,4 ? cr_field+0,target bltl extended mnemonic for bcl 12,4 ? cr_field+0,target (lr) cia + 4. bltla extended mnemonic for bcla 12,4 ? cr_field+0,target (lr) cia + 4. bltctr [cr_field] branch if less than, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 12,4 ? cr_field+0 28-26 bltctrl extended mnemonic for bcctrl 12,4 ? cr_field+0 (lr) cia + 4. table b-4. iop 480 cpu extended mnemonics (continued) mnemonic operands function other registers changed page appendix b iop 480 cpu instructions by category assembler extended mnemonics iop 480 data book r2.0 b-12 ? 2000 plx technology, inc. all rights reserved. bltlr [cr_field] branch if less than, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 12,4 ? cr_field+0 28-29 bltlrl extended mnemonic for bclrl 12,4 ? cr_field+0 (lr) cia + 4. bne [cr_field,] target branch if not equal. use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+2,target 28-21 bnea extended mnemonic for bca 4,4 ? cr_field+2,target bnel extended mnemonic for bcl 4,4 ? cr_field+2,target (lr) cia + 4. bnela extended mnemonic for bcla 4,4 ? cr_field+2,target (lr) cia + 4. bnectr [cr_field] branch if not equal, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+2 28-26 bnectrl extended mnemonic for bcctrl 4,4 ? cr_field+2 (lr) cia + 4. bnelr [cr_field] branch if not equal, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+2 28-29 bnelrl extended mnemonic for bclrl 4,4 ? cr_field+2 (lr) cia + 4. bng [cr_field,] target branch if not greater than. use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+1,target 28-21 bnga extended mnemonic for bca 4,4 ? cr_field+1,target bngl extended mnemonic for bcl 4,4 ? cr_field+1,target (lr) cia + 4. bngla extended mnemonic for bcla 4,4 ? cr_field+1,target (lr) cia + 4. bngctr [cr_field] branch if not greater than, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+1 28-26 bngctrl extended mnemonic for bcctrl 4,4 ? cr_field+1 (lr) cia + 4. table b-4. iop 480 cpu extended mnemonics (continued) mnemonic operands function other registers changed page appendix b assembler extended mnemonics iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-13 appendix b ? cpu instr/cat bnglr [cr_field] branch if not greater than, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+1 28-29 bnglrl extended mnemonic for bclrl 4,4 ? cr_field+1 (lr) cia + 4. bnl [cr_field,] target branch if not less than. use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+0,target 28-21 bnla extended mnemonic for bca 4,4 ? cr_field+0,target bnll extended mnemonic for bcl 4,4 ? cr_field+0,target (lr) cia + 4. bnlla extended mnemonic for bcla 4,4 ? cr_field+0,target (lr) cia + 4. bnlctr [cr_field] branch if not less than, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+0 28-26 bnlctrl extended mnemonic for bcctrl 4,4 ? cr_field+0 (lr) cia + 4. bnllr [cr_field] branch if not less than, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+0 28-29 bnllrl extended mnemonic for bclrl 4,4 ? cr_field+0 (lr) cia + 4. bns [cr_field,] target branch if not summary overflow. use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+3,target 28-21 bnsa extended mnemonic for bca 4,4 ? cr_field+3,target bnsl extended mnemonic for bcl 4,4 ? cr_field+3,target (lr) cia + 4. bnsla extended mnemonic for bcla 4,4 ? cr_field+3,target (lr) cia + 4. bnsctr [cr_field] branch if not summary overflow, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+3 28-26 bnsctrl extended mnemonic for bcctrl 4,4 ? cr_field+3 (lr) cia + 4. table b-4. iop 480 cpu extended mnemonics (continued) mnemonic operands function other registers changed page appendix b iop 480 cpu instructions by category assembler extended mnemonics iop 480 data book r2.0 b-14 ? 2000 plx technology, inc. all rights reserved. bnslr [cr_field] branch if not summary overflow, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+3 28-29 bnslrl extended mnemonic for bclrl 4,4 ? cr_field+3 (lr) cia + 4. bnu [cr_field,] target branch if not unordered. use cr0 if cr_field is omitted. extended mnemonic for bc 4,4 ? cr_field+3,target 28-21 bnua extended mnemonic for bca 4,4 ? cr_field+3,target bnul extended mnemonic for bcl 4,4 ? cr_field+3,target (lr) cia + 4. bnula extended mnemonic for bcla 4,4 ? cr_field+3,target (lr) cia + 4. bnuctr [cr_field] branch if not unordered, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 4,4 ? cr_field+3 28-26 bnuctrl extended mnemonic for bcctrl 4,4 ? cr_field+3 (lr) cia + 4. bnulr [cr_field] branch if not unordered, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 4,4 ? cr_field+3 28-29 bnulrl extended mnemonic for bclrl 4,4 ? cr_field+3 (lr) cia + 4. bso [cr_field,] target branch if summary overflow. use cr0 if cr_field is omitted. extended mnemonic for bc 12,4 ? cr_field+3,target 28-21 bsoa extended mnemonic for bca 12,4 ? cr_field+3,target bsol extended mnemonic for bcl 12,4 ? cr_field+3,target (lr) cia + 4. bsola extended mnemonic for bcla 12,4 ? cr_field+3,target (lr) cia + 4. bsoctr [cr_field] branch if summary overflow, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 12,4 ? cr_field+3 28-26 bsoctrl extended mnemonic for bcctrl 12,4 ? cr_field+3 (lr) cia + 4. table b-4. iop 480 cpu extended mnemonics (continued) mnemonic operands function other registers changed page appendix b assembler extended mnemonics iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-15 appendix b ? cpu instr/cat bsolr [cr_field] branch if summary overflow, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 12,4 ? cr_field+3 28-29 bsolrl extended mnemonic for bclrl 12,4 ? cr_field+3 (lr) cia + 4. bt cr_bit, target branch if cr cr_bit = 1. extended mnemonic for bc 12,cr_bit,target 28-21 bta extended mnemonic for bca 12,cr_bit,target btl extended mnemonic for bcl 12,cr_bit,target (lr) cia + 4. btla extended mnemonic for bcla 12,cr_bit,target (lr) cia + 4. btctr cr_bit branch if cr cr_bit = 1, to address in ctr. extended mnemonic for bcctr 12,cr_bit 28-26 btctrl extended mnemonic for bcctrl 12,cr_bit (lr) cia + 4. btlr cr_bit branch if cr cr_bit = 1, to address in lr. extended mnemonic for bclr 12,cr_bit 28-29 btlrl extended mnemonic for bclrl 12,cr_bit (lr) cia + 4. bun [cr_field,] target branch if unordered. use cr0 if cr_field is omitted. extended mnemonic for bc 12,4 ? cr_field+3,target 28-21 buna extended mnemonic for bca 12,4 ? cr_field+3,target bunl extended mnemonic for bcl 12,4 ? cr_field+3,target (lr) cia + 4. bunla extended mnemonic for bcla 12,4 ? cr_field+3,target (lr) cia + 4. bunctr [cr_field] branch if unordered, to address in ctr. use cr0 if cr_field is omitted. extended mnemonic for bcctr 12,4 ? cr_field+3 28-26 bunctrl extended mnemonic for bcctrl 12,4 ? cr_field+3 (lr) cia + 4. table b-4. iop 480 cpu extended mnemonics (continued) mnemonic operands function other registers changed page appendix b iop 480 cpu instructions by category assembler extended mnemonics iop 480 data book r2.0 b-16 ? 2000 plx technology, inc. all rights reserved. bunlr [cr_field] branch if unordered, to address in lr. use cr0 if cr_field is omitted. extended mnemonic for bclr 12,4 ? cr_field+3 28-29 bunlrl extended mnemonic for bclrl 12,4 ? cr_field+3 (lr) cia + 4. clrlwi ra, rs, n clear left immediate. (n < 32) (ra) 0:n ? 1 n 0 extended mnemonic for rlwinm ra,rs,0,n,31 28-122 clrlwi. extended mnemonic for rlwinm. ra,rs,0,n,31 cr[cr0] clrlslwi ra, rs, b, n clear left and shift left immediate. (n b < 32) (ra) b ? n:31 ? n (rs) b:31 (ra) 32 ? n:31 n 0 (ra) 0:b ? n ? 1 b ? n 0 extended mnemonic for rlwinm ra,rs,n,b ? n,31 ? n 28-122 clrlslwi. extended mnemonic for rlwinm. ra,rs,n,b ? n,31 ? n cr[cr0] clrrwi ra, rs, n clear right immediate. (n < 32) (ra) 32 ? n:31 n 0 extended mnemonic for rlwinm ra,rs,0,0,31 ? n 28-122 clrrwi. extended mnemonic for rlwinm. ra,rs,0,0,31 ? n cr[cr0] cmplw [bf,] ra, rb compare logical lword. use cr0 if bf is omitted. extended mnemonic for cmpl bf,0,ra,rb 28-35 cmplwi [bf,] ra, im compare logical lword immediate. use cr0 if bf is omitted. extended mnemonic for cmpli bf,0,ra,im 28-36 cmpw [bf,] ra, rb compare lword. use cr0 if bf is omitted. extended mnemonic for cmp bf,0,ra,rb 28-33 cmpwi [bf,] ra, im compare lword immediate. use cr0 if bf is omitted. extended mnemonic for cmpi bf,0,ra,im 28-34 crclr bx condition register clear. extended mnemonic for crxor bx,bx,bx 28-45 crmove bx, by condition register move. extended mnemonic for cror bx,by,by 28-43 table b-4. iop 480 cpu extended mnemonics (continued) mnemonic operands function other registers changed page appendix b assembler extended mnemonics iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-17 appendix b ? cpu instr/cat crnot bx, by condition register not. extended mnemonic for crnor bx,by,by 28-42 crset bx condition register set. extended mnemonic for creqv bx,bx,bx 28-40 extlwi ra, rs, n, b extract and left justify immediate. (n > 0) (ra) 0:n ? 1 (rs) b:b+n ? 1 (ra) n:31 32 ? n 0 extended mnemonic for rlwinm ra,rs,b,0,n ? 1 28-122 extlwi. extended mnemonic for rlwinm. ra,rs,b,0,n ? 1 cr[cr0] extrwi ra, rs, n, b extract and right justify immediate. (n > 0) (ra) 32 ? n:31 (rs) b:b+n ? 1 (ra) 0:31 ? n 32 ? n 0 extended mnemonic for rlwinm ra,rs,b+n,32 ? n,31 28-122 extrwi. extended mnemonic for rlwinm. ra,rs,b+n,32 ? n,31 cr[cr0] inslwi ra, rs, n, b insert from left immediate. (n > 0) (ra) b:b+n ? 1 (rs) 0:n ? 1 extended mnemonic for rlwimi ra,rs,32 ? b,b,b+n ? 1 28-121 inslwi. extended mnemonic for rlwimi. ra,rs,32 ? b,b,b+n ? 1 cr[cr0] insrwi ra, rs, n, b insert from right immediate. (n > 0) (ra) b:b+n ? 1 (rs) 32 ? n:31 extended mnemonic for rlwimi ra,rs,32 ? b ? n,b,b+n ? 1 28-121 insrwi. extended mnemonic for rlwimi. ra,rs,32 ? b ? n,b,b+n ? 1 cr[cr0] la rt, d(ra) load address. (ra 0) d is an offset from a base address that is assumed to be (ra). (rt) (ra) + exts(d) extended mnemonic for addi rt,ra,d 28-10 li rt, im load immediate. (rt) exts(im) extended mnemonic for addi rt,0,value 28-10 lis rt, im load immediate shifted. (rt) (im || 16 0) extended mnemonic for addis rt,0,value 28-13 table b-4. iop 480 cpu extended mnemonics (continued) mnemonic operands function other registers changed page appendix b iop 480 cpu instructions by category assembler extended mnemonics iop 480 data book r2.0 b-18 ? 2000 plx technology, inc. all rights reserved. mfcdbcr mfctr mfdac1 mfdbsr mfdccr mfdcwr mfdear mfesr mfevpr mfiac1 mficcr mficdbdr mflr mfpit mfpvr mfsgr mfsprg0 mfsprg1 mfsprg2 mfsprg3 mfsrr0 mfsrr1 mfsrr2 mfsrr3 mftbhi mftbhu mftblo mftblu mftcr mftsr mfxer rt move from special purpose register (spr) sprn. extended mnemonic for mfspr rt,sprn see table 29-2 on page 29-2 for listing of valid sprn values. 28-101 mr rt, rs move register. (rt) (rs) extended mnemonic for or rt,rs,rs 28-115 mr. extended mnemonic for or. rt,rs,rs cr[cr0] mtcr rs move to condition register. extended mnemonic for mtcrf 0xff,rs 28-103 table b-4. iop 480 cpu extended mnemonics (continued) mnemonic operands function other registers changed page appendix b assembler extended mnemonics iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-19 appendix b ? cpu instr/cat mtcdbcr mtctr mtdac1 mtdbcr mtdbsr mtdccr mtdcwr mtesr mtevpr mtiac1 mticcr mticdbdr mtlr mtpit mtpvr mtsgr mtsprg0 mtsprg1 mtsprg2 mtsprg3 mtsrr0 mtsrr1 mtsrr2 mtsrr3 mttbhi mttblo mttcr mttsr mtxer rs move to spr sprn. extended mnemonic for mtspr sprn,rs see table 29-2 on page 29-2 for listing of valid sprn values. 28-106 nop preferred no-op, triggers optimizations based on no-ops. extended mnemonic for ori 0,0,0 28-117 not ra, rs complement register. (ra) ? (rs) extended mnemonic for nor ra,rs,rs 28-114 not. extended mnemonic for nor. ra,rs,rs cr[cr0] rotlw ra, rs, rb rotate left. (ra) rotl((rs), (rb) 27:31 ) extended mnemonic for rlwnm ra,rs,rb,0,31 28-124 rotlw. extended mnemonic for rlwnm. ra,rs,rb,0,31 cr[cr0] rotlwi ra, rs, n rotate left immediate. (ra) rotl((rs), n) extended mnemonic for rlwinm ra,rs,n,0,31 28-122 rotlwi. extended mnemonic for rlwinm. ra,rs,n,0,31 cr[cr0] table b-4. iop 480 cpu extended mnemonics (continued) mnemonic operands function other registers changed page appendix b iop 480 cpu instructions by category assembler extended mnemonics iop 480 data book r2.0 b-20 ? 2000 plx technology, inc. all rights reserved. rotrwi ra, rs, n rotate right immediate. (ra) rotl((rs), 32 ? n) extended mnemonic for rlwinm ra,rs,32 ? n,0,31 28-122 rotrwi. extended mnemonic for rlwinm. ra,rs,32 ? n,0,31 cr[cr0] slwi ra, rs, n shift left immediate. (n < 32) (ra) 0:31 ? n (rs) n:31 (ra) 32 ? n:31 n 0 extended mnemonic for rlwinm ra,rs,n,0,31 ? n 28-122 slwi. extended mnemonic for rlwinm. ra,rs,n,0,31 ? n cr[cr0] srwi ra, rs, n shift right immediate. (n < 32) (ra) n:31 (rs) 0:31 ? n (ra) 0:n ? 1 n 0 extended mnemonic for rlwinm ra,rs,32 ? n,n,31 28-122 srwi. extended mnemonic for rlwinm. ra,rs,32 ? n,n,31 cr[cr0] sub rt, ra, rb subtract (rb) from (ra). (rt) ? (rb) + (ra) + 1. extended mnemonic for subf rt,rb,ra 28-149 sub. extended mnemonic for subf. rt,rb,ra cr[cr0] subo extended mnemonic for subfo rt,rb,ra xer[so, ov] subo. extended mnemonic for subfo. rt,rb,ra cr[cr0] xer[so, ov] subc rt, ra, rb subtract (rb) from (ra). (rt) ? (rb) + (ra) + 1. place carry-out in xer[ca]. extended mnemonic for subfc rt,rb,ra 28-150 subc. extended mnemonic for subfc. rt,rb,ra cr[cr0] subco extended mnemonic for subfco rt,rb,ra xer[so, ov] subco. extended mnemonic for subfco. rt,rb,ra cr[cr0] xer[so, ov] subi rt, ra, im subtract exts(im) from (ra|0). place result in rt. extended mnemonic for addi rt,ra, ? im 28-10 table b-4. iop 480 cpu extended mnemonics (continued) mnemonic operands function other registers changed page appendix b assembler extended mnemonics iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-21 appendix b ? cpu instr/cat subic rt, ra, im subtract exts(im) from (ra). place result in rt. place carry-out in xer[ca]. extended mnemonic for addic rt,ra, ? im 28-11 subic. rt, ra, im subtract exts(im) from (ra). place result in rt. place carry-out in xer[ca]. extended mnemonic for addic. rt,ra, ? im cr[cr0] 28-12 subis rt, ra, im subtract (im || 16 0) from (ra|0). place result in rt. extended mnemonic for addis rt,ra, ? im 28-13 tlbrehi rt, ra load tlbhi portion of the selected tlb entry into rt. load the pid register with the contents of the tid field of the selected tlb entry. (rt) tlbhi[(ra)] (pid) tlb[(ra)]tid extended mnemonic for tlbre rt,ra,0 28-157 tlbrelo rt, ra load tlblo portion of the selected tlb entry into rt. (rt) tlblo[(ra)] extended mnemonic for tlbre rt,ra,1 28-157 tlbwehi rs, ra write tlbhi portion of the selected tlb entry from rs. write the tid field of the selected tlb entry from the pid register. tlbhi[(ra)] (rs) tlb[(ra)]tid (pid)24:31 extended mnemonic for tlbwe rs,ra,0 28-161 tlbwelo rs, ra write tlblo portion of the selected tlb entry from rs. tlblo[(ra)] (rs) extended mnemonic for tlbwe rs,ra,1 28-161 table b-4. iop 480 cpu extended mnemonics (continued) mnemonic operands function other registers changed page appendix b iop 480 cpu instructions by category assembler extended mnemonics iop 480 data book r2.0 b-22 ? 2000 plx technology, inc. all rights reserved. tweqi ra, im trap if (ra) equal to exts(im). extended mnemonic for twi 4,ra,im twgei trap if (ra) greater than or equal to exts(im). extended mnemonic for twi 12,ra,im twgti trap if (ra) greater than exts(im). extended mnemonic for twi 8,ra,im twlei trap if (ra) less than or equal to exts(im). extended mnemonic for twi 20,ra,im twlgei trap if (ra) logically greater than or equal to exts(im). extended mnemonic for twi 5,ra,im twlgti trap if (ra) logically greater than exts(im). extended mnemonic for twi 1,ra,im twllei trap if (ra) logically less than or equal to exts(im). extended mnemonic for twi 6,ra,im twllti trap if (ra) logically less than exts(im). extended mnemonic for twi 2,ra,im twlngi trap if (ra) logically not greater than exts(im). extended mnemonic for twi 6,ra,im twlnli trap if (ra) logically not less than exts(im). extended mnemonic for twi 5,ra,im twlti trap if (ra) less than exts(im). extended mnemonic for twi 16,ra,im twnei trap if (ra) not equal to exts(im). extended mnemonic for twi 24,ra,im twngi trap if (ra) not greater than exts(im). extended mnemonic for twi 20,ra,im twnli trap if (ra) not less than exts(im). extended mnemonic for twi 12,ra,im table b-4. iop 480 cpu extended mnemonics (continued) mnemonic operands function other registers changed page appendix b storage reference instructions iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-23 appendix b ? cpu instr/cat b.5 storage reference instructions iop 480 cpu uses load and store instructions to transfer data between memory and the general purpose registers. load and store instructions operate on byte, word and lword data. the storage reference instructions also support loading or storing multiple registers, character strings, and byte-reversed data. table b-5 shows the storage reference instructions available for use in iop 480 cpu. table b-5. storage reference instructions mnemonic operands function other registers changed page lbz rt, d(ra) load byte from ea = (ra|0) + exts(d) and pad left with zeroes, (rt) 24 0|| ms(ea,1). 28-72 lbzu rt, d(ra) load byte from ea = (ra|0) + exts(d) and pad left with zeroes, (rt) 24 0|| ms(ea,1). update the base address, (ra) ea. 28-73 lbzux rt, ra, rb load byte from ea = (ra|0) + (rb) and pad left with zeroes, (rt) 24 0|| ms(ea,1). update the base address, (ra) ea. 28-74 lbzx rt, ra, rb load byte from ea = (ra|0) + (rb) and pad left with zeroes, (rt) 24 0|| ms(ea,1). 28-75 lha rt, d(ra) load word from ea = (ra|0) + exts(d) and sign extend, (rt) exts(ms(ea,2)). 28-76 lhau rt, d(ra) load word from ea = (ra|0) + exts(d) and sign extend, (rt) exts(ms(ea,2)). update the base address, (ra) ea. 28-77 lhaux rt, ra, rb load word from ea = (ra|0) + (rb) and sign extend, (rt) exts(ms(ea,2)). update the base address, (ra) ea. 28-78 lhax rt, ra, rb load word from ea = (ra|0) + (rb) and sign extend, (rt) exts(ms(ea,2)). 28-79 lhbrx rt, ra, rb load word from ea = (ra|0) + (rb) then reverse byte order and pad left with zeroes, (rt) 16 0 || ms(ea+1,1) || ms(ea,1). 28-80 lhz rt, d(ra) load word from ea = (ra|0) + exts(d) and pad left with zeroes, (rt) 16 0|| ms(ea,2). 28-81 lhzu rt, d(ra) load word from ea = (ra|0) + exts(d) and pad left with zeroes, (rt) 16 0|| ms(ea,2). update the base address, (ra) ea. 28-82 appendix b iop 480 cpu instructions by category storage reference instructions iop 480 data book r2.0 b-24 ? 2000 plx technology, inc. all rights reserved. lhzux rt, ra, rb load word from ea = (ra|0) + (rb) and pad left with zeroes, (rt) 16 0|| ms(ea,2). update the base address, (ra) ea. 28-83 lhzx rt, ra, rb load word from ea = (ra|0) + (rb) and pad left with zeroes, (rt) 16 0|| ms(ea,2). 28-84 lmw rt, d(ra) load multiple words starting from ea = (ra|0) + exts(d). place into consecutive registers, rt through gpr(31). ra is not altered unless ra = gpr(31). 28-85 lswi rt, ra, nb load consecutive bytes from ea=(ra|0). number of bytes n=32 if nb=0, else n=nb. stack bytes into words in ceil(n/4) consecutive registers starting with rt, to r final ((rt + ceil(n/4) ? 1) % 32). gpr(0) is consecutive to gpr(31). ra is not altered unless ra = r final . 28-86 lswx rt, ra, rb load consecutive bytes from ea=(ra|0)+(rb). number of bytes n=xer[tbc]. stack bytes into words in ceil(n/4) consecutive registers starting with rt, to r final ((rt + ceil(n/4) ? 1) % 32). gpr(0) is consecutive to gpr(31). ra is not altered unless ra = r final . rb is not altered unless rb = r final . if n=0, content of rt is undefined. 28-88 lwarx rt, ra, rb load lword from ea = (ra|0) + (rb) and place in rt, (rt) ms(ea,4). set the reservation bit. 28-90 lwbrx rt, ra, rb load lword from ea = (ra|0) + (rb) then reverse byte order, (rt) ms(ea+3,1) || ms(ea+2,1) || ms(ea+1,1) || ms(ea,1). 28-91 lwz rt, d(ra) load lword from ea = (ra|0) + exts(d) and place in rt, (rt) ms(ea,4). 28-92 lwzu rt, d(ra) load lword from ea = (ra|0) + exts(d) and place in rt, (rt) ms(ea,4). update the base address, (ra) ea. 28-93 lwzux rt, ra, rb load lword from ea = (ra|0) + (rb) and place in rt, (rt) ms(ea,4). update the base address, (ra) ea. 28-94 lwzx rt, ra, rb load lword from ea = (ra|0) + (rb) and place in rt, (rt) ms(ea,4). 28-95 table b-5. storage reference instructions (continued) mnemonic operands function other registers changed page appendix b storage reference instructions iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-25 appendix b ? cpu instr/cat stb rs, d(ra) store byte (rs) 24:31 in memory at ea = (ra|0) + exts(d). 28-130 stbu rs, d(ra) store byte (rs) 24:31 in memory at ea = (ra|0) + exts(d). update the base address, (ra) ea. 28-131 stbux rs, ra, rb store byte (rs) 24:31 in memory at ea = (ra|0) + (rb). update the base address, (ra) ea. 28-132 stbx rs, ra, rb store byte (rs) 24:31 in memory at ea = (ra|0) + (rb). 28-133 sth rs, d(ra) store word (rs) 16:31 in memory at ea = (ra|0) + exts(d). 28-134 sthbrx rs, ra, rb store word (rs) 16:31 byte-reversed in memory at ea = (ra|0) + (rb). ms(ea, 2) (rs) 24:31 || (rs) 16:23 28-135 sthu rs, d(ra) store word (rs) 16:31 in memory at ea = (ra|0) + exts(d). update the base address, (ra) ea. 28-136 sthux rs, ra, rb store word (rs) 16:31 in memory at ea = (ra|0) + (rb). update the base address, (ra) ea. 28-137 sthx rs, ra, rb store word (rs) 16:31 in memory at ea = (ra|0) + (rb). 28-138 stmw rs, d(ra) store consecutive words from rs through gpr(31) in memory starting at ea = (ra|0) + exts(d). 28-139 stswi rs, ra, nb store consecutive bytes in memory starting at ea=(ra|0). number of bytes n=32 if nb=0, else n=nb. bytes are unstacked from ceil(n/4) consecutive registers starting with rs. gpr(0) is consecutive to gpr(31). 28-140 stswx rs, ra, rb store consecutive bytes in memory starting at ea=(ra|0)+(rb). number of bytes n=xer[tbc]. bytes are unstacked from ceil(n/4) consecutive registers starting with rs. gpr(0) is consecutive to gpr(31). 28-141 stw rs, d(ra) store lword (rs) in memory at ea = (ra|0) + exts(d). 28-143 stwbrx rs, ra, rb store lword (rs) byte-reversed in memory at ea = (ra|0) + (rb). ms(ea, 4) (rs) 24:31 || (rs) 16:23 || (rs) 8:15 || (rs) 0:7 28-144 table b-5. storage reference instructions (continued) mnemonic operands function other registers changed page appendix b iop 480 cpu instructions by category storage reference instructions iop 480 data book r2.0 b-26 ? 2000 plx technology, inc. all rights reserved. stwcx. rs, ra, rb store lword (rs) in memory at ea = (ra|0) + (rb) only if reservation bit is set. if reserve = 1 then ms(ea, 4) (rs) reserve 0 (cr[cr0]) 2 0 || 1 || xer so else (cr[cr0]) 2 0 || 0 || xer so. 28-145 stwu rs, d(ra) store lword (rs) in memory at ea = (ra|0) + exts(d). update the base address, (ra) ea. 28-146 stwux rs, ra, rb store lword (rs) in memory at ea = (ra|0) + (rb). update the base address, (ra) ea. 28-147 stwx rs, ra, rb store lword (rs) in memory at ea = (ra|0) + (rb). 28-148 table b-5. storage reference instructions (continued) mnemonic operands function other registers changed page appendix b arithmetic and logical instructions iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-27 appendix b ? cpu instr/cat b.6 arithmetic and logical instructions table b-6 shows the set of arithmetic and logical instructions supported by iop 480 cpu. arithmetic operations are performed on integer or ordinal operands stored in registers. instructions using two operands are defined in a three operand format where the operation is performed on the operands stored in two registers and the result is placed in a third register. instructions using one operand are defined in a two operand format where the operation is performed on the operand in one register and the result is placed in another register. several instructions also have immediate formats in which one operand is coded as part of the instruction itself. most arithmetic and logical instructions can optionally set the condition code register based on the outcome of the instruction. table b-6. arithmetic and logical instructions mnemonic operands function other registers changed page add rt, ra, rb add (ra) to (rb). place result in rt. 28-7 add. cr[cr0] addo xer[so, ov] addo. cr[cr0] xer[so, ov] addc rt, ra, rb add (ra) to (rb). place result in rt. place carry-out in xer[ca]. 28-8 addc. cr[cr0] addco xer[so, ov] addco. cr[cr0] xer[so, ov] adde rt, ra, rb add xer[ca], (ra), (rb). place result in rt. place carry-out in xer[ca]. 28-9 adde. cr[cr0] addeo xer[so, ov] addeo. cr[cr0] xer[so, ov] addi rt, ra, im add exts(im) to (ra|0). place result in rt. 28-10 addic rt, ra, im add exts(im) to (ra|0). place result in rt. place carry-out in xer[ca]. 28-11 addic. rt, ra, im add exts(im) to (ra|0). place result in rt. place carry-out in xer[ca]. cr[cr0] 28-12 addis rt, ra, im add (im || 16 0) to (ra|0). place result in rt. 28-13 addme rt, ra add xer[ca], (ra), (-1). place result in rt. place carry-out in xer[ca]. 28-14 addme. cr[cr0] addmeo xer[so, ov] addmeo. cr[cr0] xer[so, ov] appendix b iop 480 cpu instructions by category arithmetic and logical instructions iop 480 data book r2.0 b-28 ? 2000 plx technology, inc. all rights reserved. addze rt, ra add xer[ca] to (ra). place result in rt. place carry-out in xer[ca]. 28-15 addze. cr[cr0] addzeo xer[so, ov] addzeo. cr[cr0] xer[so, ov] and ra, rs, rb and (rs) with (rb). place result in ra. 28-16 and. cr[cr0] andc ra, rs, rb and (rs) with ? (rb). place result in ra. 28-17 andc. cr[cr0] andi. ra, rs, im and (rs) with ( 16 0 || im). place result in ra. cr[cr0] 28-18 andis. ra, rs, im and (rs) with (im || 16 0). place result in ra. cr[cr0] 28-19 cntlzw ra, rs count leading zeros in rs. place result in ra. 28-37 cntlzw. cr[cr0] divw rt, ra, rb divide (ra) by (rb), signed. place result in rt. 28-58 divw. cr[cr0] divwo xer[so, ov] divwo. cr[cr0] xer[so, ov] divwu rt, ra, rb divide (ra) by (rb), unsigned. place result in rt. 28-59 divwu. cr[cr0] divwuo xer[so, ov] divwuo. cr[cr0] xer[so, ov] eqv ra, rs, rb equivalence of (rs) with (rb). (ra) ? ((rs) (rb)) 28-61 eqv. cr[cr0] extsb ra, rs extend the sign of byte (rs) 24:31 . place the result in ra. 28-62 extsb. cr[cr0] extsh ra, rs extend the sign of word (rs) 16:31 . place the result in ra. 28-63 extsh. cr[cr0] mulhw rt, ra, rb multiply (ra) and (rb), signed. place hi-order result in rt. prod 0:63 (ra) (rb) (signed). (rt) prod 0:31. 28-108 mulhw. cr[cr0] mulhwu rt, ra, rb multiply (ra) and (rb), unsigned. place hi-order result in rt. prod 0:63 (ra) (rb) (unsigned). (rt) prod 0:31. 28-109 mulhwu. cr[cr0] table b-6. arithmetic and logical instructions (continued) mnemonic operands function other registers changed page appendix b arithmetic and logical instructions iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-29 appendix b ? cpu instr/cat mulli rt, ra, im multiply (ra) and im, signed. place lo-order result in rt. prod 0:47 (ra) im (signed) (rt) prod 16:47 28-110 mullw rt, ra, rb multiply (ra) and (rb), signed. place lo-order result in rt. prod 0:63 (ra) (rb) (signed). (rt) prod 32:63. 28-111 mullw. cr[cr0] mullwo xer[so, ov] mullwo. cr[cr0] xer[so, ov] nand ra, rs, rb nand (rs) with (rb). place result in ra. 28-112 nand. cr[cr0] neg rt, ra negative (two ? s complement) of ra. (rt) ? (ra) + 1 28-113 neg. cr[cr0] nego xer[so, ov] nego. cr[cr0] xer[so, ov] nor ra, rs, rb nor (rs) with (rb). place result in ra. 28-114 nor. cr[cr0] or ra, rs, rb or (rs) with (rb). place result in ra. 28-115 or. cr[cr0] orc ra, rs, rb or (rs) with ? (rb). place result in ra. 28-116 orc. cr[cr0] ori ra, rs, im or (rs) with ( 16 0 || im). place result in ra. 28-117 oris ra, rs, im or (rs) with (im || 16 0). place result in ra. 28-118 subf rt, ra, rb subtract (ra) from (rb). (rt) ? (ra) + (rb) + 1. 28-149 subf. cr[cr0] subfo xer[so, ov] subfo. cr[cr0] xer[so, ov] subfc rt, ra, rb subtract (ra) from (rb). (rt) ? (ra) + (rb) + 1. place carry-out in xer[ca]. 28-150 subfc. cr[cr0] subfco xer[so, ov] subfco. cr[cr0] xer[so, ov] table b-6. arithmetic and logical instructions (continued) mnemonic operands function other registers changed page appendix b iop 480 cpu instructions by category arithmetic and logical instructions iop 480 data book r2.0 b-30 ? 2000 plx technology, inc. all rights reserved. subfe rt, ra, rb subtract (ra) from (rb) with carry-in. (rt) ? (ra) + (rb) + xer[ca]. place carry-out in xer[ca]. 28-151 subfe. cr[cr0] subfeo xer[so, ov] subfeo. cr[cr0] xer[so, ov] subfic rt, ra, im subtract (ra) from exts(im). (rt) ? (ra) + exts(im) + 1. place carry-out in xer[ca]. 28-152 subfme rt, ra, rb subtract (ra) from ( ? 1) with carry-in. (rt) ? (ra) + ( ? 1) + xer[ca]. place carry-out in xer[ca]. 28-153 subfme. cr[cr0] subfmeo xer[so, ov] subfmeo. cr[cr0] xer[so, ov] subfze rt, ra, rb subtract (ra) from zero with carry-in. (rt) ? (ra) + xer[ca]. place carry-out in xer[ca]. 28-154 subfze. cr[cr0] subfzeo xer[so, ov] subfzeo. cr[cr0] xer[so, ov] xor ra, rs, rb xor (rs) with (rb). place result in ra. 28-171 xor. cr[cr0] xori ra, rs, im xor (rs) with ( 16 0 || im). place result in ra. 28-172 xoris ra, rs, im xor (rs) with (im || 16 0). place result in ra. 28-173 table b-6. arithmetic and logical instructions (continued) mnemonic operands function other registers changed page appendix b condition register logical instructions iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-31 appendix b ? cpu instr/cat b.7 condition register logical instructions condition register (cr) logical instructions allow the user to combine the results of several comparisons without incurring the overhead of conditional branching. these instructions can significantly improve code performance if multiple conditions are tested prior to making a branch decision. table b-7 summarizes the cr logical instructions. table b-7. condition register logical instructions mnemonic operands function other registers changed page crand bt, ba, bb and bit (cr ba ) with (cr bb ). place result in cr bt . 28-38 crandc bt, ba, bb and bit (cr ba ) with ? (cr bb ). place result in cr bt . 28-39 creqv bt, ba, bb equivalence of bit cr ba with cr bb . cr bt ? (cr ba cr bb ) 28-40 crnand bt, ba, bb nand bit (cr ba ) with (cr bb ). place result in cr bt . 28-41 crnor bt, ba, bb nor bit (cr ba ) with (cr bb ). place result in cr bt . 28-42 cror bt, ba, bb or bit (cr ba ) with (cr bb ). place result in cr bt . 28-43 crorc bt, ba, bb or bit (cr ba ) with ? (cr bb ). place result in cr bt . 28-44 crxor bt, ba, bb xor bit (cr ba ) with (cr bb ). place result in cr bt . 28-45 mcrf bf, bfa move cr field, (cr[crn]) (cr[crm]) where m bfa and n bf. 28-96 appendix b iop 480 cpu instructions by category branch instructions iop 480 data book r2.0 b-32 ? 2000 plx technology, inc. all rights reserved. b.8 branch instructions the architecture provides conditional and unconditional branches to any storage location. the conditional branch instructions test condition codes set previously and branch accordingly. conditional branch instructions may decrement and test the count register (ctr) as part of determination of the branch condition and may save the return address in the link register (lr). the target address for a branch may be a displacement from the current instruction address (cia), or may be contained in the lr or ctr, or may be an absolute address. table b-8. branch instructions mnemonic operands function other registers changed page b target branch unconditional relative. li (target ? cia) 6:29 nia cia + exts(li || 2 0) 28-20 ba branch unconditional absolute. li target 6:29 nia exts(li || 2 0) bl branch unconditional relative. li (target ? cia) 6:29 nia cia + exts(li || 2 0) (lr) cia + 4. bla branch unconditional absolute. li target 6:29 nia exts(li || 2 0) (lr) cia + 4. bc bo, bi, target branch conditional relative. bd (target ? cia) 16:29 nia cia + exts(bd || 2 0) ctr if bo 2 = 0. 28-21 bca branch conditional absolute. bd target 16:29 nia exts(bd || 2 0) ctr if bo 2 = 0. bcl branch conditional relative. bd (target ? cia) 16:29 nia cia + exts(bd || 2 0) ctr if bo 2 = 0. (lr) cia + 4. bcla branch conditional absolute. bd target 16:29 nia exts(bd || 2 0) ctr if bo 2 = 0. (lr) cia + 4. bcctr bo, bi branch conditional to address in ctr. using (ctr) at exit from instruction, nia ctr 0:29 || 2 0. ctr if bo 2 = 0. 28-26 bcctrl ctr if bo 2 = 0. (lr) cia + 4. bclr bo, bi branch conditional to address in lr. using (lr) at entry to instruction, nia lr 0:29 || 2 0. ctr if bo 2 = 0. 28-29 bclrl ctr if bo 2 = 0. (lr) cia + 4. appendix b comparison instructions iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-33 appendix b ? cpu instr/cat b.9 comparison instructions comparison instructions perform arithmetic and logical comparisons between two operands and set one of the eight condition code register fields based on the outcome of the comparison. table b-9 shows the comparison instructions supported by iop 480 cpu. table b-9. comparison instructions mnemonic operands function other registers changed page cmp bf, 0, ra, rb compare (ra) to (rb), signed. results in cr[crn], where n = bf. 28-33 cmpi bf, 0, ra, im compare (ra) to exts(im), signed. results in cr[crn], where n = bf. 28-34 cmpl bf, 0, ra, rb compare (ra) to (rb), unsigned. results in cr[crn], where n = bf. 28-35 cmpli bf, 0, ra, im compare (ra) to ( 16 0 || im), unsigned. results in cr[crn], where n = bf. 28-36 appendix b iop 480 cpu instructions by category rotate and shift instructions iop 480 data book r2.0 b-34 ? 2000 plx technology, inc. all rights reserved. b.10 rotate and shift instructions rotate and shift instructions rotate and shift operands which are stored in the general purpose registers. rotate instructions can also mask rotated operands. table b-10 lists iop 480 cpu rotate and shift instructions. table b-10. rotate and shift instructions mnemonic operands function other registers changed page rlwimi ra, rs, sh, mb, me rotate left lword immediate, then insert according to mask. r rotl((rs), sh) m mask(mb, me) (ra) (r m) ((ra) ? m) 28-121 rlwimi. cr[cr0] rlwinm ra, rs, sh, mb, me rotate left lword immediate, then and with mask. r rotl((rs), sh) m mask(mb, me) (ra) (r m) 28-122 rlwinm. cr[cr0] rlwnm ra, rs, rb, mb, me rotate left lword, then and with mask. r rotl((rs), (rb) 27:31 ) m mask(mb, me) (ra) (r m) 28-124 rlwnm. cr[cr0] slw ra, rs, rb shift left (rs) by (rb) 27:31 . n (rb) 27:31. r rotl((rs), n). if (rb) 26 = 0 then m mask(0, 31 ? n) else m 32 0. (ra) r m. 28-126 slw. cr[cr0] sraw ra, rs, rb shift right algebraic (rs) by (rb) 27:31 . n (rb) 27:31 . r rotl((rs), 32 ? n). if (rb) 26 = 0 then m mask(n, 31) else m 32 0. s (rs) 0. (ra) (r m) ( 32 s ? m). xer[ca] s ((r ? m) 0). 28-127 sraw. cr[cr0] srawi ra, rs, sh shift right algebraic (rs) by sh. n sh. r rotl((rs), 32 ? n). m mask(n, 31). s (rs) 0. (ra) (r m) ( 32 s ? m). xer[ca] s ((r ? m) 0). 28-128 srawi. cr[cr0] srw ra, rs, rb shift right (rs) by (rb) 27:31 . n (rb) 27:31 . r rotl((rs), 32 ? n). if (rb) 26 = 0 then m mask(n, 31) else m 32 0. (ra) r m. 28-129 srw. cr[cr0] appendix b cache control instructions iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-35 appendix b ? cpu instr/cat b.11 cache control instructions cache control instructions allow the user to indirectly control the contents of the data and instruction caches. the user may fill, flush, invalidate and zero blocks (16-byte lines) in the data cache. the user may also invalidate congruence classes in both caches and invalidate individual lines in the instruction cache. table b-11. cache control instructions mnemonic operands function other registers changed page dcba ra, rb speculatively establish the data cache block which contains the effective address (ra|0) + (rb). 28-46 dcbf ra, rb flush (store, then invalidate) the data cache block which contains the effective address (ra|0) + (rb). 28-48 dcbi ra, rb invalidate the data cache block which contains the effective address (ra|0) + (rb). 28-49 dcbst ra, rb store the data cache block which contains the effective address (ra|0) + (rb). 28-50 dcbt ra, rb load the data cache block which contains the effective address (ra|0) + (rb). 28-51 dcbtst ra,rb load the data cache block which contains the effective address (ra|0) + (rb). 28-52 dcbz ra, rb zero the data cache block which contains the effective address (ra|0) + (rb). 28-53 dccci ra, rb invalidate the data cache congruence class associated with the effective address (ra|0) + (rb). 28-55 dcread rt, ra, rb read either tag or data information from the data cache congruence class associated with the effective address (ra|0) + (rb). place the results in rt. 28-56 icbi ra, rb invalidate the instruction cache block which contains the effective address (ra|0) + (rb). 28-64 icbt ra, rb load the instruction cache block which contains the effective address (ra|0) + (rb). 28-65 iccci ra, rb invalidate instruction cache congruence class associated with the effective address (ra|0) + (rb). 28-67 icread ra, rb read either tag or data information from the instruction cache congruence class associated with the effective address (ra|0) + (rb). place the results in icdbdr. 28-69 appendix b iop 480 cpu instructions by category interrupt control instructions iop 480 data book r2.0 b-36 ? 2000 plx technology, inc. all rights reserved. b.12 interrupt control instructions the interrupt control instructions allow the user to move data between general purpose registers and the machine state register, return from interrupts and enable or disable maskable external interrupts. table b-12 shows the interrupt control instruction set. table b-12. interrupt control instructions mnemonic operands function other registers changed page mfmsr rt move from msr to rt, (rt) (msr). 28-100 mtmsr rs move to msr from rs, (msr) (rs). 28-105 rfci return from critical interrupt (pc) (srr2). (msr) (srr3). 28-119 rfi return from interrupt. (pc) (srr0). (msr) (srr1). 28-120 wrtee rs write value of rs 16 to the external enable bit (msr[ee]). 28-169 wrteei e write value of e to the external enable bit (msr[ee]). 28-170 appendix b processor management instructions iop 480 cpu instructions by category iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. b-37 appendix b ? cpu instr/cat b.13 processor management instructions the processor management instructions move data between gprs, sprs and dcrs in iop 480 cpu; these instructions also provide traps, system calls and synchronization controls. table b-13. processor management instructions mnemonic operands function other registers changed page eieio storage synchronization. all loads and stores that precede the eieio instruction complete before any loads and stores that follow the instruction access main storage. implemented as sync , which is more restrictive. 28-60 isync synchronize execution context by flushing the prefetch queue. 28-71 mcrxr bf move xer[0:3] into field crn, where n bf. cr[crn] (xer[so, ov, ca]). (xer[so, ov, ca]) 3 0. 28-97 mfcr rt move from cr to rt, (rt) (cr). 28-98 mfdcr rt, dcrn move from dcr to rt, (rt) (dcr(dcrn)). 28-99 mfspr rt, sprn move from spr to rt, (rt) (spr(sprn)). 28-101 mtcrf fxm, rs move some or all of the contents of rs into cr as specified by fxm field, mask 4 (fxm 0 ) || 4 (fxm 1 ) || ... || 4 (fxm 6 ) || 4 (fxm 7 ). (cr) ((rs) mask) (cr) ? mask). 28-103 mtdcr dcrn, rs move to dcr from rs, (dcr(dcrn)) (rs). 28-104 mtspr sprn, rs move to spr from rs, (spr(sprn)) (rs). 28-106 sc system call exception is generated. (srr1) (msr) (srr0) (pc) pc evpr 0:15 || x'0c00' (msr[we, pr, ee, pe, dr, ir]) 0 (msr[le]) (msr[ile]) 28-125 sync synchronization. all instructions that precede sync complete before any instructions that follow sync begin. when sync completes, all storage accesses initiated prior to sync are completed. 28-155 tw to, ra, rb trap exception is generated if, comparing (ra) with (rb), any condition specified by to is true. 28-163 twi to, ra, im trap exception is generated if, comparing (ra) with exts(im), any condition specified by to is true. 28-166 iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. c-1 appendix c ? code example c real code example ! ----------------------------------------------------------------------- ! name: init.asm ! ----------------------------------------------------------------------- ! this code is written for simulation debugging. therefore, lots of shortcuts ! are in place to speed up the simulation that arent needed for the actual ! silicon (such as skipping cache initialization). also, r10 is used only ! as an indication of progression through the code. #include appendix c real code example iop 480 data book r2.0 c-2 ? 2000 plx technology, inc. all rights reserved. addi r3,0,0 ! init the dcwr mtdcwr r3 addis r3,0,0x8000 ! init cache control registers ori r3,r3,0x0001 ! first and last region are cacheable or r3,r3,r3 ! two noops to force first cacheable ! fetch from middle of cache line or r3,r3,r3 mticcr r3 mtdccr r3 sync isync pastcacheinit: addi r10,0,0x0003 ! use r10 to help debug simulation ! ! other initialization code goes here ! ! initialize iop480 so it can read a 1 mb code area for sram spaces ! this requires enabling ma[17:0], by default only ma[12:0] are enabled. ! first copy iop480 register base address into r3 addis r3,0,0x5000 ! iop480 register base address hi ori r3,r3,0x0000 ! iop480 register base address lo ! use r4 as the working variable ! turn on ma17 (locctl.7) lwz r4, 0x84(r3) ! locctl is at offset 0x84 ori r4,r4,0x80 ! make bit 7 = 1 -- ma17 mode stw r4, 0x84(r3) ! locctl is at offset 0x84 ! turn on ma16:13 (lcs0brd.12 = 0) lwz r4, 0x100(r3) ! lcs0brd is at offset 0x100 andi. r4,r4,0xefff ! make bit 12 = 0 stw r4, 0x100(r3) ! lcs0brd is at offset 0x100 ! make sure above stores all complete before going on sync ! last thing, set local init status done bit (devinit.31) lwz r4, 0x80(r3) ! devinit is at offset 0x80 oris r4,r4,0x8000 ! make bit 31 = 1 stw r4, 0x80(r3) ! devinit is at offset 0x80 ! make sure above stores all complete before going on sync ! initialize on-chip uart ! simulation conditionally skips this step (use cache init again) ! addis r4, 0,cr_cacheinit@h ! cache init crunch address ! ori r4,r4,cr_cacheinit@l appendix c real code example iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. c-3 appendix c ? code example ! lwz r5, 0(r4) ! cmpi r5, 0 ! 0 = init uart; 1 = dont bother. addi r10,0,0x0004 ! use r10 to help debug simulation ! bne pastuartinit addi r10,0,0x0005 ! use r10 to help debug simulation andi. r8,0,0x0000 ori r9,0,0x00ff addis r4,r8,0x4000 ! iop480 uart base address hi ori r4,r4,0x0000 ! iop480 uart base address lo addi r10,0,0x0006 ! use r10 to help debug simulation ! recommended initialization procedure for the uart: ! first use these exact values, then program what you want. ! by not following these steps, simulation shows that the uart may ! not run properly. ori r5,r8,0x0000 ! initial brdh value stb r5, 0x10(r4) ! store byte to brdh ori r5,r8,0x0000 ! initial brdl value stb r5, 0x14(r4) ! store byte to brdl ori r5,r8,0x0078 ! initial spls value stb r5, 0x00(r4) ! store byte to spls ori r5,r8,0x00ff ! initial sphs value stb r5, 0x08(r4) ! store byte to sphs ori r5,r8,0x0000 ! initial spctl value stb r5, 0x18(r4) ! store byte to spctl ori r5,r8,0x0000 ! initial sprc value stb r5, 0x1c(r4) ! store byte to sprc ori r5,r8,0x0000 ! initial sptc value stb r5, 0x20(r4) ! store byte to sptc ! end of exact uart initialization ! now uart should be ready to be programmed with real values ! for simulation make baud rate as fast as possible ori r5,r8,0x0000 ! initial brdh value stb r5, 0x10(r4) ! store byte to brdh ori r5,r8,0x0001 ! initial brdl value stb r5, 0x14(r4) ! store byte to brdl ori r5,r8,0x0008 ! initial spctl value stb r5, 0x18(r4) ! store byte to spctl ori r5,r8,0x00ff ! initial spls value stb r5, 0x00(r4) ! store byte to spls ori r5,r8,0x00fe ! initial sphs value stb r5, 0x08(r4) ! store byte to sphs ori r5,r8,0x0008 ! initial spctl value appendix c real code example iop 480 data book r2.0 c-4 ? 2000 plx technology, inc. all rights reserved. stb r5, 0x18(r4) ! store byte to spctl ori r5,r8,0x00b0 ! initial sprc value stb r5, 0x1c(r4) ! store byte to sprc ori r5,r8,0x00b0 ! initial sptc value stb r5, 0x20(r4) ! store byte to sptc ! clear spls one more time !ori r5,r8,0x00ff ! initial spls value !stb r5, 0x00(r4) ! store byte to spls !pastuartinit: addi r10,0,0x0007 ! use r10 to help debug simulation ! now branch to main test code ba 0xfff80000 ! branch to test case addi r10,0,0xf00d ! use r10 to help debug simulation epilog(init) .space 4 .data data: iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. d-1 appendix d?general info d general information d.1 ordering instructions the iop 480 is a 32-bit 33-mhz pci bus master i/o accelerator featuring advanced data pipe architecture technology, which includes two dma engines, programmable target and initiator data transfer modes, and pci messaging functions. the iop 480 offers 3.3v, 5v tolerant pci and local signaling supports universal pci adapter designs, 3.3v core, low-power cmos offered in two package options, a 208-pin pqfp and 225-pin (ball) pbga. the device is designed to operate at industrial temperature range. the iop 480 is also available in two local bus speed options?60 mhz or 66 mhz. d.2 united states and international representatives, and distributors a list of plx technology, inc., representatives and distributors can be found at http://www.plxtech.com. d.3 technical support plx technology, inc., technical support information is listed at http://www.plxtech.com; or call 408 774-9060 or 800 759-3735. table d-1. available packages package local bus speed (max) ordering part number 208-pin pqfp 60 mhz iop 480?aa60pi 225-pin pbga iop 480?aa60bi 208-pin pqfp 66 mhz iop 480?aa66pi 225-pin pbga iop 480?aa66bi iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-1 index index a access burst 1-2, 2-2, 2-3, 2-4, 2-10, 4-1, 5-4, 12-1, 12-3, 12-5, 12-9, 12-15, 12-19, 12-22, 12-32, 12-42, 12-48, 17-1 configuration endian, swapping 2-11 local bus 11-1 local-to-pci 3-1, 5-1, 17-36 pci 3-1, 5-4, 10-14, 13-4 endian swapping 2-11 i/o direct master 17-35 direct slave 4-1 local-to-pci 3-1, 5-1, 17-36 pci 3-1, 5-4, 5-5 power state 17-17 memory cpu byte ordering 24-17 cpu control 23-5 cpu management 27-4 cpu storage attributes 24-1 cpu sync 24-29 direct master 5-2, 17-35 direct slave 4-4 local-to-pci 3-1, 5-1, 17-34 pci 4-1, 5-4, 7-10, 10-14, 17-1, 17-12, 17-13 pci bus 1-4 protection 27-9 ad 18-5 ad[31:0] 18-4, 20-7, 20-8 add 28-7 add. 28-7 addc 28-8 addc. 28-8 addco 28-8 addco. 28-8 adde 28-9 adde. 28-9 addeo 28-9 addeo. 28-9 addi 28-10 addic 28-11 addic. 28-12 addis 28-13 addme 28-14 addme. 28-14 addmeo 28-14 addmeo. 28-14 addo 28-7 addo. 28-7 address/data/parity 2-2 ? 2-3 dp[3:0] 2-3 lad[31:0] 2-2 addressing 24-1 addressing modes 23-8 addze 28-15 addze. 28-15 addzeo 28-15 addzeo. 28-15 ads# 18-12, 20-8 advanced data pipe architecture see data pipe architecture ale 18-12, 20-7 alignment 24-11 bus transfers 6-1 cpu feature 24-1 data 2-15 error 11-22 error exception 11-24 exception 25-6, 25-12 exception summary 11-24 exception type 11-12, 11-13 exceptions 11-10 exceptions summary 24-12 little endian operation 24-12 little endian requirements 24-17 powerpc 24-12 prefetching 4-7 settings during error exceptions 11-24 unaligned transfers 4-7 and 28-16 and. 28-16 andc 28-17 andc. 28-17 andi. 28-18 andis. 28-19 arbiter see local bus internal arbiter or pci bus internal arbiter arbitration 2-5 boff# 2-5 bus 3-3 lholdack0/ldreq 2-5 architecture to bflr iop 480 data book r2.0 index-2 ? 2000 plx technology, inc. all rights reserved. lholdack1/breq 2-5 lholdreq0/lholdack 2-5 lholdreq1 2-5 local arbitration signal directions 2-5 round-robin 9-1, 17-29, 17-31 architecture boundary scan 26-8, 26-10 bridge 2-1 cpu 11-28, 23-1 device/bus dependent 5-7 distributed processing 1-4 driver 13-1 embedded applications 23-1 i 2 o13-1 notes 28-1 ? 28-173 operating environment 23-2 pci bus dependent 5-7 powerpc 11-28, 23-1, 23-2, 23-7, 24-2, 24-6, 24-9, 24-13, 24-14, 24-16, 24-18, 24-19, 24-24, 24-27, 24-28, 24-29, 24-30, 24-31, 24-34, 25-5, 26-8, 27-4, 27-5, 27-13, 28-4 development tools 1-2 layered 23-1 user instruction set 23-2, 23-3 user instruction set 1-2 risc 2-1, 23-1 see also data pipe architecture virtual environment 23-2 write-only 1-6 arithmetic compare 24-8 asynchronous interrupts, defined 11-9 asynchronous serial port unit see serial port operation atomic, locked operations 4-5 b b 28-20 ba 28-20 bc 28-21 bca 28-21 bcctr 28-26 bcctrl 28-26 bcl 28-21 bcla 28-21 bclr 28-29 bclrl 28-29 bctr 28-27 bctrl 28-27 bdnz 28-22 bdnza 28-22 bdnzf 28-22 bdnzfa 28-22 bdnzfl 28-22 bdnzfla 28-22 bdnzflr 28-30 bdnzflrl 28-30 bdnzl 28-22 bdnzla 28-22 bdnzlr 28-30 bdnzlrl 28-30 bdnzt 28-22 bdnzta 28-22 bdnztl 28-22 bdnztla 28-22 bdnztlr 28-30 bdnztlrl 28-30 bdz 28-22 bdza 28-22 bdzf 28-22 bdzfa 28-22 bdzfl 28-22 bdzfla 28-22 bdzflr 28-30 bdzflrl 28-30 bdzl 28-22 bdzla 28-22 bdzlr 28-30 bdzlrl 28-30 bdzt 28-23 bdzta 28-23 bdztl 28-23 bdztla 28-23 bdztlr 28-30 bdztlrl 28-30 beq 28-23 beqa 28-23 beqctr 28-27 beqctrl 28-27 beql 28-23 beqlr 28-30 beqlrl 28-30 bf 28-23 bfa 28-23 bfctr 28-27 bfctrl 28-27 bfl 28-23 bfla 28-23 bflr 28-30 bflrl to branching iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-3 index bflrl 28-30 b-form a-38 bge 28-23 bgea 28-23 bgectrl 28-27 bgel 28-23 bgela 28-23 bgelr 28-31 bgelrl 28-31 bgrctr 28-27 bgt 28-23 bgta 28-23 bgtctr 28-27 bgtctrl 28-27 bgtl 28-23 bgtla 28-23 bgtlr 28-31 bgtlrl 28-31 big endian byte ordering 2-11 swapping 2-13 bigend 17-30 bist interrupt 11-4 bl 28-20 bla 28-20 blast# 18-12, 20-8 ble 28-24 blea 28-24 blectr 28-27 blectrl 28-27 blel 28-24 blela 28-24 blelr 28-31 blelrl 28-31 block dma mode pci latency timer 7-2, 7-6, 7-9 blr 28-30 blrl 28-30 blt 28-24 blta 28-24 bltctr 28-27 bltctrl 28-27 bltl 28-24 bltla 28-24 bltlr 28-31 bltlrl 28-31 bne 28-24 bnea 28-24 bnectr 28-27 bnectrl 28-27 bnel 28-24 bnela 28-24 bnelr 28-31 bnelrl 28-31 bng 28-24 bnga 28-24 bngctr 28-27 bngctrl 28-27 bngl 28-24 bngla 28-24 bnglr 28-31 bnglrl 28-31 bnl 28-24 bnla 28-24 bnlctr 28-28 bnlctrl 28-28 bnll 28-24 bnlla 28-24 bnllr 28-31 bnllrl 28-31 bns 28-25 bnsa 28-25 bnsctr 28-28 bnsctrl 28-28 bnsl 28-25 bnsla 28-25 bnslr 28-31 bnslrl 28-31 bnu 28-25 bnua 28-25 bnuctr 28-28 bnuctrl 28-28 bnul 28-25 bnula 28-25 bnulr 28-31 bnulrl 28-31 boff# 18-12, 20-7 2-5 branch prediction 24-23, b-6 branching control 24-21 aa field on unconditional branches 24-21 bi field on conditional branches 24-22 bo field on conditional branches 24-22 brdh to cache iop 480 data book r2.0 index-4 ? 2000 plx technology, inc. all rights reserved. branch prediction 24-23 speculative accesses 24-24 brdh 22-6 brdl 22-6 breq 18-17, 20-8 bridge architecture 2-1 bso 28-25 bsoa 28-25 bsoctr 28-28 bsoctrl 28-28 bsol 28-25 bsola 28-25 bsolr 28-32 bsolrl 28-32 bt 28-25 bta 28-25 btctr 28-28 btctrl 28-28 bterm 18-12 bterm# 20-8 btl 28-25 btla 28-25 btlr 28-32 btlrl 28-32 buffer loading derating, pci 19-2 buffer types, i/o 18-1 bun 28-25 buna 28-25 bunctr 28-28 bunctrl 28-28 bunl 28-25 bunla 28-25 bunlr 28-32 bunlrl 28-32 burst access 1-2, 2-2, 2-3, 2-4, 2-10, 4-1, 5-4, 12-1, 12-3, 12-5, 12-9, 12-15, 12-19, 12-22, 12-32, 12-42, 12-48, 17-1 bus accesses 2-15 byte enable and coding 2-16 byte lane contents 2-16 data transfer 2-16 data transfer control 2-16 arbitration 3-3 protocol, pci 3-3 region descriptors 2-10 ? 2-11 burst boundaries with bterm enable=0 2-10 burst boundaries with bterm enable=1 2-11 direct slave 2-10 dma burst 2-10 wait state control 2-11 see also local or pci bus width 2-15 c c/be# 18-5 c/be[3:0]# 18-4, 20-7, 20-8 c0count 17-64 c0csr 17-64 c0descptr 17-65 c0locadr 17-64 c0mode 17-63 ? 17-64 c0pcihadr 17-65 c0pciladr 17-64 c0thres 17-65 c1count 17-68 c1csr 17-68 c1descptr 17-69 c1locadr 17-68 c1mode 17-67 ? 17-68 c1pcihadr 17-69 c1pciladr 17-68 c1thres 17-69 c2count 17-72 c2csr 17-72 c2destadr 17-72 c2mode 17-71 c2srcadr 17-72 cache data cacheability control 25-5 coherency 25-5 debugging 25-7, 25-10 overview 25-4 write strategies 25-4 instructions 25-5 cacheability control 25-3 coherency 25-4 dac debug events 26-7 dcu 25-6 debugging 25-7, 25-9 cap_ptr to cpu iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-5 index icu 25-6 line locking 25-11 see also cpu cache operations cap_ptr 17-14 cas[3:0]# 18-3, 18-9, 20-7 cdbcr 25-7, 29-4 cfgba 17-36 change recording 27-9 cint 11-6, 18-3, 18-18, 20-8 cint critical interrupt 11-6 circular 13-1 fifos 13-1 clear count mode 7-1, 7-3, 7-9, 17-63, 17-64, 17-67, 17-68 clk 18-1, 18-4, 20-7 clocks input 19-1 clrlslwi 28-122 clrlslwi. 28-122 clrlwi 28-122 clrlwi. 28-122 clrrwi 28-122 clrrwi. 28-122 cmp 28-33 cmpi 28-34 cmpl 28-35 cmpli 28-36 cmplw 28-35 cmplwi 28-36 cmpw 28-33 cmpwi 28-34 cntlzw 28-37 cntlzw. 28-37 code see real code example compactpci hot swap 1-1, 1-7, 14-1 ? 14-4 capable 14-1 controlling connection processes 14-1 ? 14-4 friendly 14-1 levels of compatibility 14-1 overview 14-1 pins 18-7 ready 14-1 compactpci specification xxxvii compare arithmetic 24-8 logical 24-8 condition register (cr) 23-8 condition register (cr) 24-7 configuration access local bus 11-1 local-to-pci 3-1, 5-1, 17-36 pci 3-1, 5-4, 10-14, 13-4 cycles dmcfga 17-36 example, type 0 5-5 power management 16-1, 16-2 timing diagrams 4-8 ? 5-9, 5-16, 5-17 type 0 1-2, 1-5, 5-1, 5-5, 17-1, 17-36 type 1 1-2, 1-5, 5-1, 5-5, 17-1, 17-36 hot swap 14-1 consecutive pci retries (256) interrupt 11-2 context synchronization 24-29 control/status 2-3 ? 2-5 ads# 2-3 ale 2-3 blast# 2-3 bterm# 2-4 lbe[3:0]# 2-3 llock# 2-5 lwr# 2-3 ready data transfers 2-4 ready# 2-3 wait# 2-5 controller, memory see memory controller conventions, data assignment xxxviii cpu block diagram 23-3 bootup cycle timing diagrams 6-3 bus interface 6-1 ? 6-2 accessing local bus 6-1 accessing pci bus 6-1 accessing spu 6-1 alignment 6-1 ? 6-2 initialization 6-1 overview 6-1 cache operations 25-1 ? 25-15 cache control and debugging features 25-7 ? 25-10 dcu performance 25-12 ? 25-14 icu and dcu organization 25-1 ? 25-2 icu and dcu performance modeling 25-14 ? 25-15 icu overview 25-2 ? 25-5 cr to dack1# iop 480 data book r2.0 index-6 ? 2000 plx technology, inc. all rights reserved. instructions 25-5 ? 25-7 line locking 25-11 ? 25-12 clock and test/debug pins 18-10 ? 18-11 debugging and jtag facilities 26-1 ? 28-173 debug events 26-2 debug interface 26-8 ? 26-10 debug modes 26-1 debug registers 26-2 ? 26-8 development tool support 26-1 processor control 26-2 processor status 26-2 features 23-1 instruction formats a-36 ? a-40 instruction set 28-1 ? 28-173 alphabetical listing 28-1 ? 28-3 formats 28-4 listing 28-6 ? 28-173 portability 28-4 pseudocode 28-4 ? 28-6 register usage 28-6 instruction summary a-1 ? a-40 instruction summary by opcode a-30 ? a-36 instructions by category b-1 ? b-37 arithmetic and logical instructions b-27 ? b-30 assembler extended mnemonics b-6 ? b-22 branch instructions b-32 branch interrupt control instructions b-36 cache control instructions b-35 categories b-1 comparison instructions b-33 condition register logical instructions b-31 instructions specific to powerpc embedded controllers b-2 ? b-3 privileged instructions b-4 ? b-5 processor management instructions b-37 rotate and shift instructions b-34 storage reference instructions b-23 ? b-26 instructions, alphabetical including extended mnemonics a-1 ? a-29 memory access 23-5, 24-1, 24-17, 24-29, 27-4 memory management 27-1 ? 27-14 access protection 27-9 ? 27-13 address translation 27-1 ? 27-2 overview 27-1 real-mode storage attribute control 27-13 ? 27-14 recording page references and changes 27-9 translation lookaside buffer 27-2 ? 27-7 lookaside buffer management 27-8 lookaside buffer-related exceptions 27-7 ? 27-8 organization 23-3 ? 23-8 overview 23-1 ? 23-8 powerpc architecture 23-2 implementation 23-2 programming model alignment 24-11 ? 24-12 branching control 24-21 ? 24-24 byte ordering 24-13 ? 24-21 data types 24-11 ? 24-12 instruction processing 24-21 instruction set 24-31 ? 24-35 memory organization 24-1 privileged mode operation 24-27 ? 24-28 register summary 24-1 ? 24-11 synchronization 24-28 ? 24-31 programming model speculative accesses 24-24 ? 24-27 register summary 29-1 ? 29-48 alphabetical listing 29-3 ? 29-48 device control registers 29-3 general purpose registers 29-1 machine state register (msr) and condition register (cr) 29-1 reserved fields 29-1 reserved registers 29-1 special purpose registers 29-1 ? 29-2 cr 29-6 crand 28-38 crandc 28-39 crclr 28-45 creqv 28-40 critical exceptions, defined 11-10 critical interrupt pin 11-19 crmove 28-43 crnand 28-41 crnor 28-42 crnot 28-42 cror 28-43 crorc 28-44 crset 28-40 crxor 28-45 ctr 24-4, 29-7 d dac1 26-7, 29-8 dack0# 18-12, 20-7 dack1# 18-12, 20-7 dack2# to debugging iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-7 index dack2# 18-12, 20-7 data address compare register (dac1) 26-7, 29-8 alignment 2-15, 24-11 direct slave local byte enable methods 2-15, 4-7 iop 480, as a local bus master 2-15 iop 480, as a local bus slave 2-15 storage exception 11-21 tlb miss exception 11-27 types 23-7, 24-11 data address compare (dac) dac1 register 29-8 debug status register 26-6 event 26-3 exception 28-47, 28-48, 28-49, 28-50, 28-51, 28-52, 28-54, 28-55, 28-57, 28-64, 28-66, 28-68, 28-70 exception type 11-12, 11-28 read debug event 29-11 read enable 29-9 register 29-2 size 29-10 write debug event 29-11 write enable 29-9 data assignment conventions xxxviii data cache cacheability control 25-5 cacheability register (dccr) 27-13 coherency 25-5 debugging 25-7, 25-10 instructions 25-6 locking lines 25-11 overview 25-4 unlocking lines 25-11 write strategies 25-4 write-through register (dcwr) 27-13 data communications design 1-7 ? 1-8 data machine check handling 11-21 data pipe architecture 1-2 ? 1-3 local-to-local dma 1-2, 1-5 pci latency timer 1-2 plx advancement d-1 plx proprietary technology 1-1 ring management 1-2 scatter/gather 1-2 protocols 1-5 unaligned transfer 1-2 vital product data (vpd) 1-3 data transfer mechanisms iop 480 supports 1-4 dbcr 26-3, 29-9 dbsr 26-5 dcba 25-6, 28-46 dcbf 25-6, 25-11, 28-48 dcbi 25-6, 28-49 dcbst 25-6, 28-50 dcbt 28-51 25-7 dcbtst 25-7, 28-52 dcbz 25-7, 25-11, 28-53 dccci 25-7, 28-55 dccr 27-13, 29-12 dcread 25-7, 28-56 dcu cacheability control 25-5 coherency 25-5 debugging 25-10 instructions 25-6 locking lines 25-11 unlocking lines 25-11 write strategies 25-4 dcwr 27-13, 29-14 dear 11-19, 29-16 debug control register (dbcr) 26-3 debugging boundary scan chain 26-10 cache debug control register 25-8, 29-4 cache debug data register 28-69 control register 29-9 cpu clock 18-10 miscellaneous signals 18-1 organization 23-3 test/debug pins 18-10 data cache operations 25-7 dcba 28-47 dcbf 28-48 dcbi 28-49 dcbst 28-50 dcbt 28-51 dcbtst 28-52 dcbz 28-54 dcccci 28-55 dcread 28-56, 28-57 decode to direct master iop 480 data book r2.0 index-8 ? 2000 plx technology, inc. all rights reserved. dcu 25-10 development tools 1-5, 26-1 event interrupts 1-3 events 26-2 exception handling 11-28 exceptions 11-8, 11-10, 11-12, 11-13, 11-19, 11-28, 28-47, 28-48, 28-49, 28-50, 28-51, 28-52, 28-54, 28-55, 28-57, 28-64, 28-66, 28-68, 28-70 branch taken 11-28 dac 11-28 iac 11-28 instruction completion 11-28 non-critical exceptions 11-28 trap 11-28 unconditional 11-28 facilities 23-6 icbi 28-64 icbt 28-66 iccci 28-68 icread 28-69 icu 25-9 instructions 25-6 instruction tool 28-56, 28-69 interfaces 26-8 interfaces, jtag test access port 26-8 interrupt-causing instructions 24-26 interrupts 23-7, 24-9 jtag 23-3, 23-7 interface 23-1 port 1-1 machine state register (msr) 11-14, 24-9, 24-10, 29-25 memory management 23-1 modes 23-6 ? 23-7, 26-1 external 26-1 internal 26-1 powerpc 1-3 processor control 26-2 features 10-10 status 26-2 registers 26-2 after reset 10-9 resolving debug cache problems 25-7 see also cpu debugging and jtag facilities serial port 1-1 serial uart 1-3 simulation c-1 ? c-4 software tools 1-4 sprs 23-7, 24-2, 24-3, 29-1 status register 29-11 testing 1-3 timer 1-3 trap 28-163 ? 28-164, 28-166 ? 28-167 trap instructions 11-25 tw 28-163 twi 28-166 use of isync 24-30 decode address enable bit 17-14 dmpbam 17-35 enable bit 13-4 eromrr 17-34 i/o 5-1 instruction flow 25-3 local address, remapped address bits 5-4 memory 5-1 queue location 24-21 range 4-2 risc processor core 23-3 stage in pipeline 24-18 decoupling capacitors, use of 19-1 delayed read mode pci delayed read mode 17-30 development tools 1-5 device control registers (dcrs) 23-8, 24-11 devinit 17-26 devsel# 18-4, 20-8 dfltbrd 17-54 ? 17-55 d-form a-38 diagrams, timing see timing diagrams reference list direct master data transfer mechanism 1-4 data transfer mode, supported by iop 480 1-1, 1-2 i/o access 17-35 iop 480 supports 1-3, 1-4 local bus interface introduction 2-1 ? 2-2 memory decode 5-1 operation 5-1 ? 5-18 deadlock conditions 5-6 ? 5-7 internal fifos 5-2 ? 5-3 memory write and invalidate 5-6 pci configuration access 5-4 ? 5-5 dual address cycle 5-5 i/o access 5-4 memory access 5-4 target abort 5-6 timing diagrams 5-10 ? 5-18 direct slave to electrical specifications iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-9 index prefetching, 4 kb limit 5-4 registers 17-34 ? 17-36 transfers, supported by iop 480 1-5 direct slave command codes 3-1 data transfer mechanism 1-4 data transfer mode, supported by iop 480 1-1, 1-2 i/o access 4-1 iop 480 supports 1-4 local bus interface introduction 2-1 ? 2-2 memory access 4-4 methods, local byte enable 2-15, 4-7 operation 4-1 ? 4-28 alignment 4-7 example 4-7 exclusive accesses 4-5 internal fifos 4-4 local bus byte enables 4-6 pci r2.2 delayed read mode 4-5 read ahead mode 4-5 priority 4-6 ? 4-7 registers, discussion 4-1 ? 4-3 timing diagrams 4-12 ? 4-28 transfer 4-5 ? 4-6 pci latency timer 1-2 prefetching 4-7 prefetching timing diagram 4-28 read ahead mode 4-1 timing diagrams 3-2 divw 28-58 divw. 28-58 divwo 28-58 divwo. 28-58 divwu 28-59 divwu. 28-59 divwuo 28-59 divwuo. 28-59 dma block mode, pci latency timer 7-2, 7-6, 7-9 clear count mode 7-1, 7-3, 7-9, 17-63, 17-64, 17-67, 17-68 local-to-local 1-2, 1-5, 7-1, 7-10, 7-11 controller 8-1 timing diagram 7-23 master command codes 3-1 operation 7-1 ? 7-27 channel 2 7-10 ? 7-13 channels 0 and 1 7-1 ? 7-9 registers 17-1, 17-2, 17-8, 17-9, 17-12, 17-63 ? 17-72 ring management 1-5, 7-8 scatter/gather 7-1, 7-3, 7-4, 7-7, 7-8, 7-18, 7-19, 11-2, 11-5, 17-63, 17-64, 17-67, 17-68 unaligned transfer 7-13 unaligned transfer timing diagram 7-22 dma interrupts 11-2, 11-5 dmcfga 17-36 dmdac 17-36 dmlbai 17-36 dmlbam 17-34 dmpaf# 18-2, 18-14, 20-7 dmpbam 17-35 dmrr 17-34 documentation, supplemental xxxvii doorbell register interrupts 11-8 dp[3:0] 18-2, 18-8, 18-13, 20-7 drambase 17-53 drambrd 17-48 ? 17-49 dramctl 17-50 draminit 17-51 dramrange 17-53 dramtim 17-52 ? 17-53 dreq0# 18-13, 20-7 dreq1# 18-13, 20-7 dreq2# 18-13, 20-7 driver loading derating, local bus 19-2 dual address cycle (dac) block dma mode 7-3 command type 7-9 iop 480 supports 1-3 scatter/gather dma 7-4 supported by iop 480 1-1, 5-1, 5-5, 7-1 e early power 1-7 eecs 18-7, 20-7 eedata 18-2, 18-7, 20-7 eesk 18-2, 18-7, 20-7 eieio 28-60 electrical specifications 19-1 ? 19-3 absolute maximum ratings 19-2 ac electrical characteristics 19-1 ale output delay from the local clock 19-1, 19-2 capacitance 19-2 electrical characteristics over operating range 19-3 endian mode to extended mnemonics iop 480 data book r2.0 index-10 ? 2000 plx technology, inc. all rights reserved. local bus driver loading derating 19-2 operating ranges 19-2 package thermal resistance 19-3 pci buffer loading derating 19-2 endian mode powerpc 24-12 endian swapping 2-11 ? 2-15 big endian 2-13 cpu big endian byte ordering 2-13 cpu little endian byte ordering 2-15 example 2-11 internal iop 480 cpu 2-11 ? 2-15 lower byte lanes 2-12 upper byte lanes 2-12 endian, swapping configuration register access 2-11 direct master register access 2-11 direct slave access 2-11 dma access 2-11 enum# 18-2, 18-7, 18-10, 20-7 eot0# 18-2, 18-13, 20-7 eot1# 18-2, 18-13, 20-7 eot2# 20-7 eqv 28-61 eqv. 28-61 eromba 17-33 eromrr 17-33 esr 29-17 evpr 11-17, 29-18 exception, defined 11-8 exception-handling registers, general 11-13 exceptions alignment exception summary 24-12 fit 11-26 handling msr bits 24-27 pit 11-26 registers during alignment error 11-24 critical interrupt 11-19 debug exceptions 11-28 external interrupts 11-23 fit interrupt 11-26 machine check 11-20, 11-21 pit interrupt 11-26 program exceptions 11-25 system call 11-25 watchdog interrupt 11-27 see also interrupts and exceptions srr0-srr1 (non-critical) 11-15 srr2-srr3 (critical) 11-15 execution synchronization 24-30 expansion rom space 4-1 extended mnemonics 24-34 addi 28-10 addic 28-11 addic. 28-12 addis 28-13 alphabetical listing b-6 bc, bca, bcl, bcla 28-22 bcctr, bcctrl 28-27 bclr, bclrl 28-30 bctr 28-27 bctrl 28-27 bdnz 28-22 bdnza 28-22 bdnzf 28-22 bdnzfa 28-22 bdnzfkr 28-30 bdnzfl 28-22 bdnzfla 28-22 bdnzflrl 28-30 bdnzl 28-22 bdnzla 28-22 bdnzlr 28-30 bdnzlrl 28-30 bdnzt 28-22 bdnzta 28-22 bdnztl 28-22 bdnztla 28-22 bdnztlr 28-30 bdnztlrl 28-30 bdz 28-22 bdza 28-22 bdzf 28-22 bdzfa 28-22 bdzfl 28-22 bdzfla 28-22 bdzflr 28-30 bdzflrl 28-30 bdzl 28-22 bdzla 28-22 bdzlr 28-30 bdzlrl 28-30 bdzt 28-23 bdzta 28-23 bdztl 28-23 bdztla 28-23 bdztlr 28-30 extended mnemonics to extended mnemonics iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-11 index bdztlrl 28-30 beq 28-23 beqa 28-23 beqctr 28-27 beqctrl 28-27 beql 28-23 beqlr 28-30 beqlrl 28-30 bf 28-23 bfa 28-23 bfctr 28-27 bfctrl 28-27 bfl 28-23 bfla 28-23 bflr 28-30 bflrl 28-30 bge 28-23 bgea 28-23 bgectr 28-27 bgectrl 28-27 bgel 28-23 bgela 28-23 bgelr 28-31 bgelrl 28-31 bgt 28-23 bgta 28-23 bgtctr 28-27 bgtctrl 28-27 bgtl 28-23 bgtla 28-23 bgtlr 28-31 bgtlrl 28-31 ble 28-24 blea 28-24 blectr 28-27 blectrl 28-27 blel 28-24 blela 28-24 blelr 28-31 blelrl 28-31 blr 28-30 blrl 28-30 blt 28-24 blta 28-24 bltctr 28-27 bltctrl 28-27 bltl 28-24 bltla 28-24 bltlr 28-31 bltlrl 28-31 bne 28-24 bnea 28-24 bnectr 28-27 bnectrl 28-27 bnel 28-24 bnela 28-24 bnelr 28-31 bnelrl 28-31 bng 28-24 bnga 28-24 bngctr 28-27 bngctrl 28-27 bngl 28-24 bngla 28-24 bnglr 28-31 bnglrl 28-31 bnl 28-24 bnla 28-24 bnlctr 28-28 bnlctrl 28-28 bnll 28-24 bnlla 28-24 bnllr 28-31 bnllrl 28-31 bns 28-25 bnsa 28-25 bnsctr 28-28 bnsctrl 28-28 bnsl 28-25 bnsla 28-25 bnslr 28-31 bnslrl 28-31 bnu 28-25 bnua 28-25 bnuctr 28-28 bnuctrl 28-28 bnul 28-25 bnula 28-25 bnulr 28-31 bnulrl 28-31 bso 28-25 bsoa 28-25 bsoctr 28-28 bsoctrl 28-28 bsol 28-25 bsola 28-25 bsolr 28-32 bsolrl 28-32 bt 28-25 extended mnemonics to extended mnemonics iop 480 data book r2.0 index-12 ? 2000 plx technology, inc. all rights reserved. bta 28-25 btctr 28-28 btctrl 28-28 btl 28-25 btla 28-25 btlr 28-32 btlrl 28-32 bun 28-25 buna 28-25 bunctr 28-28 bunctrl 28-28 bunl 28-25 bunla 28-25 bunlr 28-32 bunlrl 28-32 clrlslwi 28-122 clrlslwi. 28-122 clrlwi 28-122 clrlwi. 28-122 clrrwi 28-122 clrrwi. 28-122 cmp 28-33 cmpi 28-34 cmpl 28-35 cmpli 28-36 cmplw 28-35 cmplwi 28-36 cmpw 28-33 cmpwi 28-34 crclr 28-45 creqv 28-40 crmove 28-43 crnor 28-42 crnot 28-42 cror 28-43 crset 28-40 crxor 28-45 extlwi 28-123 extlwi. 28-123 extrwi 28-123 extrwi. 28-123 inslwi 28-121 inslwi. 28-121 insrwi 28-121 insrwi. 28-121 la 28-10 li 28-10 lis 28-13 mfcdbcn 28-102 mfctr 28-102 mfdac 28-102 mfdbcl 28-102 mfdbsr 28-102 mfdbsrs 28-102 mfdccr 28-102 mfdcwr 28-102 mfdear 28-102 mfesr 28-102 mfevpr 28-102 mflac1 28-102 mflccr 28-102 mflcdbdr 28-102 mflr 28-102 mfplt 28-102 mfpvr 28-102 mfsgr 28-102 mfsler 28-102 mfspr 28-102 mfsprg0 28-102 mfsprg1 28-102 mfsprg2 28-102 mfsprg3 28-102 mftcr 28-102 mftsr 28-102 mfxer 28-102 mptvr 28-107 mr 28-115 mr. 28-115 mtcdbcr 28-107 mtcr 28-103 mtcrf 28-103 mtctr 28-107 mtdac1 28-107 mtdbcr 28-107 mtdbsr 28-107 mtdccr 28-107 mtdcwr 28-107 mtesr 28-107 mtevpr 28-107 mtiac1 28-107 mticcr 28-107 mticdbdr 28-107 mtlr 28-107 mtpit 28-107 mtsear 28-107 mtsgr 28-107 mtsler 28-107 mtspr 28-107 mtsprg1 28-107 mtsprg2 28-107 external interrupts to extsh. iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-13 index mtsprg3 28-107 mtsrr0 28-107 mtsrr1 28-107 mtsrr2 28-107 mtsrr3 28-107 mttcr 28-107 mttsprg0 28-107 mttsr 28-107 mttxer 28-107 nop 28-117 nor, nor. 28-114 not 28-114 not. 28-114 or, or. 28-115 ori 28-117 rlwimi, rlwimi. 28-121 rlwinm, rlwinm. 28-122 rlwnm, rlwnm. 28-124 rotlw 28-124 rotlw. 28-124 rotlwi 28-123 rotlwi. 28-123 rotrwi 28-123 rotrwi. 28-123 slwi 28-123 slwi. 28-123 srwi 28-123 srwi. 28-123 sub 28-149 sub. 28-149 subc 28-150 subc. 28-150 subco 28-150 subco. 28-150 subf, subf., subfo, subfo. 28-149 subfc, subfc., subfco, subfco. 28-150 subi 28-10 subic 28-11 subic. 28-12 subis 28-13 subo 28-149 subo. 28-149 tblrehi 28-158 tblrelo 28-158 tblwehi 28-162 tblwelo 28-162 tlbre 28-158, 28-162 trap 28-165 tw 28-165 tweq 28-165 tweqi 28-168 twge 28-165 twgei 28-168 twgle 28-165 twgt 28-165 twgti 28-168 twi 28-168 twle 28-165 twlei 28-168 twlgei 28-168 twlgt 28-165 twlgti 28-168 twlle 28-165 twllei 28-168 twllt 28-165 twllti 28-168 twlng 28-165 twlngi 28-168 twlnl 28-165 twlnli 28-168 twlt 28-165 twlti 28-168 twne 28-165 twnei 28-168 twng 28-165 twngi 28-168 twnl 28-165 twnli 28-168 external interrupts dma 11-23 exception 11-23 jtag port 11-23 pins 11-23 serial port 11-23 extlwi 28-123 extlwi. 28-123 extrwi 28-123 extrwi. 28-123 extsb 28-62 extsb. 28-62 extsh 28-63 extsh. 28-63 fifo to i/o buffer types iop 480 data book r2.0 index-14 ? 2000 plx technology, inc. all rights reserved. f fifo access 13-2 direct master 5-2 pci i/o 5-5 pci memory 5-4 backoff 5-7 circular 13-2 operation 13-5 ? 13-6 direct master operation 5-2 ? 5-3 direct slave 4-4 read 4-1, 4-5 transfer 4-5 full or empty, response to 4-4, 5-2 head pointer 13-2 hostfreelist 13-6 hostpostlist 13-6 i 2 o enable sequence 13-4 ifhpr 13-2 iftpr 13-2 inbound 13-1 free queue 13-1, 13-2, 13-3 post queue 13-1 internal 4-4, 5-2 interrupt bit 13-3 iptpr 13-2 ofhpr 13-2 oftpr 13-2 ophpr 13-2 opqim 13-4 optpr 13-2 outbound 13-1 circular memory 13-2 free queue 13-1, 13-3, 13-4 post queue 13-1, 13-2 overflow conditions 13-2 prefetching 4-1, 13-3 ? 13-4 queue base address 13-2 queue base size 13-2 read 4-4, 4-7, 5-2, 5-4 read ahead mode 4-5 shared local memory 13-2 tail pointer 13-2 write 4-4, 4-5, 4-7, 5-2, 5-4, 5-7 fixed interval timer (fit) 11-33 exception 11-26 flush pending reads on writes 17-30 frame# 18-4, 20-8 g general exception-handling registers 11-13 general purpose registers (gprs) 23-7 gnt# 18-2, 18-6, 20-7 gnt0# 18-2, 18-6, 20-7 gnt1# 18-6, 20-7 gnt2# 18-2, 18-6, 20-7 gpr0-gpr31 24-2, 29-19 ground and power, pins 18-1, 18-11 use with decoupling capacitors 19-1 h halt# 18-10, 20-7 high-priority mode pci latency timer 1-7 real time application design 1-7 round-robin 8-1 timing diagram 8-2 hmode 18-2, 18-5, 18-7, 18-10, 20-7 hostoutidx 17-25 hot plug 1-1 specification xxxvii hot swap see compactpci hot swap hscapid 17-19 hscsr 17-20 hsnext 17-19 i i/o decode 5-1 hot swap requirement 14-1 processor 1-4 see also intelligent i/o (i 2 o) i/o access direct master 17-35 direct slave 4-1 local-to-pci 3-1, 5-1, 17-36 pci 3-1, 5-4, 5-5 power state 17-17 i/o buffer types 18-1 i 2 o to instruction listing iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-15 index i 2 o 13-1 ? 13-8 architecture 13-1 iac1 26-8, 29-20 ibm, powerpc embedded environment 11-9 icbi 25-6, 25-12, 28-64 icbt 25-6, 28-65 iccci 25-6, 28-67 iccr 27-13, 29-21 icdbdr 25-9, 29-23 icread 25-6, 28-69 icu cacheability control 25-3 coherency 25-4 debugging 25-9 instructions 25-6 locking lines 25-11 unlocking lines 25-11 idsel 18-4, 20-7 ifhpr 17-21 i-form a-38 iftpr 17-22 imprecise interrupts, defined 11-9 initialization 10-8 requirements 10-10 see also reset and initialization inslwi 28-121 inslwi. 28-121 insrwi 28-121 insrwi. 28-121 instruction cache cacheability register (iccr) 27-13 fields a-36 formats 28-4, a-36 b-form a-38 d-form a-38 diagrams a-38 i-form a-38 i-form a-38 m-form a-40 sc-form a-38 x-form a-39 xfx-form a-40 xl-form a-40 xo-form a-40 forms a-38 mftb 11-29 queue 24-21 set brief summaries by category 24-31 summary arithmetic and logical 24-33 branch 24-33 cache control 24-34 compare 24-33 cr logical 24-33 interrupt control 24-34 processor management 24-34 rotate and shift 24-33 tlb management 24-34 set portability 28-4 tlb (itlb) 27-5 tlb (tlb) miss exception 11-27 instruction address compare (iac) debug status register 26-6, 26-8 event 26-3 exception type 11-12, 11-28 iac1 debug event 29-11 iac1 register 29-20 register 29-2 instruction forms a-36 instruction listing add 28-7 add. 28-7 addc 28-8 addc. 28-8 addco 28-8 addco. 28-8 adde 28-9 adde. 28-9 addeo 28-9 addeo. 28-9 addi 28-10 addic 28-11 addic. 28-12 addis 28-13 addme 28-14 addme. 28-14 addmeo 28-14 addmeo. 28-14 addo 28-7 addo. 28-7 addze 28-15 addze. 28-15 addzeo 28-15 addzeo. 28-15 and 28-16 and. 28-16 andc 28-17 andc. 28-17 instruction listing to instruction listing iop 480 data book r2.0 index-16 ? 2000 plx technology, inc. all rights reserved. andi. 28-18 andis. 28-19 b28-20 ba 28-20 bc 28-21 bca 28-21 bcctr 28-26 bcctrl 28-26 bcl 28-21 bcla 28-21 bclr 28-29 bclrl 28-29 bl 28-20 bla 28-20 cmp 28-33 cmpi 28-34 cmpl 28-35 cmpli 28-36 cntlzw 28-37 cntlzw. 28-37 crand 28-38 crandc 28-39 creqv 28-40 crnand 28-41 crnor 28-42 cror 28-43 crorc 28-44 crxor 28-45 dcba 28-46 dcbf 28-48 dcbi 28-49 dcbst 28-50 dcbt 28-51 dcbtst 28-52 dcbz 28-53 dccci 28-55 dcread 28-56 divw 28-58 divw. 28-58 divwo 28-58 divwo. 28-58 divwu 28-59 divwu. 28-59 divwuo 28-59 divwuo. 28-59 eieio 28-60 eqv 28-61 eqv. 28-61 extsb 28-62 extsb. 28-62 extsh 28-63 extsh. 28-63 icbi 28-64 icbt 28-65 iccci 28-67 icread 28-69 isync 28-71 lbz 28-72 lbzu 28-73 lbzux 28-74 lbzx 28-75 lha 28-76 lhau 28-77 lhaux 28-78 lhax 28-79 lhbrx 28-80 lhz 28-81 lhzu 28-82 lhzux 28-83 lhzx 28-84 lmw 28-85 lswi 28-86 lswx 28-88 lwarx 28-90 lwbrx 28-91 lwz 28-92 lwzu 28-93 lwzux 28-94 lwzx 28-95 mcrf 28-96 mcrxr 28-97 mfcr 28-98 mfdcr 28-99 mfmsr 28-100 mfspr 28-101 mftb 28-103 mtcrf 28-103 mtdcr 28-104 mtspr 28-106 mulhw 28-108 mulhw. 28-108 mulhwu 28-109 mulhwu. 28-109 mulli 28-110 mullw 28-111 mullw. 28-111 mullwo 28-111 mullwo. 28-111 nand 28-112 nand. 28-112 instruction machine check handling to instructions iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-17 index neg 28-113 neg. 28-113 nego 28-113 nego. 28-113 nor 28-114 nor. 28-114 or 28-115 or. 28-115 orc 28-116 orc. 28-116 ori 28-117 oris 28-118 rfci 28-119 rfi 28-120 rlwimi 28-121 rlwimi. 28-121 rlwinm 28-122 rlwinm. 28-122 rlwnm 28-124 rlwnm. 28-124 sc 28-125 slw 28-126 slw. 28-126 sraw 28-127 sraw. 28-127 srawi 28-128 srawi. 28-128 srw 28-129 srw. 28-129 stb 28-130 stbu 28-131 stbux 28-132 stbx 28-133 sth 28-134 sthbrx 28-135 sthu 28-136 sthux 28-137 sthx 28-138 stmw 28-139 stswi 28-140 stswx 28-141 stw 28-143 stwbrx 28-144 stwcx. 28-145 stwu 28-146 stwux 28-147 stwx 28-148 subf 28-149 subf. 28-149 subfc 28-150 subfc. 28-150 subfco 28-150 subfco. 28-150 subfe 28-151 subfe. 28-151 subfeo 28-151 subfeo. 28-151 subfic 28-152 subfme 28-153 subfme. 28-153 subfmeo 28-153 subfmeo. 28-153 subfo 28-149 subfo. 28-149 subfze 28-154 subfze. 28-154 subfzeo 28-154 sync 28-155 tlbia 28-156 tlbre 28-157 tlbsx 28-159 tlbsx. 28-159 tlbsync 28-160 tlbwe 28-161 tw 28-163 twi 28-166 wrtee 28-169 wrteei 28-170 xor 28-171 xori 28-172 instruction machine check handling 11-20 instruction sets see cpu instruction set instruction storage exception 11-22 instruction summary see cpu instruction summary instructions alignment exceptions, causing 24-12 alphabetical, including extended mnemonics a-1 arithmetic and logical b-27 branch b-32 cache 25-5, 25-6 cacheability control 25-3 coherency 25-4 dac debug events 26-7 dcu 25-6 debugging 25-7, 25-9 icu 25-6 locking lines 25-11 inta# to interrupts iop 480 data book r2.0 index-18 ? 2000 plx technology, inc. all rights reserved. unlocking lines 25-11 cache control b-35 alignment 24-11 categories b-1 comparison b-33 condition register logical b-31 extended mnemonics b-6 format diagrams a-38 formats a-36 forms a-36, a-38 interrupt control b-36 opcodes a-30 privileged 24-28, b-4 processor management b-37 rotate and shift b-34 see also cpu instruction set specific to powerpc embedded controllers b-2 storage reference b-23 alignment 24-11 inta# 11-2, 11-4, 18-2, 18-4, 20-8 integrated powerpc i/o processor 1-1 ? 1-8 applications 1-5 ? 1-8 block diagram 1-1 features 1-2 ? 1-4 highlights 1-1 plx company background 1-4 ? 1-5 product background 1-4 ? 1-5 intelligent i/o (i 2 o) enable sequence 13-4 ? 13-6 inbound free queue fifo 13-3 inbound messages 13-1 inbound post queue fifo 13-3 outbound free queue fifo 13-4 outbound messages 13-1 ? 13-2 outbound post queue fifo 13-3 ? 13-4 overview 13-1 performance tuning 13-6 pointer management 13-2 registers used 13-1 intelligent i/o (i 2 o) 13-1 ? 13-8 interface apu 23-3 core 23-1 cpu gf type 18-12 cpu organization 23-3 data 23-1 data cache requesting access 25-13 debug 23-6, 26-1, 26-8 doorbell registers 11-8 error during line fill 25-4 flexibility in bus 17-1 interrupt controller 23-7 performing transfer dfltbrd 17-54 drambrd 17-49 lcs0brd 17-38, 17-39 lcs1brd 17-41 lcs2brd 17-44 lcs3brd 17-46 plb-compliant 23-7 precharge command 12-32 priority changes 25-14 register level programming 10-7 register level programming, pciccr 17-11 reset during soft reset 16-1 pmcsr 17-17 see also cpu bus interface, local bus interface, pci bus interface serial eeprom 18-7 set bits 13-4 specification, pmc 17-16 spu registers 22-2 system 1-4 to sustain maximum core clock performance 25-14 when accessing sdram 12-19 when design cannot meet timing requirements 25-14 when local reset# asserted 10-2 internal arbiter see local bus internal arbiter or pci bus internal arbiter interrupt controller interface 23-7 interrupts 11-1 ? 11-36 asynchronous, defined 11-9 definition 11-8 doorbell registers 11-8 exception, defined 11-8 imprecise, defined 11-9 interrupt, defined 11-8 iop 480 exceptions, interrupts and timers 11-8 ? 11-36 local bus pins 18-18 local interrupts 11-3 ? 11-7 bist 11-4 cint critical 11-6 dma 11-5 local bus parity error 11-5 local bus timeout 11-5 local interrupt input 11-5 interrupts and exceptions to lcs1base iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-19 index local interrupt output (into) 11-7 master/target abort 11-6 messaging unit inbound post queue 11-6 messaging unit outbound free queue overflow 11-5 pci bus parity errors 11-5 pci interrupt input (inta#) 11-4 pci system error output (serr#) 11-4 refresh 11-6 serial port 11-5 machine check, defined 11-9 mailbox 11-3 mailbox registers 11-8 overview 11-1 pci interrupts 11-1 ? 11-2 consecutive pci retries, 256 11-2 dma 11-2 local interrupt input (inti) 11-1 local-to-pci doorbell 11-1 master/target abort 11-1 ? 11-2 messaging unit outbound post queue 11-2 pci interrupt output (inta#) 11-2 pci system error output (serr#) 11-3, 11-4 pci-to-local doorbell 11-4 power management event (pme#) 11-4 precise, defined 11-9 synchronous, defined 11-9 interrupts and exceptions alignment error 11-24 architectural definitions and behavior 11-9 critical 11-11 critical interrupt pin 11-19 data machine check handling 11-21 data storage 11-21 data tlb miss 11-27 debug 11-28 external interrupts 11-23 fixed interval timer (fit) 11-26 implementation behavior 11-10 instruction machine check 11-10 instruction machine check handling 11-20 instruction storage 11-22 instruction, tlb, miss 11-27 iop 480 exceptions, interrupts and timers 11-8 ? 11-36 non-critical 11-10 program 11-24 programmable interval timer (pit) 11-26 system call 11-25 watchdog timer 11-27 inti 11-1, 11-5, 18-3, 18-18, 20-8 into 11-7, 18-3, 18-18, 20-8 iopoutidx 17-25 iphpr 13-2, 17-22 iptpr 17-22 iqp 17-25 irdy# 18-4, 18-5, 20-8 isync 28-71 itlb 27-5 j jtag see cpu debugging and jtag facilities l l2pdbell 17-57 la 28-10 lad[31:0] 18-13, 18-18, 20-8 larbr 17-29 las0ba 17-31 las1ba 17-32 las1rr 17-31 las2ba 17-33 las2rr 17-32 lasorr 17-31 latency timer, pci block dma mode 7-2, 7-6, 7-9 data pipe architecture 1-2 pci_pciclsr 17-3 pciltr 17-11 real time application design 1-7 lbe[3:0]# 18-14, 20-8 lbz 28-72 lbzu 28-73 lbzux 28-74 lbzx 28-75 lclk 18-10, 20-7 lcs range access local characteristics 2-6 lcs0# 18-2, 18-14, 20-7 lcs0base 17-39 lcs0brd 17-38 ? 17-39 lcs0range 17-39 lcs0rt 17-39 lcs0wt 17-39 lcs1# 18-2, 18-15, 20-7 lcs1base 17-43 lcs1brd to local bus parity error interrupt iop 480 data book r2.0 index-20 ? 2000 plx technology, inc. all rights reserved. lcs1brd 17-41 ? 17-42 lcs1range 17-43 lcs1rt 17-42 lcs1wt 17-42 lcs2# 18-2, 18-15, 20-7 lcs2base 17-45 lcs2brd 17-43 ? 17-44 lcs2range 17-45 lcs2rt 17-45 lcs2wt 17-45 lcs3# 18-2, 18-8, 18-15, 20-7 lcs3base 17-48 lcs3brd 17-46 ? 17-47 lcs3range 17-48 lcs3rt 17-47 lcs3wt 17-47 ldreq 20-8 ledin 20-7 ledon 20-7 ledon/ledin 18-7 lha 28-76 lhau 28-77 lhaux 28-78 lhax 28-79 lhbrx 28-80 lholdack 20-8 lholdack0 18-2, 18-17, 20-8 lholdack1 18-17, 20-8 lholdreq0 18-2, 18-17, 20-8 lholdreq1 18-17, 20-7 lhz 28-81 lhzu 28-82 lhzux 28-83 lhzx 28-84 li 28-10 line locking, cache 25-11 linstat 17-60 ? 17-61 lintenb 17-61 ? 17-62 lis 28-13 little endian byte ordering 2-11 little endian operation and alignment 24-12 llock# 18-15 2-5 lmw 28-85 local reset 10-1, 10-2 local address, incremented 17-64 local bus arbiter pins 18-17 configuration access 11-1 driver loading derating 19-2 interface 2-1 ? 2-16 accesses 2-15 data alignment 2-15 endian swapping 2-11 ? 2-15 introduction 2-1 ? 2-2 local signals 2-2 pins 18-12 ? 18-16 protocol 2-6 ? 2-10 region descriptors 2-10 ? 2-11 regions 2-2 ? 2-5 signals 2-2 width 2-15 internal arbiter 8-1 ? 8-2 high-priority mode 8-1 initialization 8-1 overview 8-1 performance tuning 8-2 round-robin mode 8-1 interrupts, pins 18-18 master, unaligned transfer 2-15, 4-7, 7-8, 7-13 protocol 2-6 ? 2-10 basic access 2-6 burst transactions 2-10 bus and control signals during recovery and idle states 2-10 wait states 2-6 timeout interrupt 11-5 timing diagrams 2-7 ? 2-9, 2-14 local bus parity error interrupt 11-5 local chip selects, range access local characteristics to memory iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-21 index local chip selects, range access local characteristics 2-6 local configuration registers 17-1, 17-2, 17-5, 17-12, 17-26 ? 17-37 local interrupt input 11-5 local interrupt input (inti) 11-1 local interrupt output (into) 11-7 local interrupts 11-3 ? 11-7 bist 11-4 cint critical 11-6 dma 11-5 into 11-7 local bus parity error 11-5 local bus timeout 11-5 local interrupt output (into) 11-7 mailbox 11-3 master/target abort 11-6 messaging unit inbound post queue 11-6 messaging unit outbound free queue overflow 11-5 pci bus parity errors 11-5 pci enumerate input (enum#) 11-3 pci interrupt input (inta#) 11-4 pci system error output (serr#) 11-4 pci-to-local doorbell 11-4 pins 18-18 power management 11-4 power management event (pme#) 11-4 refresh 11-6 serial port 11-5 local-to-local dma 7-1, 7-10, 7-11 controller 8-1 data pipe architecture 1-2, 1-5 timing diagram 7-23 local-to-pci doorbell interrupt 11-1 locctl 17-27 ? 17-28 lock# 18-4, 20-7, 20-8 locked atomic operations 4-5 loctmo 17-28 loctmr 17-28 logical compare 24-8 low power operation 12-12 lr 24-4, 29-24 lswi 28-86 lswx 28-88 lwarx 28-90 lwbrx 28-91 lwr# 18-15, 20-8 lwz 28-92 lwzu 28-93 lwzux 28-94 lwzx 28-95 m ma[12:0] 18-8, 18-15 ma[16:13] 18-2, 18-8, 18-13, 20-7 ma17 18-2, 18-8, 18-15 machine check interrupts, defined 11-9 machine state register (msr) 23-8, 29-25 11-13, 23-7, 24-2, 24-9, 24-29, 29-1 sleep mode 29-25 mailbox interrupt 11-3 mailbox register interrupts 11-8 master command codes 3-1 master/target abort interrupt 11-1 ? 11-2, 11-6 mbox1 17-56 mbox2 17-56 mbox3 17-56 mbox4 17-56 mbox5 17-56 mbox6 17-56 mbox7 17-57 mcas# 18-3, 18-8, 20-7 mcke 18-8, 20-7 mcrf 28-96 mcrxr 28-97 mcs[3:0]# 18-3, 18-9, 20-7 mdqm[3:0]# 18-3, 18-9, 20-7 memory access cpu byte ordering 24-17 cpu control 23-5 cpu management 27-4 cpu storage attributes 24-1 cpu sync 24-29 direct master 5-2, 17-35 direct slave 4-4 local-to-pci 3-1, 5-1, 17-34 pci 4-1, 5-4, 7-10, 10-14, 17-1, 17-12, 17-13 controller 12-1 ? 12-54 dram 12-12 ? 12-52 overlapping address spaces 12-53 ? 12-54 overview 12-1 pins 18-8 ? 18-9 registers 17-1, 17-2, 17-6, 17-12, 17-38 ? 17-55 messaging queue registers to mtiac1 iop 480 data book r2.0 index-22 ? 2000 plx technology, inc. all rights reserved. signal loading 12-53 sram 12-2 ? 12-11 decode 5-1 management see cpu memory management management unit 23-5 map 24-1 storage attributes 24-1 organization 24-1 messaging queue registers 17-21 ? 17-25 base addresses 17-2 description 17-4 internal registers 17-1 memory base address 17-12 offset 17-4 messaging unit inbound post queue interrupt 11-6 messaging unit outbound free queue overflow interrupt 11-5 messaging unit outbound post queue interrupt 11-2 mfcdbcn 28-102 mfcr 28-98 mfctr 28-102 mfdac 28-102 mfdbcl 28-102 mfdbsr 28-102 mfdbsrs 28-102 mfdccr 28-102 mfdcr 28-99 mfdcwr 28-102 mfdear 28-102 mfesr 28-102 mfevpr 28-102 mflac1 28-102 mflccr 28-102 mflcdbdr 28-102 mflr 28-102 mfmsr 28-100 m-form a-40 mfplt 28-102 mfpvr 28-102 mfsgr 28-102 mfsler 28-102 mfspr 28-101 mfsprg0 28-102 mfsprg1 28-102 mfsprg2 28-102 mfsprg3 28-102 mftb 11-29, 28-103 mftcr 28-102 mftsr 28-102 mfxer 28-102 mmu exceptions data storage 27-7 data tlb miss 27-7 instruction storage 27-7 instruction tlb miss 27-8 protection 27-9 ex 27-10 tid 27-9 zone 27-10 reference and change recording 27-9 tlb management 27-8 tlb reload tlbia 27-8 tlbre, tlbwe 27-8 tlbsx 27-8 tlbsync 27-8 tlb-related exceptions 27-7 virtual-to-real address algorithm 27-1 moe# 18-3, 18-8, 20-7 mptvr 28-107 mqcr 17-21 mr 28-115 mr. 28-115 mras# 18-9, 20-7 msr 11-13, 23-7, 24-2, 24-9, 24-29, 29-1, 29-25 msr bits and exception handling 24-27 mtcdbcr 28-107 mtcr 28-103 mtcrf 28-103 mtctr 28-107 mtdac1 28-107 mtdbcr 28-107 mtdbsr 28-107 mtdccr 28-107 mtdcr 28-104 mtdcwr 28-107 mtdear 28-107 mtesr 28-107 mtevpr 28-107 mtiac1 28-107 mticcr to pci iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-23 index mticcr 28-107 mticdbdr 28-107 mtlr 28-107 mtp 18-10, 20-7 mtpit 28-107 mtsgr 28-107 mtsler 28-107 mtspr 28-106 mtsprg1 28-107 mtsprg2 28-107 mtsprg3 28-107 mtsrr0 28-107 mtsrr1 28-107 mtsrr2 28-107 mtsrr3 28-107 mttcr 28-107 mttsprg0 28-107 mttsr 28-107 mttxer 28-107 mulhw 28-108 mulhw. 28-108 mulhwu 28-109 mulhwu. 28-109 mulli 28-110 mullw 28-111 mullw. 28-111 mullwo 28-111 mullwo. 28-111 mwe# 18-9, 20-7 n nand 28-112 nand. 28-112 neg 28-113 neg. 28-113 nego 28-113 nego. 28-113 non-critical exceptions, defined 11-10 nop 28-117 nor 28-114 nor. 28-114 not 28-114 not. 28-114 notation 28-4, a-36 o ofhpr 17-22 oftpr 17-23 opcodes a-30 operations, locked atomic 4-5 ophpr 17-23 opqim 17-24 opqis 17-24 optpr 17-23 oqp 17-25 or 28-115 or. 28-115 orc 28-116 orc. 28-116 ori 28-117 oris 28-118 p p2ldbell 17-57 pabtadr 17-62 package 20-1 ? 20-9 par 18-5, 20-8 park option 9-1 part number recommendation 10-3 part number used 10-3 pattern generation mode 22-5 pbga footprint 20-4 printed circuit board (pcb) assembly compatibility 20-9 process conditions 20-9 see also 225-pin pbga pinout pci command codes 3-1 configuration access 3-1, 5-1, 5-4, 10-14, 13-4, 17-36 configuration registers 17-1, 17-2, 17-3, 17-9 ? 17-20 direct local-to-pci command codes 3-1 flush pending reads on writes 17-30 i/o access 3-1, 5-1, 5-4, 5-5, 17-36 master command codes 3-1 pci arbiter pins to pid iop 480 data book r2.0 index-24 ? 2000 plx technology, inc. all rights reserved. memory access 3-1, 4-1, 5-1, 5-4, 7-10, 10-14, 17-1, 17-12, 17-13, 17-34 reset 10-1, 10-2 retry writes 17-30 signals 3-2 ad 3-2 c/be[3:0]# 3-2 devsel# 3-2 frame# 3-2 irdy# 3-2 stop# 3-2 trdy# 3-2 target command codes 3-1 pci arbiter pins 18-6 pci buffer loading derating 19-2 pci bus arbitration 3-3 interface 3-1 ? 3-3 internal arbiter 9-1 ? 9-2 grant on idle mode 9-2 initialization 9-1 overview 9-1 park on iop 480 mode 9-2 park option 9-1 performance tuning 9-2 priority mode 9-1 pci bus power management interface specification xxxvii, 16-1 protocol 3-3 pci bus controller pins 18-4 ? 18-5 pci bus parity error interrupts 11-5 pci bus power management interface specification xxxvii, 16-1 pci enumerate input (enum#) 11-3 pci hot-plug specification, revision 1.0 xxxvii pci industrial computer manufacturers group xxxvii pci initiator see direct master pci interrupt input (inta#) 11-4 pci interrupt output (inta#) 11-2 pci interrupts 11-1 ? 11-2 11-2 consecutive pci retries, 256 11-2 dma 11-2 local interrupt input (inti) 11-1 local-to-pci doorbell 11-1 master/target abort 11-1 ? 11-2 messaging unit outbound post queue 11-2 pci interrupt output (inta#) 11-2 pci latency timer block dma mode 7-2, 7-6, 7-9 data pipe architecture 1-2 high priority mode latency timer, pci 1-7 pci_pciclsr 17-3 pciltr 17-11 real time application design 1-7 pci local bus specification, revision 2.2 xxxvii pci power management interface specification 1-1 pci read, read ahead mode 4-5 pci special interest group xxxvii pci system error output (serr#) 11-3, 11-4 pci target see direct slave pcibar0 17-12 pcibar1 17-12 pcibar2 17-13 pcibar3 17-13 pcibar4 17-13 pcibar5 17-13 pcibistr 17-11 pciccr 17-11 pcicis 17-13 pciclsr 17-11 pcicr 17-9 pcictl 17-30 pcidid 17-9 pcierbar 17-14 pcihtr 17-11 pciilr 17-14 pciipr 17-14 pciltr 17-11 pcimgr 17-15 pcimlr 17-15 pcirev 17-10 pcisid 17-14 pcisr 17-10 pcisvid 17-14 pci-to-local doorbell interrupt 11-4 pcivid 17-9 perr# 18-5, 20-8 picmg xxxvii pid 27-9, 29-27 pin type abbreviations to pins iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-25 index pin type abbreviations 18-1 pins 16450 compatible serial port 18-7 ad 18-5 ad[31:0] 18-4, 20-7, 20-8 ads# 18-12, 20-8 ale 18-12, 20-7 blast# 18-12, 20-8 boff# 18-12, 20-7 breq 18-17, 20-8 bterm# 18-12, 20-8 c/be# 18-5 c/be[3:0]# 18-4, 20-7, 20-8 cas[3:0]# 18-3, 18-9, 20-7 cint 18-3, 18-18, 20-8 clk 18-1, 18-4, 20-7 compactpci hot swap 18-7 configuration control 18-2 ? 18-3 cpu clock and test/debug 18-10 ? 18-11 dack0# 18-12, 20-7 dack1# 18-12, 20-7 dack2# 18-12, 20-7 description 18-1 ? 18-18 devsel# 18-4, 20-8 dmpaf# 18-2, 18-14, 20-7 dp[3:0] 18-2, 18-8, 18-13, 20-7 dreq0# 18-13, 20-7 dreq1# 18-13, 20-7 dreq2# 18-13, 20-7 eecs 18-7, 20-7 eedata 18-2, 18-7, 20-7 eesk 18-2, 18-7, 20-7 enum# 18-2, 18-7, 18-10, 20-7 eot0# 18-2, 18-13, 20-7 eot1# 18-2, 18-13, 20-7 eot2# 20-7 frame# 18-4, 20-8 gnt# 18-2, 18-6, 20-7 gnt0# 18-2, 18-6, 20-7 gnt1# 18-6, 20-7 gnt2# 18-2, 18-6, 20-7 ground and power 18-1, 18-11, 19-1 halt# 18-10, 20-7 hmode 18-2, 18-5, 18-7, 18-10, 20-7 i/o pin summary 18-1 idsel 18-4, 20-7 inta# 18-2, 18-4, 20-8 inti 18-3, 18-18, 20-8 into 18-3, 18-18, 20-8 irdy# 18-4, 18-5, 20-8 lad[31:0] 18-13, 18-18, 20-8 lbe[3:0]# 18-14, 20-8 lclk 18-10, 20-7 lcs0# 18-2, 18-14, 20-7 lcs1# 18-2, 18-15, 20-7 lcs2# 18-2, 18-15, 20-7 lcs3# 18-2, 18-8, 18-15, 20-7 ldreq 20-8 ledin 20-7 ledon 20-7 ledon/ledin 18-7 lholdack 20-8 lholdack0 18-2, 18-17, 20-8 lholdack1 18-17, 20-8 lholdreq0 18-2, 18-17, 20-8 lholdreq1 18-17, 20-7 llock# 18-15 local bus arbiter 18-17 local bus interface (iop 480 cpu gf type) 18-12 ? 18-16 local bus interrupts 18-18 lock# 18-4, 20-7, 20-8 lwr# 18-15, 20-8 ma[12:0] 18-8, 18-15 ma[16:13] 18-2, 18-8, 18-13, 20-7 ma17 18-2, 18-8, 18-15 mcas# 18-3, 18-8, 20-7 mcke 18-8, 20-7 mcs[3:0]# 18-3, 18-9, 20-7 mdqm[3:0]# 18-3, 18-9, 20-7 memory controller 18-8 ? 18-9 moe# 18-3, 18-8, 20-7 mras# 18-9, 20-7 mtp 18-10, 20-7 mwe# 18-9, 20-7 par 18-5, 20-8 pci arbiter 18-6 bus controller 18-4 ? 18-5 configuration interface 18-7 serial eeprom 18-7 perr# 18-5, 20-8 pme# 18-2, 18-5, 20-7 power and ground 18-1, 18-11, 19-1 ras[3:0]# 18-3, 18-9, 20-7 rd# 18-16, 20-8 ready# 18-12, 18-16, 20-8 req# 18-2, 18-6, 20-7 req0# 18-2, 18-6, 20-7 req1# 18-6, 20-7 pinstat to power management iop 480 data book r2.0 index-26 ? 2000 plx technology, inc. all rights reserved. req2# 18-2, 18-6, 20-7 reset# 18-10, 20-8 rst# 18-2, 18-5, 18-10, 20-7 rx 18-7, 20-7 serr# 18-5, 20-8 stop# 18-5, 20-8 tck 18-10, 20-7 tdi 18-10, 20-7 tdo 18-10, 20-7 tms 18-10, 20-7 trdy# 18-5, 20-8 trst# 18-11, 20-7 ts1 18-2, 18-6, 20-7 ts2 18-2, 18-6, 20-7 ts3 18-2, 18-7, 20-7 ts4 18-2, 18-7, 20-7 ts5 18-3, 18-7, 20-7 ts6 18-11, 20-7 tx 18-3, 18-7, 20-7 type abbreviations 18-1 unused 18-1, 18-11 user0 18-2, 18-15, 20-7 user1 18-2, 18-15, 20-7 user2 18-3, 18-18, 20-8 user3 18-2, 18-13, 20-7 user4 18-2, 18-13, 20-7 vdd 18-11, 20-7, 20-8 vdda 18-10, 20-7 vss 18-11, 20-7, 20-8 wait# 18-16, 20-8 pinstat 17-58 pintenb 17-58 pit 11-32, 29-28 exception 11-26 plastic ball grid array see pbga plastic quad flat pack see pqfp plb see processor, local bus (plb) plx technology, inc. company background 1-4 ? 1-5 iop 480 available packages d-1 representatives and distributors d-1 technical support information d-1 plxid 17-37 plxrev 17-37 pmc 17-16 pmcapid 17-15 pmcsr 17-17 pmcsr_bse 17-17 pmdata 17-18 pme# 18-2, 18-5, 20-7 pme# pci interrupt 11-4 pmnext 17-15 pmscale 17-18 portability, instruction set 28-4 power applied with ambient temperature 19-2 architecture 29-1 circuitry 14-2 connector signal 26-9 consumed 17-3 consumed values 10-7 consumed values register 17-19 consumption 1-1, 1-4, 1-5, 23-1, 23-4, 26-9, d-1 controller 14-2 dissipated values 10-7 dissipated values register 17-19 dissipation 17-3, 19-2, 23-3 early 1-7, 14-2 good 14-2 pins 18-1 quiescent supply current 19-3 range 5-1 reduce memory consumption mode 18-8 sleep mode, in 29-25 supply current 19-3 power and ground, pins 18-1, 18-11 use with decoupling capacitors 19-1 power management 11-4, 16-1 ? 16-2 adapter 10-1 capabilities 10-7, 17-3 capabilities register 17-16 capability id register 17-15 clock 23-1 control/status register 17-17 csr 17-3 data register 17-18 data scale values 10-7 data_scale values register 17-18 features for adapters and embedded systems 1-2 functional description 16-1 host 10-1 internal register access 17-1 power management event (pme#) to real code example iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-27 index interrupt 11-3, 11-7, 17-60 interrupt enable 17-62 next capability pointer register 17-15 next item pointer 10-7 overview 16-1 r2.2 spec feature 1-1 registers 17-1 reset 10-2 scale values 17-3 self-refresh level 17-50 system changes power mode example 16-2 wake-up request example 16-2 power management event (pme#) 11-4, 18-2, 18-5 power management interrupt 11-4 power, low 12-12 power-down 12-18, 12-19 power-on 14-1, 17-51 reset and initialization 10-1 powerpc architecture see architecture, powerpc embedded environment 11-9 risc processor core 23-1, 23-3, 24-28, 25-1, 29-3 featured in iop 480 1-1 features 1-2 initialization 10-8 see also debugging, cpu, endian mode, integrated powerpc, i/o processor, and/or powerpc risc processor core power-up 10-3, 10-9, 11-11, 12-15, 12-42, 18-13 pqfp package materials/properties 20-3 printed circuit board (pcb) assembly compatibility 20-3 see also 208-pin pqfp precharge 14-1 precise interrupts, defined 11-9 preempt, external enable 17-29 prefetching 4-1 4 kb limit 5-4, 17-35 alignment 4-7 branches to count register 24-25 branches to link register 24-25 direct slave example 4-7 direct slave timing diagram 4-28 fifo 13-3 ? 13-4 queue 24-21 read ahead mode 4-5 primary opcodes a-30 privileged dcrs 24-28 instructions 24-28 mode 24-27 operation 24-27 sprs 24-28 problem state 24-27 processor, local bus (plb) 23-1, 23-4, 23-7, 25-11 program exception 11-24 programmable interval timer 11-26, 11-32 protection 27-9 cache instructions 27-11 ex 27-10 string instructions 27-12 tid 27-9 translate mode 27-9 zone 27-10 pseudocode 28-4 pu, programming model 24-1 pull-down resistors, internal and external 18-1 pull-up resistor, internal and external 18-1 pvr 24-6, 29-29 pwrcon 17-18 pwrdis 17-19 q qbar 17-21 qsr 17-24 queue 24-21 r r0-r31 24-2, 29-19 ras[3:0]# 18-3, 18-9, 20-7 rd# 18-16, 20-8 read ahead mode direct slave operation 4-1 pci delayed read mode, with or without 4-5 pci read 4-5 pci read ahead mode 4-5, 17-30 prefetching 4-5 ready# 18-12, 18-16, 20-8 real code example c-1 ? c-4 real time application design to registers iop 480 data book r2.0 index-28 ? 2000 plx technology, inc. all rights reserved. real time application design high-priority mode 1-7 pci latency timer 1-7 reference recording 27-9 refresh interrupt 11-6 register set summary 23-7 register summary see cpu register summary registers alignment error 11-24 bigend 17-30 brdh 22-6 brdl 22-6 c0count 17-64 c0csr 17-64 c0descptr 17-65 c0locadr 17-64 c0mode 17-63 ? 17-64 c0pcihadr 17-65 c0pciladr 17-64 c0thres 17-65 c1count 17-68 c1csr 17-68 c1descptr 17-69 c1locadr 17-68 c1mode 17-67 ? 17-68 c1pcihadr 17-69 c1pciladr 17-68 c1thres 17-69 c2count 17-72 c2csr 17-72 c2destadr 17-72 c2mode 17-71 c2srcadr 17-72 cap_ptr 17-14 cdbcr 25-7, 29-4 cfgba 17-36 cr 23-8, 29-1, 29-6 critical interrupt 11-19 ctr 24-4, 29-7 dac1 26-7, 29-8 dbcr 26-3, 29-9 dbsr 26-5 dccr 27-13, 29-12 dcr numbering 29-3 dcwr 27-13, 29-14 dear 11-19, 29-16 debug exceptions 11-28 device control 23-8, 24-11 devinit 17-26 dfltbrd 17-54 ? 17-55 dmcfga 17-36 dmdac 17-36 dmlbai 17-36 dmlbam 17-34 dmpbam 17-35 dmrr 17-34 drambase 17-53 drambrd 17-48 ? 17-49 dramctl 17-50 draminit 17-51 dramrange 17-53 dramtim 17-52 ? 17-53 eromba 17-33 eromrr 17-33 esr 29-17 evpr 11-17, 29-18 external interrupts 11-23 fit interrupt 11-26 general purpose 23-7 gpr 29-1 gpr0-gpr31 24-2, 29-19 hostoutidx 17-25 hscapid 17-19 hscsr 17-20 hsnext 17-19 iac1 26-8, 29-20 iccr 27-13, 29-21 icdbdr 25-9, 29-23 ifhpr 17-21 iftpr 17-22 iopoutidx 17-25 iphpr 17-22 iptpr 17-22 iqp 17-25 l2pdbell 17-57 larbr 17-29 las0ba 17-31 las0rr 17-31 las1ba 17-32 las1rr 17-31 las2ba 17-33 las2rr 17-32 lcs0base 17-39 lcs0brd 17-38 ? 17-39 lcs0range 17-39 lcs0rt 17-39 lcs0wt 17-39 lcs1base 17-43 lcs1brd 17-41 ? 17-42 registers to registers iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-29 index lcs1range 17-43 lcs1rt 17-42 lcs1wt 17-42 lcs2base 17-45 lcs2brd 17-43 ? 17-44 lcs2range 17-45 lcs2rt 17-45 lcs2wt 17-45 lcs3base 17-48 lcs3brd 17-46 ? 17-47 lcs3range 17-48 lcs3rt 17-47 lcs3wt 17-47 linstat 17-60 ? 17-61 lintenb 17-61 ? 17-62 locctl 17-27 ? 17-28 loctmo 17-28 loctmr 17-28 lr 24-4, 29-24 machine check 11-20, 11-21 mbox0 17-56 mbox1 17-56 mbox2 17-56 mbox3 17-56 mbox4 17-56 mbox5 17-56 mbox6 17-56 mbox7 17-57 mqcr 17-21 msr 11-13, 23-8, 24-2, 24-9, 24-29, 29-1, 29-25 ofhpr 17-22 oftpr 17-23 ophpr 17-23 opqim 17-24 opqis 17-24 optpr 17-23 oqp 17-25 p2ldbell 17-57 pabtadr 17-62 pcibar0 17-12 pcibar1 17-12 pcibar2 17-13 pcibar3 17-13 pcibar4 17-13 pcibar5 17-13 pcibistr 17-11 pciccr 17-11 pcicis 17-13 pciclsr 17-11 pcicr 17-9 pcictl 17-30 pcidid 17-9 pcierbar 17-14 pcihtr 17-11 pciilr 17-14 pciipr 17-14 pciltr 17-11 pcimgr 17-15 pcimlr 17-15 pcirev 17-10 pcisid 17-14 pcisr 17-10 pcisvid 17-14 pcivid 17-9 pid 27-9, 29-27 pinstat 17-58 pintenb 17-58 pit 11-32, 29-28 pit interrupt 11-26 plxid 17-37 plxrev 17-37 pmc 17-16 pmcapid 17-15 pmcsr 17-17 pmcsr_bse 17-17 pmdata 17-18 pmnext 17-15 pmscale 17-18 program exceptions 11-25 pvr 24-6, 29-29 pwrcon 17-18 pwrdis 17-19 qbar 17-21 qsr 17-24 r0-r31 24-2, 29-19 reserved 29-1 reserved fields 29-1 sgr 27-13, 29-30, 29-32 skr 27-13 sler 27-14, 29-34 spctl 22-7 special purpose 23-7, 24-2 sphs 22-8 spls 22-8 spr numbering 29-1 sprb 22-9 sprc 22-9 sprg0-sprg3 24-6, 29-36 sptb 22-9 sptc 22-9 req# to secondary opcodes iop 480 data book r2.0 index-30 ? 2000 plx technology, inc. all rights reserved. srr0 11-15, 29-37 srr0-srr1 (non-critical) 11-15 srr1 11-15, 29-38 srr2 11-15, 29-39 srr2-srr3 (critical) 11-15 srr3 11-15, 29-40 summary 23-7, 24-1 system call 11-25 tbhi 29-41 tbhu 29-42 tblo 29-43 tblu 29-44 tcr 11-33, 11-36, 29-45 tsr 11-33, 11-35, 29-46 uartba 17-37 vpd_cap 17-20 vpd_data 17-20 watchdog interrupt 11-27 xer 24-5, 29-47 zpr 27-10, 29-48 req# 18-2, 18-6, 20-7 req0# 18-2, 18-6, 20-7 req1# 18-6, 20-7 req2# 18-2, 18-6, 20-7 reservation bit 28-90, 28-145 reserved fields 29-1 registers 29-1 reset and initialization 10-1 ? 10-14 cpu boot 10-8 ? 10-10 dram initialization 10-14 initialization code example 10-11 ? 10-13 local 10-1, 10-2 overview 10-1 pci 10-1, 10-2 power-on 10-1 processor initialization 10-8 processor state after 10-8 reset 10-1 ? 10-3 serial eeprom 10-3 ? 10-8 software 10-1, 10-2, 10-8 reset# 18-10, 20-8 retry pci writes 17-30 rfci 28-119 rfi 28-120 ring management data communications design 1-7 data pipe architecture 1-2 dma 1-5, 7-8 valid mode 7-8 risc architecture 2-1 risc processor see powerpc risc processor core risc, ibm system/6000 24-13 risctrace 17-26, 18-2, 18-3, 18-6, 18-7, 18-11, 23-6 riscwatch 10-2, 23-6, 23-7, 26-1, 26-8, 26-9 rlwimi 28-121 rlwimi. 28-121 rlwinm 28-122 rlwinm. 28-122 rlwnm 28-124 rlwnm. 28-124 rotlw 28-124 rotlw. 28-124 rotlwi 28-123 rotlwi. 28-123 rotrwi 28-123 rotrwi. 28-123 round-robin arbitration 9-1, 17-29, 17-31 high-priority mode 8-1 mode 8-1 mode example 9-1 operation mode 9-1 performance tuning 8-2 timing diagrams 8-2 rst# 18-2, 18-5, 18-10, 20-7 runtime registers 17-1, 17-2, 17-7, 17-11, 17-12, 17-56 ? 17-62 rx 18-7, 20-7 s sc 28-125 scatter/gather data pipe architecture 1-2 dma 7-1, 7-3, 7-4, 7-7, 7-8, 7-18, 7-19, 11-2, 11-5, 17-63, 17-64, 17-67, 17-68 sc-form a-38 sdram refresh 11-6 secondary opcodes a-30 serial eeprom to signal names iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-31 index serial eeprom devinit bits 17-26 interface 18-7 interface pins 18-7 loading sequence 17-8 part number used 10-3 pci 18-7 reset and initialization 10-3 ? 10-8 vital product data (vpd) 10-3 vpd partitioning 15-1 serial port 1-1, 1-3 baud rate generator 22-4 functional block 22-1 initialization and configuration 22-10 ? 22-11 interrupts 11-3, 11-5 operating mode 22-2 operation 22-1 ? 22-11 operations 22-4 ? 22-6 overview 22-1 receiver 22-5 interrupts 22-6 register descriptions 22-6 ? 22-9 registers 22-2 transmitter 22-4 interrupts 22-5 line break 22-5 serr# 11-3, 11-4, 18-5, 20-8 sgr 27-13, 29-30, 29-32 signal names address and data 18-4 address and data bus 18-13 address latch enable 18-12 address strobe 18-12 backoff request out 18-12 burst last 18-12 bus command and byte enables 18-4 bus lock 18-15 bus terminate 18-12 byte enables 18-14 chip select 18-7 clock 18-4 clock enable 18-8 column address strobe 18-8, 18-9 critical interrupt 18-18 cycle frame 18-4 data mask outputs 18-9 data parity 18-13 device select 18-4 direct master programmable almost full 18-14 dma 0 end of transfer input/user input 18-13 dma 1/2 end of transfer input/user input 18-13 dma acknowledge output channel 0 18-12 dma acknowledge outputs channels 1 and 2 18-12 dma request input 18-13 dma request inputs 18-13 grant 18-6 grant 0/request 18-6 grant 1 18-6 grant 2 18-6 ground (pbga package only) 18-11 ground common grounds (pqfp and pbga packages) 18-11 halt 18-10 host mode 18-10 hot swap 18-7 initialization device select 18-4 initiator ready 18-4 interrupt 18-4 interrupt input 18-18 interrupt output 18-18 led control pin 18-7 local bus chip select 18-14, 18-15 local bus chip select 3 18-15 local bus hold acknowledge 18-17 local bus hold acknowledge 0 18-17 local bus hold acknowledge 1 18-17 local bus hold request 18-17 local bus hold request 0 18-17 local bus hold request 1 18-17 local clock input 18-10 lock 18-4 manufacturing test pin 18-10 memory address 18-8, 18-13 memory address 17 18-15 memory chip selects 18-9 output 18-10 output enable 18-8 parity 18-5 parity error 18-5 power (3.3v) 18-11 power management event 18-5 read strobe 18-16 ready 18-16 request 0 18-6 request 1 18-6 request 2 18-6 reset 18-5 reset input 18-10 risctrace 1 output 18-6 signals, pci to stbu iop 480 data book r2.0 index-32 ? 2000 plx technology, inc. all rights reserved. risctrace 2 output 18-6 risctrace 3 output 18-7 risctrace 4 output 18-7 risctrace 5 output 18-7 risctrace 6 output 18-11 row address strobe 18-9 serial data clock 18-7 serial eeprom data 18-7 serial receive 18-7 serial transmit 18-7 stop 18-5 systems error 18-5 target ready 18-5 test clock input 18-10 test data in 18-10 test data output 18-10 test mode select 18-10 test reset 18-11 unused pbga pins 18-11 user input 18-15 user input/output 18-15 user output 18-15 wait 18-16 write enable 18-9 write/read# 18-15 signals, pci 3-2 ad 3-2 c/be[3:0]# 3-2 devsel# 3-2 frame# 3-2 irdy# 3-2 stop# 3-2 trdy# 3-2 simulation debugging real code example c-1 ? c-4 single address cycle (sac) block dma mode 7-3 on pci bus 5-5, 7-1 scatter/gather dma 7-4 16450 compatible serial port pins 18-7 skr 27-13 sleep mode machine state register (msr) 29-25 sler 27-14, 29-34 slw 28-126 slw. 28-126 slwi 28-123 slwi. 28-123 software, reset 10-1, 10-2, 10-8 space 04-1 14-1 24-1 expansion rom 4-1 spctl 22-7 special purpose registers (sprs) part of powerpc architecture 23-7, 24-2 specifications see electrical specifications speculative accesses 24-24 fetching 24-24 guarded storage 24-25 on the 401core 24-24 on the 401gf 24-24 sphs 22-8 spls 22-8 sprb 22-9 sprc 22-9 sprg0-sprg3 24-6, 29-36 sptb 22-9 sptc 22-9 spu see serial port operation sraw 28-127 sraw. 28-127 srawi 28-128 srawi. 28-128 srr0 11-15, 29-37 srr1 11-15, 29-38 srr2 11-15, 29-39 srr3 11-15, 29-40 srw 28-129 srw. 28-129 srwi 28-123 srwi. 28-123 states, four basic address 2-2 data/wait 2-2 idle 2-2 recovery 2-2 stb 28-130 stbu 28-131 stbux to tcr iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-33 index stbux 28-132 stbx 28-133 sth 28-134 sthbrx 28-135 sthu 28-136 sthux 28-137 sthx 28-138 stmw 28-139 stop# 18-5, 20-8 storage attribute control registers dccr 27-13 dcwr 27-13 iccr 27-13 sgr 27-13 skr 27-13 sler 27-14 regions 24-1 compression register (skr) 27-13 guarded architectural overview 24-25 register (sgr) 27-13 speculative accesses to 24-25 little endian register (sler) 27-14 synchronization 24-31 stswi 28-140 stswx 28-141 stw 28-143 stwbrx 28-144 stwcx. 28-145 stwu 28-146 stwux 28-147 stwx 28-148 sub 28-149 28-149 subc 28-150 subc. 28-150 subco 28-150 subco. 28-150 subf 28-149 subf. 28-149 subfc 28-150 subfc. 28-150 subfco 28-150 subfco. 28-150 subfe 28-151 subfe. 28-151 subfeo 28-151 subfeo. 28-151 subfic 28-152 subfme 28-153 subfme. 28-153 subfmeo 28-153 subfmeo. 28-153 subfo 28-149 subfo. 28-149 subfze 28-154 28-154 subfzeo 28-154 subfzeo. 28-154 subi 28-10 subic 28-11 subic. 28-12 subis 28-13 subo 28-149 subo. 28-149 supervisor state 24-27 supplemental documentation xxxvii sync 28-155 synchronization architectural references 24-28 context 24-29 execution 24-30 storage 24-31 synchronous interrupts, defined 11-9 system call exception 11-25 t target command codes 3-1 tbhi 29-41 tbhu 29-42 tblo 29-43 tblrehi 28-158 tblrelo 28-158 tblu 29-44 tblwehi 28-162 tblwelo 28-162 tck 18-10, 20-7 tcr 11-36, 29-45 tdi to 208-pin pqfp package iop 480 data book r2.0 index-34 ? 2000 plx technology, inc. all rights reserved. tdi 18-10, 20-7 tdo 18-10, 20-7 terms and definitions xxxviii time base 11-30 timer facilities overview 11-28 timers fit 11-33 fixed interval timer 11-33 pit 11-32 programmable interval timer 11-32 tcr 11-36 timer control register 11-36 timer status register 11-35 tsr 11-35 watchdog 11-33 timing diagrams configuration cycles 4-8 ? 5-9 cpu bootup cycle 6-3 direct master operation 5-10 ? 5-18 direct slave operation 4-12 ? 4-28 local bus 2-7 ? 2-9, 2-14 reference list 21-1 tlb fields 27-3 hardware 27-2 instruction 27-5 consistency 27-6 shadow 27-5 consistency 27-6 unified 27-2 tlbia 28-156 tlbre 28-157 tlbsx 28-159 tlbsx. 28-159 tlbsync 28-160 tlbwe 28-161 tms 18-10, 20-7 transfer, unaligned data pipe architecture 1-2 dma 7-13 local bus master 2-15, 4-7, 7-8, 7-13 timing diagram 7-22 trap 28-165 trdy# 18-5, 20-8 trst# 18-11, 20-7 ts1 18-2, 18-6 ts1# 20-7 ts2 18-2, 18-6, 20-7 ts3 18-2, 18-7, 20-7 ts4 18-2, 18-7, 20-7 ts5 18-3, 18-7, 20-7 ts6 18-11, 20-7 tsr 11-35, 29-46 tw 28-163 tweq 28-165 tweqi 28-168 twge 28-165 twgei 28-168 twgle 28-165 twgt 28-165 twgti 28-168 twi 28-166 twle 28-165 twlei 28-168 twlgei 28-168 twlgt 28-165 twlgti 28-168 twlle 28-165 twllei 28-168 twllt 28-165 twllti 28-168 twlng 28-165 twlngi 28-168 twlnl 28-165 twlnli 28-168 twlt 28-165 twlti 28-168 twne 28-165 twnei 28-168 twng 28-165 twngi 28-168 twnl 28-165 twnli 28-168 208-pin pqfp package materials 20-3 mechanical specifications 20-1 pinout 20-2 printed circuit board 20-3 properties 20-3 225-pin pbga package to xori iop 480 data book r2.0 ? 2000 plx technology, inc. all rights reserved. index-35 index 225-pin pbga package layout 20-6 materials 20-9 mechanical specifications 20-4 pinout 20-7 ? 20-8 printed circuit board 20-9 properties 20-9 suggested land pattern for pcb layout 20-5 tx 18-3, 20-7 txd 18-7 type 0 12-16 access internal register 17-1 advanced data pipe architecture 1-2, 1-3 built-in self test interrupt 11-4 configuration cycles 1-2, 1-3, 1-5, 4-1, 5-1, 5-5, 17-1, 17-36 example 5-5 timing diagram 5-16 decode, direct master memory 5-1 decode, i/o 5-1 dmcfga 17-36 internal registers, pci bus access to 4-1 pci host embedded systems 1-5 type 1 12-16 access, internal register 17-1 advanced data pipe architecture 1-2, 1-3 configuration cycles 1-2 configuration cycles 1-3, 1-5, 5-1, 5-5, 17-1, 17-36 timing diagram 5-17 decode, direct master memory 5-1 decode, i/o 5-1 dmcfga 17-36 pci host embedded systems 1-5 types, data 24-11 u uartba 17-37 unaligned transfer data pipe architecture 1-2 dma 7-13 local bus master 2-15, 4-7, 7-8, 7-13 timing diagram 7-22 units, memory management 23-5 unused pins 18-1, 18-11 user mode 24-27 user0 18-2, 18-15, 20-7 user1 18-2, 18-15, 20-7 user2 18-3, 18-18, 20-8 user3 18-2, 18-13, 20-7 user4 18-2, 18-13, 20-7 v vdd 18-11, 20-7, 20-8 vdda 18-10, 20-7 vital product data (vpd) 15-1 ? 15-4 access to serial eeprom 1-4, 10-3 data pipe architecture 1-3 overview 15-1 random read and write area 15-2 registers 15-1, 17-1, 17-3, 17-20 sequential read area 15-2 serial eeprom partitioning 15-1 vpd_cap 17-20 vpd_data 17-20 vss 18-11, 20-7, 20-8 w wait# 18-16, 20-8 watchdog timer 11-33 watchdog timer exception 11-27 wimg, virtual mode control 27-4 write-back/write-through 1-2, 23-4, 23-5, 25-1, 25-4, 25-5, 27-4 dcwr 29-14 ? 29-15 wrtee 28-169 wrteei 28-170 x xer 24-5, 29-47 x-form a-39 xfx-form a-40 xl-form a-40 xo-form a-40 xor 28-171 xori 28-172 zone fault to zpr iop 480 data book r2.0 index-36 ? 2000 plx technology, inc. all rights reserved. z zone fault 11-21 zpr register 29-48 zone protection 27-10 |
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